JP2012256806A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit an occurrence of a short circuit between a gate electrode and a contact.SOLUTION: A semiconductor device comprises: a first diffusion region (3) provided on a substrate (2); a second diffusion region (3) provided on the substrate (2); a first contact (11) connected to the first diffusion region (3); a second contact (11) connected to the second diffusion region (3); a channel region provided between the first diffusion region (3) and the second diffusion region (3); and a gate electrode (5) provided on the channel region via a gate insulation film (6). The gate electrode (5) includes a first region (A-A') sandwiched by the first contact (11) and the second contact (11) and a second region (B-B') different from the first region. The first region (A-A') includes a first lateral face on the first contact side and a second lateral face on the second contact side. The first lateral face slants in a direction away from the first contact. The second lateral face slants in a direction away from the second contact.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a field effect transistor and a method for manufacturing the semiconductor device.

  Most of the currently popular semiconductor devices include a field effect transistor. A typical transistor includes a diffusion layer functioning as a source or a drain and a gate electrode. The diffusion layer is connected to the wiring via a contact. With the demand for miniaturization and high integration of semiconductor devices, it has become necessary to reduce the distance between the contact and the gate electrode. By reducing the distance between the contact and the gate electrode, the possibility that the gate electrode and the contact are short-circuited increases. A technique for preventing a short circuit between a gate electrode and a contact is known (for example, see Patent Document 1).

  Patent Document 1 discloses a technique related to a method for manufacturing a semiconductor device, which can improve the embedding property of an interlayer insulating film and improve a short-circuit prevention margin. In that technology, a gate whose upper part is covered with a gate upper insulating film is formed on a semiconductor substrate, and after the insulating film is formed on the entire surface, the entire shape is etched back to form the upper shape on the side surface of the gate upper insulating film and gate Forms a tapered sidewall inclined at 5 ° to 30 ° from the vertical direction. Then, a first interlayer insulating film is formed on the entire surface, only the first interlayer insulating film is planarized by CMP, and the first interlayer insulating film has a higher polishing selectivity than the gate upper insulating film. To flatten the first interlayer insulating film, the gate upper insulating film, and the sidewalls. After that, a second interlayer insulating film is formed on the entire surface, and a contact hole is formed on the first interlayer insulating film and the second interlayer insulating film by lithography so as to cover the upper part of the side wall where the gate side wall becomes flat. Form. The contact hole is filled with a conductive material to form a contact pad.

JP 2006-237082 A

  When manufacturing a semiconductor device, misalignment, gate dimension / contact dimension thickening, contact shape distortion, and the like may occur due to manufacturing variations at the time of processing in a lithography process. For example, in the technique described in Patent Document 1, when the misalignment of the contact hole 16 occurs due to manufacturing variations at the time of processing by the lithography process, when the distance between the gate electrode and the contact becomes narrow, Insulation breakdown (short circuit between contact and gate electrode) may occur due to various manufacturing variations.

  In general transistors, in order to prevent a short circuit between the contact and the gate electrode, measures such as reducing the contact size or strengthening the contact alignment management are considered. However, when the contact size is reduced, the contact resistance increases. In addition, if the contact management is strengthened, the equipment capacity will be reduced due to the deterioration of the re-construction rate.

  A problem to be solved by the present invention is a technique for suppressing the occurrence of a short circuit between a gate electrode and a contact due to the shortening of the distance between the gate electrode and the contact while suppressing the occurrence of fluctuations in transistor characteristics. Is to provide.

  [Means for Solving the Problems] will be described below using the numbers used in [DETAILED DESCRIPTION]. These numbers are added to clarify the correspondence between the description of [Claims] and [Mode for Carrying Out the Invention]. However, these numbers should not be used to interpret the technical scope of the invention described in [Claims].

  In order to solve the above problems, a first diffusion region (3) provided in the substrate (2), a second diffusion region (3) provided in the substrate (2), and a first diffusion region (3) The first contact (11) connected to the second diffusion region (3), the second contact (11) connected to the second diffusion region (3), and provided between the first diffusion region (3) and the second diffusion region (3). A semiconductor device is provided which includes the channel region thus formed and a gate electrode (5) provided on the channel region via a gate insulating film (6). The gate electrode (5) includes a first region (AA ′) sandwiched between the first contact (11) and the second contact (11), and a second region (BB ′) different from the first region. With. The first region (A-A ′) includes a first side surface on the first contact side and a second side surface on the second contact side. The first side surface is inclined in a direction away from the first contact. The second side surface is inclined in a direction away from the second contact.

  According to the invention disclosed in the present application, it is possible to suppress the occurrence of a short circuit between the gate electrode and the contact due to the shortening of the distance between the gate electrode and the contact accompanying the miniaturization of the semiconductor circuit. Therefore, if a typical effect obtained thereby is briefly described, it is possible to suppress the occurrence of yield reduction.

FIG. 1 is a plan view illustrating the configuration of the semiconductor device 1 of this embodiment. FIG. 2A is a cross-sectional view illustrating the configuration of the A-A ′ cross section of the semiconductor device 1 of this embodiment. FIG. 2B is a cross-sectional view illustrating a configuration of the B-B ′ cross section of the semiconductor device 1 of this embodiment. FIG. 3A is a plan view illustrating the first step in the process of processing the gate electrode of the semiconductor device 1. FIG. 3B is a cross-sectional view illustrating a first step in the process for processing the gate electrode of the semiconductor device 1. FIG. 4A is a plan view illustrating the second stage of the processing step of the gate electrode of the semiconductor device 1. FIG. 4B is a cross-sectional view illustrating a second step in the process for processing the gate electrode of the semiconductor device 1. FIG. 4C is a cross-sectional view illustrating a second step in the process for processing the gate electrode of the semiconductor device 1. FIG. 5A is a plan view illustrating a third step in the process of processing the gate electrode of the semiconductor device 1. FIG. 5B is a cross-sectional view illustrating a third step in the process for processing the gate electrode of the semiconductor device 1. FIG. 6A is a plan view illustrating the fourth step in the process of processing the gate electrode of the semiconductor device 1. FIG. 6B is a cross-sectional view illustrating a fourth stage in the process of processing the gate electrode of the semiconductor device 1. FIG. 7A is a plan view illustrating the fifth stage of the processing step of the gate electrode of the semiconductor device 1. FIG. 7B is a cross-sectional view illustrating a fifth step in the process for processing the gate electrode of the semiconductor device 1. FIG. 8A is a cross-sectional view illustrating the configuration of the semiconductor device 1 of this embodiment. FIG. 8B is a cross-sectional view illustrating the configuration of the general semiconductor device 101 of this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a plan view illustrating the configuration of the semiconductor device 1 of this embodiment. In the plan view of FIG. 1, an interlayer insulating film is omitted in order to facilitate understanding of the semiconductor device 1 of the present embodiment. In the semiconductor device 1 of this embodiment, the periphery of the element is surrounded by the element isolation region 9. The semiconductor device 1 includes a diffusion layer that functions as a source or a drain and a gate electrode. A diffusion layer silicide 7 is formed on the diffusion layer. A gate silicide 8 is formed on the gate electrode. A contact 11 is formed on part of the diffusion layer silicide 7. The side surface of the gate electrode under the gate silicide 8 is covered with a sidewall insulating film 13. In the semiconductor device 1 of the present embodiment, the region of the gate electrode sandwiched between the contacts 11 (gate electrode adjacent to the contact) is selectively formed in a tapered shape. As shown in FIG. 1, the sidewall insulating film 13 in that region is removed. Further, since the gate electrode 5 in the region is formed in a tapered shape, a part of the gate electrode 5 is exposed when viewed from above.

  2A and 2B are cross-sectional views illustrating the cross-sectional configuration of the semiconductor device 1 of this embodiment. FIG. 2A illustrates an A-A ′ cross section in FIG. 1. FIG. 2B illustrates the B-B ′ cross section in FIG. 1. Referring to FIG. 2A, the semiconductor device 1 includes a source / drain diffusion layer region 3 formed in the silicon substrate 2 and an extension region 4 in the A-A ′ cross section. A diffusion layer silicide 7 is provided on the source / drain diffusion layer region 3. The semiconductor device 1 includes a gate electrode 5. The gate electrode 5 is formed on the silicon substrate 2 via the gate insulating film 6. A gate silicide 8 is formed on the gate electrode 5. The semiconductor device 1 is covered with an interlayer insulating film 12. A contact 11 connected to the diffusion layer silicide 7 of the semiconductor device 1 penetrates the interlayer insulating film 12. The lower end of the contact 11 is connected to the source / drain diffusion layer region 3 through the diffusion layer silicide 7, and the upper end is connected to a wiring (not shown).

  As shown in FIG. 2A, in the A-A ′ cross section, the gate electrode 5 is processed so that the cross section has a tapered shape. Thereby, the distance between the contact and the gate electrode (upper part) can be increased, and a short circuit between the contact and the gate electrode can be suppressed. Referring to FIG. 2B, the semiconductor device 1 includes a gate electrode 5 having a substantially rectangular cross section in the B-B ′ cross section. In the B-B ′ cross section, the side surface of the gate electrode 5 is covered with the sidewall insulating film 13.

  Below, the manufacturing method of the semiconductor device 1 of this embodiment is demonstrated. In the following description of the manufacturing method, a detailed description of the process prior to the process of processing the gate electrode close to the contact is omitted. FIG. 3A is a plan view illustrating the state of the semiconductor structure in the first stage of the process of processing the gate electrode of the semiconductor device 1 of this embodiment. In this first stage, the semiconductor structure is covered with the interlayer insulating film 12. In the following description, in order to facilitate understanding of the configuration of the semiconductor structure in the manufacturing process, the region covered with the interlayer insulating film 12 is made visible.

  In the first stage, the source / drain diffusion layer region 3, the gate electrode 5, the diffusion layer silicide 7, the gate silicide 8 and the sidewall insulating film 13 are formed in a region surrounded by the element isolation region 9 formed on the silicon substrate. A semiconductor device 1 is formed. FIG. 3B is a cross-sectional view illustrating a cross section of the semiconductor structure in the first stage. FIG. 3B illustrates the structure of the A-A ′ cross section and the B-B ′ cross section of FIG. 3A. As shown in FIG. 3B, in the first stage, there is no difference between the structure of the A-A ′ section and the structure of the B-B ′ section.

  FIG. 4A is a plan view illustrating a second stage of the gate electrode processing step. As shown in FIG. 4A, a resist 21 is applied over the entire surface of the interlayer insulating film 12. In the following description, in order to facilitate understanding of the structure of the semiconductor structure during the manufacturing process, the region covered with the resist 21 is visualized. After the resist 21 is formed, a region where the contact 11 is formed is specified in a later step, and the resist 21 on the gate electrode adjacent to the contact 11 is selectively removed to form the opening 22.

  FIG. 4B is a cross-sectional view illustrating a configuration of the A-A ′ cross section in the second stage. As shown in FIG. 4B, in the A-A ′ cross section, an opening 22 is formed in the resist 21 to expose a part of the interlayer insulating film 12. FIG. 4C is a cross-sectional view illustrating a configuration of the B-B ′ cross section in the second stage. The semiconductor structure in the B-B ′ cross section maintains the first stage state. The resist 21 protects the surface of the interlayer insulating film 12.

  FIG. 5A is a plan view illustrating a third stage of the gate electrode processing step. As shown in FIG. 5A, in the third stage, the interlayer insulating film 12 exposed by the opening 22 and the sidewall insulating film 13 under the interlayer insulating film 12 are removed to open the opening 23. Form. Thereby, a part of the gate silicide 8 and a part of the extension region 4 are exposed.

  FIG. 5B is a cross-sectional view illustrating a configuration of the A-A ′ cross section in the third stage. As shown in FIG. 5B, part of the gate silicide 8 and part of the side surface of the gate electrode 5 are exposed in the third stage.

  FIG. 6A is a plan view illustrating a fourth stage of the gate electrode processing step. As shown in FIG. 6A, in the fourth stage, the exposed gate silicide 8 is selectively removed, and the gate electrode 5 under the gate silicide 8 is etched so that the cross section becomes tapered. To form.

  FIG. 6B is a cross-sectional view illustrating a configuration of the A-A ′ cross section in the fourth stage. As shown in FIG. 6B, in the fourth stage, the gate electrode 5 is processed so that the length in the gate length direction becomes shorter as it goes upward.

  FIG. 7A is a plan view illustrating the fifth stage of the gate electrode processing step. As shown in FIG. 7A, in the fifth stage, after the resist 21 is removed, the opening 23 is filled with the same material as the interlayer insulating film 12. FIG. 7B is a cross-sectional view illustrating a configuration of the A-A ′ cross section in the fifth stage. As shown in FIG. 7B, in the fifth stage, the side surface of the gate electrode 5 processed so as to have a tapered cross section is covered with an interlayer insulating film 12.

  Thereafter, a contact 11 is formed in the vicinity of the tapered gate electrode 5. By selectively shortening the length in the gate length direction of the upper part of the gate electrode in the region close to the contact by dry etching, the distance between the contact and the gate electrode (upper part) can be further increased. Thereby, a short circuit between the contact and the gate electrode can be suppressed.

[Comparative example]
Below, the comparative example of this embodiment is demonstrated. 8A and 8B are cross-sectional views illustrating the configuration of the semiconductor device 1 of this embodiment and a general semiconductor device 101 when misalignment occurs in the step of forming a contact. FIG. 8A illustrates a cross-sectional configuration of the semiconductor device 1 of this embodiment. FIG. 8B illustrates a configuration of a general semiconductor device 101. In the step of forming the contact, when misalignment occurs, in the semiconductor device 1 of the present embodiment, the distance between the contact and the gate electrode is the distance L1. In the general semiconductor device 101, the distance between the contact and the gate electrode is the distance L2. As shown in FIGS. 8A and 8B,
Distance L1> Distance L2
In the semiconductor device 1 according to the present embodiment, the distance between the contact and the gate electrode (upper part) can be further increased, so that a short circuit between the contact and the gate electrode can be suppressed.

  The embodiment of the present invention has been specifically described above. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Silicon substrate 3 ... Source / drain diffused layer region 4 ... Extension region 5 ... Gate electrode 6 ... Gate insulating film 7 ... Diffusion layer silicide 8 ... Gate silicide 9 ... Element isolation region 11 ... Contact 12 ... Interlayer insulation Film 13 ... Side wall insulating film 21 ... Resist 22 ... Opening 23 ... Opening L1 ... Distance L2 ... Distance

Claims (7)

A first diffusion region provided on the substrate;
A second diffusion region provided on the substrate;
A first contact connected to the first diffusion region;
A second contact connected to the second diffusion region;
A channel region provided between the first diffusion region and the second diffusion region;
A gate electrode provided on the channel region via a gate insulating film,
The gate electrode is
A first region sandwiched between the first contact and the second contact;
A second region different from the first region,
The first region is
A first side surface on the first contact side;
A second side surface on the second contact side,
The first side surface is
Inclining away from the first contact;
The second side surface is
A semiconductor device inclined in a direction away from the second contact. The semiconductor device according to claim 1,
The first region of the gate electrode is
A bottom surface of a first region corresponding to an interface between the gate insulating film and the gate electrode;
A first region upper surface,
The length of the bottom surface of the first region in the gate length direction is
A semiconductor device longer than a length of the upper surface of the first region in the gate length direction. The semiconductor device according to claim 2,
The length of the first region in the gate length direction is:
A semiconductor device that monotonously decreases from the bottom surface of the first region to the top surface of the first region. The semiconductor device according to claim 3.
The second region of the gate electrode is
A bottom surface of a second region corresponding to an interface between the gate insulating film and the gate electrode;
A second region upper surface,
The length of the second region of the gate electrode in the gate length direction is:
A semiconductor device having a substantially constant length from the bottom surface of the second region to the top surface of the second region. A method for manufacturing a semiconductor device comprising: a first diffusion region provided on a substrate with a channel region interposed therebetween; a second diffusion region; and a gate electrode provided on the receiving of the channel region via a gate insulating film,
(A) identifying a region in which a first contact connected to the first diffusion region and a second contact connected to the second diffusion region are formed;
(B) identifying a region of the gate electrode sandwiched between the first contact and the second contact as a first region;
(C) forming an inclination in a direction away from the first contact on the first side surface of the first region on the first contact side, and forming a second side surface on the second contact side of the first region on the second side surface of the first region; A method of manufacturing a semiconductor device, comprising the step of forming an inclination in a direction away from two contacts. In the manufacturing method of the semiconductor device according to claim 5,
The step (c) includes:
When the bottom surface of the first region corresponding to the interface between the gate insulating film and the gate electrode in the first region and the top surface of the first region as the top surface of the first region,
A method of manufacturing a semiconductor device, comprising: forming the gate electrode such that a length of the bottom surface of the first region in a gate length direction is longer than a length of the top surface of the first region in the gate length direction. In the manufacturing method of the semiconductor device according to claim 6,
The step (c) includes:
A method of manufacturing a semiconductor device, comprising: forming the gate electrode so that the length of the first region in the gate length direction monotonously decreases from the bottom surface of the first region to the top surface of the first region.

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