KR20100127673A - Method for fabricating contact plug - Google Patents

Method for fabricating contact plug Download PDF

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Publication number
KR20100127673A
KR20100127673A KR1020090046203A KR20090046203A KR20100127673A KR 20100127673 A KR20100127673 A KR 20100127673A KR 1020090046203 A KR1020090046203 A KR 1020090046203A KR 20090046203 A KR20090046203 A KR 20090046203A KR 20100127673 A KR20100127673 A KR 20100127673A
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KR
South Korea
Prior art keywords
insulating film
contact plug
trench
contact
film
Prior art date
Application number
KR1020090046203A
Other languages
Korean (ko)
Inventor
유태준
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090046203A priority Critical patent/KR20100127673A/en
Publication of KR20100127673A publication Critical patent/KR20100127673A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for forming a contact plug is provided to constantly maintain critical-dimension by simultaneously arranging isolated contact plugs and dense contact plugs on a layout. CONSTITUTION: An insulating layer(205) is formed on a wafer(200). A first region(A) and a second region(B) are defined on the insulating layer. Dense contact plugs are formed in the first region. Isolated contact plugs are formed in the second region. A first trench is formed in the first region using a first mask. A buried insulating layer(210) buries the first trench. The etching selectivity of the buried insulating layer is different from that of the insulating layer. A second trench is formed in the second region using a second mask.

Description

Method for fabricating contact plug}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a method for forming a contact plug.

As the degree of integration of semiconductor devices increases, DRAMs having high capacities (DRAMs) are used. The DRAM device includes a memory cell region for storing information data in the form of charge and a peripheral circuit region for inputting / outputting data. In the process of manufacturing a semiconductor device, contact plugs are used to implement circuit patterns on a semiconductor substrate and to electrically connect respective circuit patterns. The contact plugs are made of different materials according to the type of circuit pattern to be connected, and the density of the patterns constituting the contact plugs is also relatively dense pattern or a gap between the patterns arranged by dense spacing between the patterns. Widely arranged isolation patterns (isolation patterns) are made different.

1 is a view showing a layout of a general contact plug. FIG. 2 is a cross-sectional view of FIG. 1 cut out in the X-X 'direction and the Y-Y' direction.

1 and 2, when fabricating a semiconductor device, densities of the first contact plugs 115 and the second contact plugs 120 connected to the circuit patterns are designed differently according to the type of the circuit pattern. . In order to implement the first contact plug 115 and the second contact plug 120 having different densities in the same space, reticles having different shapes must be manufactured. In other words, two reticles are required. Next, an exposure process and an etching process for disposing a reticle on a wafer and transferring a desired pattern, and also two processes each using reticles containing the shapes of the first contact plug 115 and the second contact plug 120. Should be. However, due to the difference in density between the first and second contact plugs 115 and 120, portions having different sizes of spaces between the contact plugs may occur according to the X-X'-axis direction or the Y-Y'-axis direction. . Here, the parts not described in the drawings are the substrate 100, the device isolation layer 105, and the interlayer insulating layer 110.

In particular, in the case of the second contact plug 115, a dense pattern is disposed in one direction, and an isolation pattern having a relatively lower density than the dense pattern is disposed in the other direction. As such, when the dense pattern and the isolated pattern are all disposed on one layout, it is difficult to maintain a uniform critical width (CD).

Accordingly, in order to maintain a uniform line width, an assist pattern may be inserted into a layout in which both the first contact plug 110 and the second contact plug 115 are disposed to maintain the CD uniformity. Research is ongoing but there are limitations. Therefore, there is a need for a method capable of keeping the line width uniform when forming contact plugs having different densities.

An object of the present invention is to provide a method for forming a contact plug that can be formed to maintain a uniform line width when an isolated contact plug and a dense contact plug are disposed together in the process of manufacturing the contact plug.

A method for forming a contact plug according to the present invention includes forming an insulating film on a wafer; Forming a first trench using a first mask in which an isolated contact hole layout is designed on a first region of the insulating layer; Filling the first trench with a buried insulating film having a different etching selectivity from the insulating film; Forming a second trench on the second region of the insulating layer using a second mask in which a dense contact hole layout is designed; Filling the second trench with a first contact material film; Forming a third trench of the same width as the second trench by using the second mask in the buried insulating film; Filling the third trench with a second contact material film; And grinding the first contact material layer and the second contact material layer to form a first contact plug and a second contact plug.

In the present invention, it is preferable that the insulating film is formed by including an oxide film, and the buried insulating film is formed by including a nitride film.

The first contact material layer may be formed of polysilicon, and the second contact material layer may be formed of tungsten.

The second contact plug is formed in a shape surrounded by the buried insulating film.

According to the present invention, when the isolated contact plug and the dense contact plug are arranged together on the layout, the line width can be kept uniform. In addition, the layout of the isolated contact plug and the dense contact plug may be designed to be arranged at equal intervals, and the contact plug may be formed using materials having different etching selectivities.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

3 to 12 are views for explaining a method for forming a contact plug according to an embodiment of the present invention.

Referring to FIG. 3, an insulating film 205 is formed on the wafer 200. On the wafer 200, a first region A in which a dense contact hole is to be formed and a second region B in which an isolation contact hole is to be formed are defined. The insulating film 205 may be formed including an oxide film. Next, a resist film is applied on the wafer 200, and the first mask 300 having the layout of FIG. 4 and the exposure equipment are subjected to a first lithography process including an exposure and development process to partially cover the surface of the insulating film 205. A first resist film pattern 207 is formed to expose the film. 3 and 4, the first mask 300 includes a first opening 305 that exposes a portion corresponding to the first region A of the wafer 200, and includes a second region ( B) is designed to block layout.

Referring to FIG. 5, an exposed portion of the insulating layer 205 is etched using the first resist layer pattern 207 as an etch mask to form a first trench 209 that exposes a portion of the surface of the wafer 200. Subsequently, a buried insulating film 210 is formed on the insulating film 205 to fill all of the first trenches 209. The buried insulating film 210 is formed of a material having a different etching selectivity from the insulating film 205, for example, a nitride film. Next, the planarization process is performed, and the buried insulating film 210 is polished to a height equivalent to that of the surface of the insulating film 205. Here, the planarization process may be performed by a chemical mechanical polishing (CMP) method.

Referring to FIG. 6, a resist film is coated on the insulating film 205 and the buried insulating film 210, and the second mask 310 having the layout of FIG. 7 and a second process including an exposure and development process using an exposure apparatus. The lithography process is performed to form a second resist film pattern 215 exposing a portion of the surface of the insulating film 205. Here, the second mask 310 is designed in a layout including a second opening 315 exposing a portion corresponding to the second region B of the wafer. Here, the second opening 315 is designed in a pattern layout that is relatively denser than the first opening 305.

Referring to FIG. 8, an exposed portion of the insulating layer 205 is etched using the second resist layer pattern 215 as an etching mask to form a second trench 217 that exposes a portion of the surface of the wafer 200. The insulating layer 205 performs an etching process using an etching source for selectively etching an oxide film. Therefore, the buried insulating film 210 is not affected by the etching process by the etching selectivity of the nitride film and the oxide film.

Next, a first contact material film 220 is formed on the insulating film 205 and the buried insulating film 210 to fill all of the second trenches 217. The first contact material layer 220 may be formed of a conductive material to electrically connect the circuit pattern, and may include a polysilicon layer. The first contact material layer 220 may have a multilayer structure in which one or more polysilicon layers are stacked. Next, a planarization process is performed on the first contact material film 220 to be polished to a level equivalent to the surface of the insulating film 205. Here, the planarization process may be performed by chemical mechanical polishing (CMP) method.

Referring to FIG. 9, a resist film 223 is coated on the insulating film 205 and the buried insulating film 210. Next, a third lithography process including an exposure and development process is performed using the second mask 310 and exposure equipment of FIG. 7. Here, the second mask 310 is designed in a layout including a second opening 315 exposing a portion corresponding to the second region B of the wafer. Here, the second opening 315 is designed in a pattern layout that is relatively denser than the first opening 305. In this tertiary lithography process, a third resist film pattern (not shown) for exposing the buried insulating film 210 and a portion of the surface of the insulating film 205 by the size of the second opening 315 is formed.

Referring to FIG. 10, a third trench 225 exposing the surface of the wafer 200 is formed in the buried insulating film 210 by an etching process using the third resist layer pattern as an etching mask. The etching process is performed using an etching source having a higher etching selectivity of the nitride film than the oxide film. Here, when the overlay of the second mask 310 is exactly matched, the first contact material film 220 formed in the insulating film 205 is recessed by an etching selectivity with the nitride film. In addition, when the second mask 310 is moved away from the target overlay, the insulating layer 205 is also etched to be relatively formed on the first contact material layer 220 and the insulating layer 205 than the third trench 225. Low depth groove 230 is formed.

Referring to FIG. 11, a second contact material layer 235 is formed on the insulating layer 205 and the buried insulating layer 210 to fill all of the third trenches 225. The second contact material film 235 may be formed of a metal material, and may form a tungsten (W) film. The second contact material film 235 also fills the insulating film 205 and the groove 230 formed on the first contact material film 220.

Referring to FIG. 12, a planarization process is performed on the second contact material layer 235 to form a first contact plug 240 and a second contact plug 245. The planarization process is performed until the second contact material layer 235 filling the groove 230 is removed. In this planarization process, the first contact plug 240 is formed on the first region A of the wafer 200, and the second contact plug 245 is formed on the second region B. Here, the planarization process may be performed by chemical mechanical polishing (CMP) method. Here, the second contact plug 245 is formed in a shape surrounded by the buried insulating film 210.

In the method of forming a contact plug according to the present invention, a buried insulating film having a high etch selectivity is formed in a region where an isolated contact plug is to be formed, and then two exposure processes are performed using a mask of a dense contact plug, thereby providing a gap between the contact plugs. You can design different layouts at equal intervals. In addition, by maintaining the etching selectivity differently, it is possible to form a compact contact plug and a relatively isolated contact plug. In addition, if the contact plug material type is different, it can be applied without affecting each material.

1 illustrates a general contact plug layout.

FIG. 2 is a cross-sectional view of FIG. 1 cut out in the X-X 'direction and the Y-Y' direction.

3 to 12 are views for explaining a method for forming a contact plug according to an embodiment of the present invention.

Claims (5)

Forming an insulating film on the wafer; Forming a first trench using a first mask in which an isolated contact hole layout is designed on a first region of the insulating layer; Filling the first trench with a buried insulating film having a different etching selectivity from the insulating film; Forming a second trench on the second region of the insulating layer using a second mask in which a dense contact hole layout is designed; Filling the second trench with a first contact material film; Forming a third trench of the same width as the second trench by using the second mask in the buried insulating film; Filling the third trench with a second contact material film; And And grinding the first contact material layer and the second contact material layer to form a first contact plug and a second contact plug. The method of claim 1, And forming an insulating film including an oxide film. The method of claim 1, And a buried insulating film including a nitride film. The method of claim 1, Wherein the first contact material layer is formed of polysilicon and the second contact material layer is formed of tungsten. The method of claim 1, And forming the second contact plug in a shape surrounded by the buried insulating film.
KR1020090046203A 2009-05-26 2009-05-26 Method for fabricating contact plug KR20100127673A (en)

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Application Number Priority Date Filing Date Title
KR1020090046203A KR20100127673A (en) 2009-05-26 2009-05-26 Method for fabricating contact plug

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Application Number Priority Date Filing Date Title
KR1020090046203A KR20100127673A (en) 2009-05-26 2009-05-26 Method for fabricating contact plug

Publications (1)

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KR20100127673A true KR20100127673A (en) 2010-12-06

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153479B2 (en) 2013-03-11 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of preventing a pattern collapse

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153479B2 (en) 2013-03-11 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of preventing a pattern collapse
US9502287B2 (en) 2013-03-11 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of preventing pattern collapse
US10515895B2 (en) 2013-03-11 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of preventing pattern collapse
US11043453B2 (en) 2013-03-11 2021-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of preventing pattern collapse

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