KR101545682B1 - 고속의 주변 상호연결 버스를 통한 비디오 렌더링 - Google Patents

고속의 주변 상호연결 버스를 통한 비디오 렌더링 Download PDF

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Publication number
KR101545682B1
KR101545682B1 KR1020107014602A KR20107014602A KR101545682B1 KR 101545682 B1 KR101545682 B1 KR 101545682B1 KR 1020107014602 A KR1020107014602 A KR 1020107014602A KR 20107014602 A KR20107014602 A KR 20107014602A KR 101545682 B1 KR101545682 B1 KR 101545682B1
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South Korea
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graphics
memory
display
processor
graphics subsystem
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Korean (ko)
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KR20100114496A (ko
Inventor
제프리 쳉
테리 라비올레
제임스 후앙
로버트 자브르지키
제이슨 롱
시앙쿠안 웽
샤샤 마린코빅
필 무마흐
밍웨이 치엔
마이클 트레시더
로멘 솔트체프
조지 시
이오우리 리츠마노프
Original Assignee
에이티아이 테크놀로지스 유엘씨
에이티아이 인터내셔널 에스알엘
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G09G5/397—Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
  • Information Transfer Systems (AREA)
KR1020107014602A 2007-11-30 2008-12-01 고속의 주변 상호연결 버스를 통한 비디오 렌더링 Active KR101545682B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/987,559 2007-11-30
US11/987,559 US20080143731A1 (en) 2005-05-24 2007-11-30 Video rendering across a high speed peripheral interconnect bus

Publications (2)

Publication Number Publication Date
KR20100114496A KR20100114496A (ko) 2010-10-25
KR101545682B1 true KR101545682B1 (ko) 2015-08-19

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KR1020107014602A Active KR101545682B1 (ko) 2007-11-30 2008-12-01 고속의 주변 상호연결 버스를 통한 비디오 렌더링

Country Status (6)

Country Link
US (1) US20080143731A1 (enExample)
EP (1) EP2225752B1 (enExample)
JP (1) JP5529748B2 (enExample)
KR (1) KR101545682B1 (enExample)
CN (2) CN101965610A (enExample)
WO (1) WO2009073617A1 (enExample)

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CN105389768B (zh) * 2015-10-21 2019-06-28 努比亚技术有限公司 图片处理方法及装置
JP2017097066A (ja) * 2015-11-19 2017-06-01 ルネサスエレクトロニクス株式会社 画像処理装置及び画像処理方法
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Also Published As

Publication number Publication date
EP2225752B1 (en) 2016-03-23
CN107845374A (zh) 2018-03-27
US20080143731A1 (en) 2008-06-19
JP5529748B2 (ja) 2014-06-25
WO2009073617A1 (en) 2009-06-11
JP2011509445A (ja) 2011-03-24
CN107845374B (zh) 2021-10-01
EP2225752A1 (en) 2010-09-08
KR20100114496A (ko) 2010-10-25
CN101965610A (zh) 2011-02-02

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