KR101543767B1 - Method For Forming Selective Emitter Of Solar Cell Solar Cell and Fabricating Method Thereof - Google Patents

Abstract

More particularly, the solar cell is formed on the entire surface of a first impurity semiconductor substrate, and has a high concentration doped region of the second impurity and a high concentration doped region of the second impurity. A second impurity semiconductor layer made of a lightly doped region of the second impurity and a front electrode formed on the heavily doped region of the second impurity in the second impurity semiconductor layer and a rear electrode formed on the rear surface of the first impurity semiconductor substrate, And the depth of the heavily doped region of the second impurity is deeper than the depth of the lightly doped region of the second impurity.

Solar cell, selective emitter, doped region, impurity, front electrode, rear electrode

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selective emitter of a solar cell,

The present invention relates to a solar cell having a selective emitter, a method of manufacturing the solar cell, and a method of forming a selective emitter of the solar cell.

In recent years, interest in environmentally friendly alternative energy has increased due to global environmental problems and resource depletion. One of the technologies that attracts people's attention in this situation is PV technology.

Solar cells that produce electricity using solar light are generally manufactured using silicon. Currently, commercially available single crystal Bulk silicon solar cells are not actively utilized because of high manufacturing cost and installation cost. In order to solve such a cost problem, researches on a solar cell using silicon have been actively conducted, and various attempts have been made to manufacture a high efficiency solar cell module.

Solar cells are the next generation of clean energy sources, and many studies have been conducted for decades. The solar cell can be divided into a solar cell that generates steam required to rotate the turbine using solar heat, and a solar cell that converts sunlight (photons) into electrical energy using the properties of a semiconductor. Among them, researches on a photovoltaic cell that converts light energy into electrical energy by using electrons and holes generated by absorbed photons are actively conducted. The solar cell is generally referred to as a solar cell. The characteristics required of the solar cell include high photoelectric conversion efficiency, low manufacturing cost, and short energy recovery years. And there is an economical effect in terms of the manufacturing cost by reducing the number of processes, and active research is under way.

Until now, as the material of the solar cell, a material of a Group IV family such as single crystal silicon, polycrystalline silicon, amorphous silicon, amorphous SiC, amorphous SiN, amorphous SiGe and amorphous SiSn or gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs) (InP), and compound semiconductors of II-VI group such as CdS, CdTe, Cu ₂ S and the like. The solar cell can be divided into a solar cell that generates steam required to rotate the turbine using solar heat, and a solar cell that converts sunlight (photons) into electrical energy using the properties of a semiconductor. Among them, researches on a photovoltaic cell that converts light energy into electrical energy by using electrons and holes generated by absorbed photons are actively conducted.

Among the solar cells, the silicon solar cell has a problem that the contact resistance between the silicon surface and the front electrode is high. Therefore, researches on an emitter for lowering the contact resistance between the silicon surface and the front electrode are actively conducted.

In addition, since the process of forming an emitter of a solar cell for providing a high efficiency solar cell in the conventional solar cell manufacturing process is complicated and pointed out as a problem in terms of time and cost, an improved technique is needed It is true.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a method of forming an optional emitter for lowering the contact resistance between an emitter and an electrode of a solar cell, and to provide a solar cell including such an optional emitter It has its purpose.

Another object of the present invention is to provide a solar cell with a high efficiency by manufacturing a solar cell using a simple and shortened process time of the emitter, which is different from the conventional selective emitter manufacturing process.

The technical objects to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical subjects which are not mentioned can be clearly understood by those skilled in the art from the description of the present invention .

In general, the structure of a solar cell has a hetero-junction structure of a p-type semiconductor and an n-type semiconductor like a diode, and carriers are separated by electrons charged with (+) and holes (+) due to incidence of sunlight, A difference occurs.

This is called a photovoltaic effect. In a p-type semiconductor and an n-type semiconductor constituting a solar cell, electrons are attracted toward the n-type semiconductor and holes are attracted toward the p-type semiconductor, And the potential difference is generated. When these electrodes are connected, power can be obtained.

The maximum value P _max of the output power of the solar cell is represented by the product of the output current Ip and the output voltage Vp and the photoelectric conversion efficiency η of the solar cell corresponds to the maximum value P _max of the output power, (S x I, S is the element area, and I is the intensity of the light irradiated to the solar cell).

Therefore, in order to increase the photovoltaic efficiency? Of the solar cell, it is necessary to increase the short-circuit current Isc or the open-circuit voltage Voc or increase the fill factor (FF) indicating the degree of the output current-voltage curve.

In recent years, research and development has been carried out in order to improve the absorption rate of sunlight and reduce the transfer resistance of carriers, thereby improving the efficiency. In order to reduce the contact resistance between the electrode and the semiconductor emitter layer, the structure of the emitter layer, Time is improving.

1 is a cross-sectional view of a solar cell including a selective emitter in which the structure of the emitter layer is changed according to the prior art. The p-type semiconductor substrate 101 and the n-type semiconductor layer 102 forming the pn heterojunction, An electrode 104, a BSF (Back Surface Field) layer 105 formed on the lower surface of the p-type semiconductor substrate 101, and a rear electrode 106.

The n-type semiconductor layer 102 is an emitter layer composed of a selective emitter layer which is formed to be thick in a region in contact with the electrode to reduce the contact resistance with the front electrode 104 and thinner than the region in contact with the electrode. Thus, this selective emitter structure reduces the contact resistance and reduces the ohmic resistance of the carrier and improves the lifetime of the carrier.

This selective emitter layer contributes to the efficiency by reducing the contact resistance between the electrode and the emitter layer. However, since the manufacturing process is added, the complex emitter layer and the over-production cost are required. Research is needed.

In order to solve these problems and achieve the above object, a solar cell according to an embodiment of the present invention is formed on the entire surface of a first impurity semiconductor substrate, and includes a heavily doped region of the second impurity and a lightly doped region of the second impurity A front electrode formed on the heavily doped region of the second impurity semiconductor layer; and a rear electrode formed on the rear surface of the first impurity semiconductor substrate. Wherein a depth of the heavily doped region of the second impurity is deeper than a depth of the lightly doped region of the second impurity.

In the present invention, the bonding interface between the first impurity semiconductor substrate and the second impurity semiconductor layer may be a concave-convex structure, and the shape and the shape of the concave and convex are not limited.

The heavily doped region of the second impurity and the lightly doped region of the second impurity may be formed on the entire surface of the first impurity semiconductor substrate so as to cross each other. However, the present invention is not limited thereto, 2 doped region of the second impurity and a low doped region of the second impurity may be formed in a predetermined space.

In the present invention, the depth of the lightly doped region of the second impurity may become deeper from the center of the lightly doped region toward the interface between the lightly doped region of the second impurity and the lightly doped region of the second impurity.

The center portion of the lightly doped region of the second impurity does not mean a specific point but is located at an interface between the heavily doped region of the second impurity and the lightly doped region of the second impurity, Quot; portion ".

In the present invention, the depth of the central portion of the lightly doped region of the second impurity may be 0.1 탆 to 0.2 탆, and the depth of the interface of the lightly doped region of the second impurity may be larger than the center portion depth and smaller than 0.8 탆. Therefore, the thickness or the depth of the lightly doped region of the second impurity can be formed to have a larger value at the interface with the heavily doped region of the second impurity at the center.

The first impurity in the present invention may be a p-type semiconductor impurity, and the second impurity may be an n-type semiconductor impurity, or vice versa. Refers to dopants of different types of impurity semiconductors, so that the solar cell of the present invention forms a pn hetero junction layer.

The n-type semiconductor impurity may be selected from the group consisting of Group 5 elements such as phosphorus (P), arsenic (As), and antimony (Sb).

In order to achieve the above object, a selective emitter forming method of a solar cell according to the present invention is a method for forming a selective emitter of a solar cell including a heavily doped region of a second impurity and a lightly doped region of a second impurity on the entire surface of a first impurity semiconductor substrate Applying a second impurity paste to a predetermined region on the first impurity semiconductor substrate in a heavily doped region of the second impurity through a step of heat treating the second impurity paste .

And the lightly doped region of the second impurity is formed in the remaining region where the heavily doped region of the second impurity is not formed on the first impurity semiconductor substrate.

In the present invention, the lightly doped region of the second impurity is formed simultaneously with the step of heat-treating the second impurity paste.

Also in the present invention, the lightly doped region of the second impurity may be formed by diffusion of the second impurity gas, wherein the second impurity gas is diffused into the second impurity paste, which is spontaneously vaporized from the applied second impurity paste, Impurity gas, or artificially implanted POCl ₃ gas during the manufacturing process of the solar cell.

In the present invention, the second impurity paste can be applied by a screen printing method or a printing method. However, the second impurity paste is not necessarily limited to these methods but can be applied to any known method capable of patterning a paste on a substrate.

In the present invention, the step of applying the second impurity paste and the step of heat-treating may be sequentially performed separately, but the present invention is not limited thereto and may be performed in one step. That is, the second impurity-based paste is patterned on the first impurity-type semiconductor substrate in the chamber which has already been set to a high temperature, so that the firing process can be performed simultaneously with the formation of the second impurity semiconductor layer.

The temperature of the heat treatment in the present invention is not particularly limited, but can be set at a temperature of 820 캜 to 950 캜 within 30 seconds to 10 minutes.

The method for manufacturing a solar cell of the present invention for achieving the above object is characterized by a process including a method for forming a selective emitter of the solar cell as described above.

The selective emitter formation method of the present invention can simplify the selective emitter formation process compared to the conventional method and can reduce the cost in terms of production cost.

According to the present invention, a selective emitter is formed on the front surface of a solar cell by applying a paste, thereby reducing the contact resistance between the electrode and the emitter layer, thereby providing a highly efficient solar cell.

In addition, since the present invention introduces a simple manufacturing process to form a selective emitter layer, the process time can be shortened and the cost of production of the solar cell can be reduced.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a method of forming a selective emitter of a solar cell according to an embodiment of the present invention.

Referring to FIG. 2, a method according to an embodiment of the present invention for laminating a selective emitter layer of a solar cell on a semiconductor substrate is illustrated.

That is, an n-type semiconductor layer 202 is formed on the p-type semiconductor substrate 201. An n-type impurity paste 210 is applied to a portion where the front electrodes are to be stacked on the n-type semiconductor layer to form a selective emitter layer As shown in FIG.

The region where the n-type impurity paste 210 is applied on the p-type semiconductor substrate 201 directly impregnates impurities into the substrate, and solid phase diffusion is induced. Therefore, the highly doped region 220 of the n-type impurity is formed on the p-type semiconductor substrate corresponding to the region to which the n-type impurity paste 210 is applied.

The remaining region of the p-type semiconductor substrate 201 not coated with the n-type impurity paste 210 is doped through the diffusion of the n-type impurity gas to form the lightly doped region 230 of the n-type impurity. That is, the lightly doped region 230 of the n-type impurity may be formed through gas phase diffusion.

The source gas for vapor phase diffusion in the lightly doped region 230 of the n-type impurity is an n-type impurity gas which becomes an n-type impurity gas which is naturally generated outward when the heat treatment is performed in a state in which the n-type impurity paste 210 is applied .

Or an n-type impurity gas which is artificially injected into the process chamber during the manufacturing process of the solar cell as another embodiment.

Since these gaseous n-type impurities can be dispersed in the air to the atmosphere rather than directly applied and diffused in a solid phase form on the semiconductor substrate, the semiconductor substrate is doped at a relatively low concentration so that a low concentration doping region .

The n-type impurity may be a dopant selected from the group consisting of a Group 5 element, and phosphorus (P) is mainly used although not particularly limited.

The n-type impurity gas injected from the outside can be mainly POCl ₃ or the like.

Due to the high concentration diffusion of the n-type impurity due to the direct contact of the n-type impurity paste, the density of the n-type impurity is higher than that of the other lightly doped region 230 in the heavily doped region 220 of the n-type impurity, The thickness of the doped region becomes thicker than that of the other doped regions.

Therefore, as the n-type impurity paste is patterned and applied on the p-type semiconductor substrate 201 in any form and shape, low concentration doped regions of the n-type impurity are formed to cross each other except for these coated portions.

One embodiment in which the heavily doped region 220 and the lightly doped region 230 of the n-type impurity are formed may be as shown in FIG. 7 to be described below.

FIGS. 3A to 3C and FIGS. 4A to 4C are cross-sectional views illustrating a process for forming a selective emitter of a solar cell according to an embodiment of the present invention. These processes are part of the process of manufacturing the solar cell and only the process of forming the selective emitter is read out.

3A to 3C, an n-type impurity paste 310 is applied on a p-type semiconductor substrate 301 according to a pattern (FIG. 3A)

These coating methods are not particularly limited, but can be carried out by a known screen printing method, printing method and the like.

At this time, in the previous process, the surface of the p-type semiconductor substrate 301 may be formed into a concavo-convex shape through a texturing process.

The texturing method may be a mechanical or chemical etching method, and is not particularly limited, but a chemical etching method using a material such as potassium hydroxide (KOH) can be used.

Next, a baking process is performed to heat-treat the semiconductor substrate for a solar cell to which the paste is applied. At this time, phosphorous silicate glass (PSG) may be formed on the n-type impurity semiconductor layer 302 as shown in FIG. 3B. The heat treatment may be performed at a temperature of 820 to 950 캜 for 30 seconds.

PSG by-products and the like that are unnecessarily generated in the heat treatment process are removed using hydrogen fluoride (HF) (FIG. 3C)

A byproduct layer such as PSG is formed to deteriorate the insulation characteristic of the solar cell, so that the process of removing the by-product layer which deteriorates the insulation characteristic is performed.

3C is a cross-sectional view of the solar cell after removing the PSG. A part directly coated with the n-type impurity paste 310 through the baking process of the heat treatment is formed as the highly doped region 320 in the n-type impurity semiconductor layer 302 The remaining unapplied portion is formed into the lightly doped region 330 in the n-type impurity semiconductor layer 302.

Thus, the heavily doped region and the heavily doped region of the n-type impurity function as selective emitters because the doping concentration of the impurity is different and the density is different.

Since the front electrode is formed on the heavily doped region 320 of the n-type impurity and the portion where no electrode is formed is formed as the lightly doped region 330 through the remaining process of the succeeding solar cell, The contact resistance can be designed to be low.

Meanwhile, as another embodiment of the present invention, FIGS. 4A to 4C form a selective emitter layer of a solar cell through the following process.

That is, in the processes of FIGS. 4A to 4C, the n-type impurity paste is applied simultaneously with the heat treatment in one firing furnace to form a selective emitter.

In this method, impurity doping is performed at the same time as firing in the firing furnace without using a separate impurity diffusing device or a process to form an impurity semiconductor layer which forms a pn junction, thereby simplifying the manufacturing process of the solar cell and shortening the manufacturing time .

As shown in FIG. 4A, the p-type semiconductor substrate 401 is first prepared, and the surface of the substrate is processed to have a concave-convex structure by a texturing process.

An n-type impurity semiconductor layer 402 is formed in a predetermined region on the p-type semiconductor substrate to form a pn junction structure.

According to one embodiment of the present invention, the n-type impurity semiconductor layer 402 may be patterned and formed in a predetermined region. The n-type impurity semiconductor layer may be patterned by a known doping method of the semiconductor layer, and the n-type impurity paste 410 may be formed on the patterned n-type semiconductor layer to form a selective emitter layer have.

However, since the emitter layer is formed by dividing into two layers in this embodiment, the n-type impurity paste 410 is coated and heat-treated to form an n-type impurity semiconductor layer Type impurity doped region can be divided and formed at the same time.

 In other words, as another embodiment, the n-type impurity paste 410 is coated on the p-type semiconductor substrate in the baking furnace heated to a predetermined temperature or higher to form the n-type impurity semiconductor layer and the selective emitter layer different from each other.

4B shows that PSG (Phosphorous Silicate Glass) 403 is formed on the n-type impurity semiconductor layer 402 when the heat treatment is performed. The description of this part is already described above. Similarly, PSG by-products and the like that are unnecessarily generated in the heat treatment process can be removed by using hydrogen fluoride (HF) (FIG. 4C)

Referring to FIG. 4C, the pn junction solar cell in which the PSG (phosphorus silicate glass) 403 is removed has a portion directly coated with the n-type impurity paste 410 in the n-type impurity semiconductor layer 402, And the remaining portion that is not coated is formed as a lightly doped region 430 in the n-type impurity semiconductor layer 402.

Therefore, an optional emitter composed of a heavily doped region and a lightly doped region of an n-type impurity can be formed by a simple process.

Thereafter, a solar cell including a selective emitter is manufactured through a conventional manufacturing process of a general solar cell. In some cases, the antireflection film may be laminated on the front side of the selective emitter layer. The antireflection film may be formed by a known deposition method such as a chemical vapor deposition method or a physical vapor deposition method.

A BSF (Back Surface Field) layer is formed on the rear surface of the semiconductor substrate by using aluminum (Al) or the like.

Electrodes are formed on the front and back sides of the solar cell, respectively, so that electrons and hole carriers separated from the pn junction are pulled to form a potential difference, thereby allowing electricity to flow.

The structure of the solar cell including the selective emitter formed according to the final present invention is shown in Fig.

Referring to FIG. 5, a selective emitter layer 502 is formed on a p-type semiconductor substrate 501 by the same method as the above embodiment, and an antireflection film 503 is stacked thereon.

The selective emitter layer is in contact with the front electrode 504, and the portion where the front electrode contacts is formed as a heavily doped region of the n-type impurity at a higher density than the remaining region.

And the remaining region where the front electrode is not in contact corresponds to the low concentration doping region of the n-type impurity.

A BSF layer 505 is formed on the rear surface of the p-type semiconductor substrate 501, and a rear electrode 506 is formed on a predetermined region on the BSF layer 505.

The material, material, forming method, and the like of the above-described antireflection film 503, the front electrode 504, the BSF layer 505, and the rear electrode 506 can be known by those skilled in the art The detailed description will be omitted.

6 is an enlarged cross-sectional view of a selective emitter portion of a solar cell according to an embodiment of the present invention.

The cross section of the n-type semiconductor layer 602 formed according to the method of forming the selective emitter according to the embodiment of the present invention is partially enlarged. According to one embodiment, in the cross section of the lightly doped region of the n-type impurity, May be thinner or equal to the thickness or depth of the interface with the high concentration doped region.

In other words, referring to FIG. 6, Wl means the thickness of the left interface of the interface between the lightly doped region and the heavily doped region of the n-type impurity semiconductor layer. And Wr means the thickness of the right interface of the interface between the lightly doped region and the heavily doped region in the n-type impurity semiconductor layer. Wc means the thickness of the center of the n-type impurity semiconductor layer at the center of the lightly doped region, that is, the center distance apart from the both interfaces by the same distance.

In one embodiment of the present invention, the central portion of the lightly doped region does not exactly mean the center of the lightly doped region but assumes a generic central portion that refers to a central portion that is the same or a similar distance from the interface with the lightly doped region.

As can be seen from FIG. 6, in the selective emitter layer of the present invention, the thickness of the center portion of the finally formed selective emitter layer is thinner than that of relatively different portions. Preferably from 0.1 mu m to 0.2 mu m.

The thickness of the interface between the heavily doped region and the heavily doped region in the other selective emitter layer may be thicker and may not exceed at least 1 탆. Preferably 0.8 占 퐉 to 0.9 占 퐉.

The difference in the thickness of the n-type impurity semiconductor layer in the low concentration doping region can be obtained by adjusting the concentration of the n-type impurity gas diffused supplied from the outside to the gaseous phase so as to diffuse differentially.

This difference in thickness is due to the fact that the heavily doped region of the n-type impurity semiconductor layer is directly implanted with impurities in the solid phase through the application of the n-type impurity paste, so that the boundary surface with the lightly doped region becomes a boundary where the impurity diffuses from high density to low density Such a difference in thickness may be automatically formed.

7 is a top plan view of a solar cell including a selective emitter formed according to an embodiment of the present invention.

This shows an embodiment of a pattern in which a heavily doped region 720 and a lightly doped region 730 of an n-type impurity are formed in the selective emitter layer. The high concentration n-type dopant existing on the surface of the p-type semiconductor substrate can be prevented from being excessively present by not doping the region where the electrode is not located at a high concentration.

Therefore, the contact resistance between the electrode and the n-type impurity semiconductor layer is minimized and the formation of a precipitate in the doped region is minimized, so that the lifetime of the charge is not reduced and ultimately the operating efficiency of the solar cell is improved.

In this embodiment, a paste containing P (phosphorus) is used as the high concentration impurity, but As (arsenic) and Sb (antimony) may be used in addition to P (phosphorus).

According to the embodiments of the present invention, not only the selective emitter is formed on the front surface of the solar cell by simply applying and firing the semiconductor impurity paste but also the diffusion process using the POCl ₃ gas is not performed, The process of forming the selective emitter of the first electrode is simplified.

Although the present invention has been described in connection with the specific embodiments of the present invention, it is to be understood that the present invention is not limited thereto. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. In addition, the materials of each component described herein can be readily selected and substituted for various materials known to those skilled in the art. Those skilled in the art will also appreciate that some of the components described herein can be omitted without degrading performance or adding components to improve performance. In addition, those skilled in the art may change the order of the method steps described herein depending on the process environment or equipment. Therefore, the scope of the present invention should be determined by the appended claims and equivalents thereof, not by the embodiments described.

1 is a sectional view showing the structure of a solar cell including a selective emitter according to the prior art.

2 is a cross-sectional view illustrating a method of forming a selective emitter of a solar cell according to an embodiment of the present invention.

FIGS. 3A through 3C are cross-sectional views illustrating a process for forming a selective emitter of a solar cell according to an embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a method of forming a selective emitter of a solar cell according to another embodiment of the present invention.

FIG. 5 is a cross-sectional view of a solar cell manufactured by a manufacturing process of a solar cell including a method of forming a selective emitter of the solar cell according to an embodiment of the present invention. FIG.

6 is an enlarged cross-sectional view of a selective emitter portion of a solar cell according to an embodiment of the present invention.

FIG. 7 is a top view of a solar cell including an optional emitter formed according to an embodiment of the present invention. FIG.

DESCRIPTION OF THE REFERENCE NUMERALS OF THE DRAWINGS FIG.

101, 201, 301, 401, 501: p-type semiconductor substrate

102, 202, 302, 402, 502, and 602: an n-type semiconductor layer

103, 503: antireflection film 104, 504: front electrode

105, 505: BSF (Back Surface Field) layer 106, 506:

210, 310, 410: n-type impurity paste

220, 320, 420, 720: heavily doped region of n-type impurity

230, 330, 430, 730: a lightly doped region of the n-type impurity

303, 403: Phosphorous Silicate Glass (PSG)

Claims (18)

A second impurity semiconductor layer formed on the entire surface of the first impurity semiconductor substrate and consisting of a heavily doped region of the second impurity and a lightly doped region of the second impurity; A front electrode formed on the heavily doped region of the second impurity of the second impurity semiconductor layer; And And a rear electrode formed on the rear surface of the first impurity semiconductor substrate, The depth of the heavily doped region of the second impurity is deeper than the depth of the lightly doped region of the second impurity, Wherein the depth of the lightly doped region of the second impurity is deeper toward the interface between the heavily doped region of the second impurity and the lightly doped region of the second impurity at the center of the lightly doped region. The method according to claim 1, And the junction surface of the first impurity semiconductor substrate and the second impurity semiconductor layer has a concavo-convex structure. The method according to claim 1, Wherein the heavily doped region of the second impurity and the lightly doped region of the second impurity are formed so as to cross each other over the entire surface of the first impurity semiconductor substrate. delete The method according to claim 1, Wherein a depth of a central portion of the lightly doped region of the second impurity is 0.1 占 퐉 to 0.2 占 퐉. The method according to claim 1, Wherein the interface depth of the lightly doped region of the second impurity is larger than the depth of the central portion and smaller than 0.8 占 퐉. The method according to claim 1, Wherein the first impurity is a p-type semiconductor impurity, and the second impurity is an n-type semiconductor impurity. 8. The method of claim 7, Wherein the n-type semiconductor impurity is selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb). 1. A method of forming a selective emitter of a solar cell comprising a heavily doped region of a second impurity and a lightly doped region of a second impurity on the entire surface of a first impurity semiconductor substrate, Wherein the heavily doped region of the second impurity is doped, Applying a second impurity paste on the first impurity semiconductor substrate so as to have a pattern corresponding to a heavily doped region of the second impurity; And a step of heat-treating the second impurity paste, The lightly doped region of the second impurity is formed in the remaining region where the heavily doped region of the second impurity is not formed on the first impurity semiconductor substrate, The lightly doped region of the second impurity is formed simultaneously with the heavily doped region of the second impurity in the step of performing the heat treatment by the diffusion of the second impurity gas in the step of heat-treating the second impurity paste A method for forming a selective emitter of a solar cell. delete delete delete 10. The method of claim 9, Wherein the second impurity gas is a second impurity gas generated from the applied second impurity paste or an injected POCl ₃ gas. 10. The method of claim 9, Wherein the second impurity paste is applied by a screen printing method or a printing method. 10. The method of claim 9, Wherein the heat treatment is performed at a temperature of 820 캜 to 950 캜 for 30 seconds to 10 minutes. 10. The method of claim 9, Wherein the first impurity is a p-type semiconductor impurity, and the second impurity is an n-type semiconductor impurity. 17. The method of claim 16, Wherein the n-type semiconductor impurity is selected from the group consisting of phosphorous (P), arsenic (As), and antimony (Sb). A method of manufacturing a solar cell comprising the selective emitter forming method of the solar cell according to any one of claims 9, 13 and 17.

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