KR101540927B1 - Semiconductor package and method for manufacturing the same - Google Patents

Semiconductor package and method for manufacturing the same Download PDF

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Publication number
KR101540927B1
KR101540927B1 KR1020130108792A KR20130108792A KR101540927B1 KR 101540927 B1 KR101540927 B1 KR 101540927B1 KR 1020130108792 A KR1020130108792 A KR 1020130108792A KR 20130108792 A KR20130108792 A KR 20130108792A KR 101540927 B1 KR101540927 B1 KR 101540927B1
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South Korea
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chip
lower chip
molding
input
molding compound
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KR1020130108792A
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Korean (ko)
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KR20150029855A (en
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김영래
성필제
박두현
백종식
송용
안서연
윤석우
김희대
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앰코 테크놀로지 코리아 주식회사
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Abstract

본 발명은 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 관통 실리콘 비아를 이용하여 복수의 칩을 적층하는 구조와 재배선 공정을 이용한 팬 아웃 구조를 동시에 실현할 수 있도록 한 반도체 패키지 및 이의 제조 방법에 관한 것이다.
즉, 본 발명은 관통 실리콘 비아를 이용하여 상부칩 및 하부칩을 상호 적층하되, 상부칩과 하부칩을 봉지시키는 몰딩 공정 후에 상부칩과 하부칩의 전기적 신호가 입출력되는 입출력 패드를 직접 하부칩 및 그 주변의 몰딩 컴파운드 수지 표면에 재배선 공정을 이용하여 형성해줌으로써, 기판을 배제하여 제조 비용을 절감하는 동시에 전체적인 패키지 두께를 줄일 수 있도록 한 반도체 패키지 및 이의 제조 방법을 제공하고자 한 것이다.The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package capable of simultaneously realizing a structure in which a plurality of chips are stacked using a through silicon via and a fanout structure using a rewiring process, ≪ / RTI >
That is, according to the present invention, the upper chip and the lower chip are stacked by using a through silicon via, and after the molding process for sealing the upper chip and the lower chip, the input / The present invention is to provide a semiconductor package and a method for manufacturing the semiconductor package which can reduce the manufacturing cost and the overall package thickness by eliminating the substrate by forming the molding compound compound around the resin by using a rewiring process.

Description

반도체 패키지 및 이의 제조 방법{Semiconductor package and method for manufacturing the same}[0001] Semiconductor package and method for manufacturing same [0002]

본 발명은 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 관통 실리콘 비아를 이용하여 복수의 칩을 적층하는 구조와 재배선 공정을 이용한 팬 아웃 구조를 동시에 실현할 수 있도록 한 반도체 패키지 및 이의 제조 방법에 관한 것이다.
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package capable of simultaneously realizing a structure in which a plurality of chips are stacked using a through silicon via and a fanout structure using a rewiring process, ≪ / RTI >

각종 전자기기 제품의 경량화, 소형화, 고속화, 다기능화, 고성능화 등 복합화 추세에 따라, 전자기기내 탑재되는 반도체 소자들에 대한 높은 신뢰성을 요구하고 있으며, 그에 따라 웨이퍼 레벨의 칩 스케일 패키지, 인터포저에 여러개의 칩을 한꺼번에 부착하여 기판에 탑재시킨 칩 적층형 패키지 등 다양한 구조의 패키지가 개발되고 있다.In order to meet the demands for high reliability of semiconductor devices mounted in electronic devices in accordance with the tendency of composite electronic devices such as weight reduction, miniaturization, high speed, multifunction, and high performance, wafer level chip scale packages and interposers Various types of packages such as a chip stacked package in which a plurality of chips are mounted together and mounted on a substrate are being developed.

특히, 기판에 형성된 전도성패드 간의 간격 및 반도체 칩의 신호 입출력을 위한 본딩패드 간의 간격이 매우 조밀하게 형성됨에 따라, 기판과 반도체 칩을 도전성 와이어를 이용하여 전기적 신호 교환 가능하게 연결하던 일반적인 와이어 본딩 방식을 탈피하여, 기판과 반도체 칩을 범프와 같은 전도성 매개수단을 이용하여 연결시킨 칩 적층형 반도체 패키지가 제조되고 있다.Particularly, since the interval between the conductive pads formed on the substrate and the interval between the bonding pads for inputting and outputting signals of the semiconductor chip are formed very densely, a general wire bonding method in which the substrate and the semiconductor chip are electrically- A chip stacked semiconductor package in which a substrate and a semiconductor chip are connected to each other by using a conductive medium such as a bump is manufactured.

여기서, 첨부한 도 2a 내지 2h를 참조로 종래의 칩 적층형 패키지에 대한 구성을 살펴보면 다음과 같다.Hereinafter, the structure of a conventional chip stack package will be described with reference to FIGS. 2A to 2H.

먼저, 다수의 칩이 소잉라인을 경계로 가로 및 세로 방향을 따라 등간격으로 배열된 웨이퍼를 구비하고, 웨이퍼의 각 칩 즉, 하부칩(10)에 관통 실리콘 비아(14)를 형성한다.(도 2a 참조)First, a plurality of chips are arranged at equally spaced intervals along the lateral and longitudinal directions with respect to the sawing line, and the through silicon vias 14 are formed in each chip of the wafer, that is, the lower chip 10. 2A)

보다 상세하게는, 상기 웨이퍼의 각 칩은 상부칩과 기판 간의 전기적 신호 전달 역할을 하는 동시에 상부칩과 기판 간의 실질적인 접촉을 회피하여 상부칩과 기판 간의 서로 다른 열팽창계수에 따른 워피지 현상 발생시 상부칩이 기판으로부터 이탈되는 것을 완충시키는 역할을 하는 인터포져 역할의 하부칩(10)으로서, 상부칩과 기판 간의 도전 경로가 되는 다수의 관통 실리콘 비아(14)가 형성된 구조로 구비된다.More particularly, each chip of the wafer serves as an electrical signal transfer between the upper chip and the substrate, while avoiding substantial contact between the upper chip and the substrate, and when a warpage phenomenon occurs according to different thermal expansion coefficients between the upper chip and the substrate, And a plurality of through silicon vias 14 serving as a conductive path between the upper chip and the substrate are formed as a lower chip 10 serving as an interposer that serves to buffer the separation of the upper chip from the substrate.

이때, 상기 관통 실리콘 비아(14)는 통상의 레이저 가공 방법 등을 이용하여 일정 깊이의 비아홀을 형성한 후, 비아홀내에 도전성 충진재를 도금 또는 충진시킨 구조를 갖는다.At this time, the through silicon vias 14 have a structure in which a via hole having a predetermined depth is formed using a conventional laser processing method or the like, and then a conductive filler is plated or filled in the via hole.

다음으로, 상기 웨이퍼의 각 칩 즉, 하부칩(10)에 형성된 각 관통 실리콘 비아(14)에 범핑 공정에 의하여 구리필러 또는 솔더볼과 같은 제1전도성 범프(12)가 융착된다.(도 2b 참조)Next, a first conductive bump 12 such as a copper filler or a solder ball is fused to each through silicon via 14 formed in each chip of the wafer, that is, the lower chip 10 (see FIG. 2B) )

이어서, 일면에 접착수단(18)이 도포된 캐리어(16)를 상기 하부칩(10)의 범핑면에 임시로 부착시켜서, 상기 하부칩(10)의 제1전도성 범프(12)들이 접착수단(18)에 묻히며 보호되는 상태가 되는 동시에 하부칩(10)이 캐리어(16)에 의하여 핸들링 가능하게 받쳐지는 상태가 되도록 한다.(도 2c 참조)The carrier 16 on one side of which the bonding means 18 has been applied is then temporarily attached to the bumping face of the lower chip 10 so that the first conductive bumps 12 of the lower chip 10 are bonded to the bonding means 18 so that the lower chip 10 is in a state of being supported by the carrier 16 so as to be able to be handled (see FIG.

연이어, 상기 캐리어(16)에 부착되어 받쳐진 하부칩(10)의 백면(제1전도성 범프가 부착된 면의 반대면)에 대하여 백그라인딩을 실시하되, 관통 실리콘 비아(14)가 노출될 때까지 백그라인딩을 실시하고, 노출된 관통 실리콘 비아(14)의 선단부에 통상의 도금 공정에 의하여 니켈/알루미늄 재질의 패드(15)가 형성되도록 한다.(도 2d 참조)Subsequently, back grinding is applied to the back side (opposite side of the side to which the first conductive bump is attached) of the lower chip 10 attached to the carrier 16, when the through silicon via 14 is exposed And a nickel / aluminum pad 15 is formed on the tip of the exposed through silicon via 14 by a conventional plating process (see Fig. 2 (D)).

이때, 상기 관통 실리콘 비아(14)의 선단부에 형성된 니켈/알루미늄 패드(15)는 상부칩(20)과 도전 가능하게 연결하는 제2전도성 범프(22)가 용이하게 융착되는 자리가 된다.At this time, the nickel / aluminum pad 15 formed at the tip portion of the through silicon via 14 becomes a place where the second conductive bump 22, which conductively connects to the upper chip 20, is easily fused.

이어서, 상기 캐리어(16)로부터 웨이퍼 상태인 하부칩(10)만 떼어내는 디본딩(debonding)을 실시한 후, 떼어낸 웨이퍼 상태의 하부칩(10)을 기판(30)에 탑재되도록 개개 단위로 분리하는 다이싱(dicing)을 실시한다.(도 2e 참조)Subsequently, debonding is performed in which only the lower chip 10 in a wafer state is detached from the carrier 16, and then the lower chips 10 in the wafer state, which have been detached, are separated and mounted on the substrate 30 (See Fig. 2 (e)).

다음으로, 개개 단위로 분리된 하부칩(10) 즉, 관통 실리콘 비아(14)에 제1전도성 범프(12)가 융착된 하부칩(10)을 기판(30: PCB, Printed Circuit Board)에 도전 가능하게 부착하는 단계가 진행된다.(도 2f 참조)Next, the lower chip 10, in which the first conductive bumps 12 are fused to the lower chip 10, that is, the through silicon vias 14, which are separated in individual units, is mounted on a PCB (Printed Circuit Board) (See Figure 2F). ≪ RTI ID = 0.0 >

좀 더 상세하게는, 상기 하부칩(10)의 제1전도성 범프(12)를 기판(30)의 상면에 형성된 전도성패턴에 도전 가능하게 부착시킴으로써, 기판(30)에 대한 하부칩(10)의 탑재가 이루어진다.More specifically, the first conductive bump 12 of the lower chip 10 is conductively attached to the conductive pattern formed on the upper surface of the substrate 30, so that the lower chip 10 of the lower chip 10 Mounting is done.

이때, 상기 기판(30)과 하부칩(10)의 저면 사이에는 다수의 제1전도성 범프(12)가 존재하는 상태인 바, 이 제1전도성 범프(12)들 간의 절연을 유지하는 동시에 제1전도성 범프(12)의 견고한 위치 고정을 위하여 기판(30)과 하부칩(10)의 저면 간의 틈새 공간에 절연성의 언더필 재료(24)가 충진되는 언더필 공정이 더 진행된다.At this time, a plurality of first conductive bumps 12 are present between the substrate 30 and the bottom surface of the lower chip 10 to maintain insulation between the first conductive bumps 12, The underfill process in which the insulating underfill material 24 is filled in the space between the substrate 30 and the bottom surface of the lower chip 10 for firmly fixing the conductive bump 12 is achieved.

이어서, 상기 하부칩(10) 위에 상부칩(20)을 전기적 신호 교환 가능하게 적층하는 단계가 진행된다.Then, the upper chip 20 is stacked on the lower chip 10 so as to be electrically exchangeable.

즉, 상기 상부칩(20)의 본딩패드(21)에 범핑 공정을 이용하여 제2전도성 범프(22)를 형성시킨 상태에서, 상부칩(20)의 제2전도성 범프(22)를 하부칩(10)의 관통 실리콘 비아(14)의 선단면에 융착시키고, 연이어 제2전도성 범프(22)들 간의 절연을 유지하는 동시에 견고한 위치 고정을 위하여 상부칩(10)의 저면과 하부칩(20)의 상면 간의 틈새 공간에 절연성의 언더필 재료(24)를 충진하는 언더필 공정을 진행함으로써, 하부칩(10)에 대한 상부칩(20)의 적층이 완료된다.(도 2g 참조)That is, the second conductive bump 22 of the upper chip 20 is electrically connected to the lower chip (not shown) in the state that the second conductive bump 22 is formed on the bonding pad 21 of the upper chip 20 using a bumping process 10 so as to secure insulation between the second conductive bumps 22 and to firmly fix the position of the second conductive bumps 22 to the bottom surface of the upper chip 10 and the bottom surface of the lower chip 20 The underfill process for filling the insulative underfill material 24 in the gap space between the upper surfaces is completed so that the stacking of the upper chip 20 to the lower chip 10 is completed (see FIG. 2G)

마지막으로, 상기 기판(30) 위에 적층된 하부칩(10) 및 상부칩(20)을 보호하기 위하여 몰딩 컴파운드 수지(26)로 봉지시키는 몰딩 공정을 진행함과 함께 기판(30)의 저면에 형성된 볼랜드(32)에 솔더볼과 같은 입출력단자(34)를 융착시키는 공정을 진행함으로써, 종래의 반도체 패키지가 완성된다.(도 2h 참조)Finally, a molding process is performed to encapsulate the lower chip 10 and the upper chip 20, which are stacked on the substrate 30, with a molding compound resin 26, and a molding process is performed on the bottom surface of the substrate 30 A process of fusing the input / output terminal 34 such as a solder ball to the borland 32 is performed to complete the conventional semiconductor package (refer to FIG. 2H)

그러나, 상기한 종래의 반도체 패키지는 기본적으로 상부칩 및 하부칩이 탑재되는 기판을 이용함에 따라, 전체적인 반도체 패키지 두께가 증가하여 경박단소화에 역행하는 단점이 있고, 특히 반도체 패키지의 구성 중 기판의 단가가 고가이어서 제조비용이 상승하는 주된 요인으로 작용하는 단점이 있다.
However, since the above-mentioned conventional semiconductor package basically uses the substrate on which the upper chip and the lower chip are mounted, there is a disadvantage that the thickness of the whole semiconductor package increases and it goes against the thinning and shortening of the overall package. Particularly, It has a disadvantage in that the unit cost is high and thus the manufacturing cost is increased.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 관통 실리콘 비아를 이용하여 상부칩 및 하부칩을 상호 적층하되, 상부칩과 하부칩을 봉지시키는 몰딩 공정 후에 상부칩과 하부칩의 전기적 신호가 입출력되는 입출력 패드를 직접 하부칩 및 그 주변의 몰딩 컴파운드 수지 표면에 재배선 공정을 이용하여 형성해줌으로써, 기판을 배제하여 제조 비용을 절감하는 동시에 전체적인 패키지 두께를 줄일 수 있도록 한 반도체 패키지 및 이의 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, A semiconductor package which can reduce the manufacturing cost and reduce the overall package thickness by eliminating the substrate and forming the input / output pad by directly rewiring the input / output pads on the surface of the lower chip and the surrounding molding compound resin, The purpose is to provide.

상기한 목적을 달성하기 위한 본 발명의 반도체 패키지는: 다수의 관통 실리콘 비아가 형성된 하부칩과; 상기 하부칩의 관통 실리콘 비아에 융착되는 전도성 범프가 본딩패드에 형성된 상부칩과; 상기 상부칩과 하부칩이 적층된 상태에서 하부칩의 저면을 제외하고, 상부칩 및 하부칩을 봉지시키며 몰딩된 몰딩 컴파운드 수지와; 하부칩의 저면을 통하여 노출된 다수의 관통 실리콘 비아 중, 선택된 관통 실리콘 비아의 하면에서 몰딩 컴파운드 수지의 저면 영역 중 원하는 위치로 연장 형성된 도전성 재배선과; 상기 도전성 재배선의 연장된 끝단부에 형성된 입출력패드에 융착되는 입출력단자; 를 포함하여 구성된 것을 특징으로 한다.According to an aspect of the present invention, there is provided a semiconductor package comprising: a lower chip having a plurality of through silicon vias formed therein; An upper chip having conductive bumps fused to the through vias of the lower chip formed on the bonding pads; A molding compound resin molding the upper chip and the lower chip in a state where the upper chip and the lower chip are stacked, excluding the bottom surface of the lower chip; A plurality of through silicon vias exposed through the bottom surface of the lower chip, conductive growing lines extending from a bottom surface of the selected through silicon vias to a desired position in a bottom surface region of the molding compound resin; An input / output terminal fused to an input / output pad formed at an extended end of the conductive rewiring line; And a control unit.

또한, 상기 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에는 재배선의 입출력패드를 제외한 나머지 재배선을 절연시키도록 패시베이션층이 도포된 것을 특징으로 한다.In addition, a passivation layer is coated on the bottom surface of the lower chip and the bottom surface of the molding compound resin to insulate the rewiring lines other than the input / output pads of the rewiring lines.

특히, 상기 입출력단자의 위치 고정을 위하여 입출력단자의 측부를 감싸주도록 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 위치 고정용 몰딩수지가 더 몰딩된 것을 특징으로 한다.In particular, a molding resin for position fixing is further molded over the bottom surface of the lower chip and the bottom surface of the molding compound resin so as to surround the side of the input / output terminal for fixing the position of the input / output terminal.

바람직하게는, 상기 몰딩 컴파운드 수지의 상면에 대한 그라인딩을 실시하여, 상부칩의 상면이 외부로 노출된 것을 특징으로 한다.Preferably, the upper surface of the upper chip is exposed to the outside by performing grinding on the upper surface of the molding compound resin.

상기한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조 방법은: 다수의 관통 실리콘 비아가 일정 깊이로 형성된 웨이퍼 상태의 하부칩 제공 단계와; 상기 하부칩을 캐리어에 부착하여 관통 실리콘 비아의 선단면이 노출되도록 하부칩의 백면을 그라인딩한 후, 웨이퍼 상태인 하부칩을 개개의 칩 단위로 분리하는 단계와; 상부칩의 본딩패드에 형성된 전도성 범프를 상기 각 하부칩의 관통 실리콘 비아에 융착시키는 하부칩에 대한 상부칩 적층 단계와; 서로 적층된 하부칩 및 상부칩을 캐리어로부터 분리하여 몰딩용 캐리어 위에 일정 간격으로 부착시키는 단계와; 상기 몰딩용 캐리어 위에 몰딩 컴파운드 수지를 몰딩하여, 서로 적층된 하부칩 및 상부칩이 봉지되도록 한 몰딩 단계와; 상기 몰딩용 캐리어를 분리한 후, 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 재배선을 형성하는 단계와; 상기 재배선의 끝단부에 형성된 입출력패드에 입출력단자를 융착시키는 단계; 를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package, including: providing a lower chip in a wafer state in which a plurality of through silicon vias are formed at a predetermined depth; Attaching the lower chip to a carrier to grind the bottom surface of the lower chip so that a front end surface of the through silicon via is exposed, and then separating the lower chip in a wafer state into individual chip units; An upper chip laminating step for lower chips for fusing conductive bumps formed on the bonding pads of the upper chip to the through silicon vias of the lower chips; Separating the lower chip and the upper chip from each other and attaching the lower chip and the upper chip to the molding carrier at regular intervals; A molding step of molding a molding compound on the carrier for molding to encapsulate the lower chip and the upper chip stacked with each other; Forming a rewiring line on the bottom surface of the lower chip and the bottom surface of the molding compound resin after the carrier for molding is separated; Fusing an input / output terminal to an input / output pad formed at an end of the rewiring line; And a control unit.

바람직하게는, 상기 웨이퍼 상태인 하부칩을 개개의 칩 단위로 분리하는 단계는 스텔스 다이싱 공정을 이용하여 진행되는 것을 특징으로 한다.Preferably, the step of separating the lower chip, which is in the wafer state, into individual chip units is performed using a stealth dicing process.

또한, 상기 서로 적층된 하부칩 및 상부칩을 캐리어로부터 분리한 후, 상부칩의 상면에 필름을 부착하는 단계와, 서로 분리된 상태인 하부칩 간의 간격이 보다 넓게 이격되도록 필름을 좌우로 잡아당겨 늘려주는 단계가 더 진행되는 것을 특징으로 한다.A step of separating the lower chip and the upper chip from each other and then attaching a film to the upper surface of the upper chip and a step of pulling the film from side to side so that the interval between the lower chips, And the step of increasing the number of steps is further progressed.

특히, 상기 재배선은 하부칩의 저면을 통하여 노출된 다수의 관통 실리콘 비아 중, 선택된 관통 실리콘 비아의 하면에서 몰딩 컴파운드 수지의 저면 영역 중 원하는 위치로 연장 형성되는 것을 특징으로 한다.In particular, the rewiring is extended from a bottom surface of the selected through silicon vias to a desired one of the bottom surface regions of the molding compound resin among the plurality of through silicon vias exposed through the bottom surface of the lower chip.

또한, 상기 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 재배선의 입출력패드를 제외한 나머지 재배선을 절연시키도록 패시베이션층을 도포하는 단계를 더 포함하는 것을 특징으로 한다.The method may further include coating a passivation layer on the bottom surface of the lower chip and the bottom surface of the molding compound resin to insulate the rewiring lines other than the input / output pads of the rewiring lines.

바람직하게는, 상기 입출력단자의 측부를 감싸주도록 패시베이션층이 도포된 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 위치 고정용 몰딩수지를 몰딩하는 단계를 더 포함하는 것을 특징으로 한다.Preferably, the method further comprises molding the molding resin for position fixing over the bottom surface of the lower chip coated with the passivation layer and the bottom surface of the molding compound resin so as to surround the side of the input / output terminal.

더욱 바람직하게는, 상기 상부칩의 상면이 외부로 노출되도록 몰딩 컴파운드 수지의 상면에 대한 그라인딩을 실시하는 단계를 더 포함하는 것을 특징으로 한다.
More preferably, the method further comprises grinding the upper surface of the molding compound so that the upper surface of the upper chip is exposed to the outside.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 별도의 기판 사용 없이, 하부칩 및 상부칩을 적층하는 단계와 하부칩 및 상부칩을 몰딩하는 단계 후, 재배선을 형성하는 도금 공정을 이용하여 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 전기적 입출력 경로가 되는 재배선을 형성하여, 칩 적층 구조이면서 팬 아웃 형태의 반도체 패키지를 완성함으로써, 종래의 기판을 사용한 구조에 비하여 전체적인 반도체 패키지 두께를 줄일 수 있고, 특히 기판을 배제함에 따른 제조 비용을 크게 절감할 수 있다.According to the present invention, the steps of laminating the lower chip and the upper chip, and the step of molding the lower chip and the upper chip, without using a separate substrate, The entire semiconductor package thickness can be reduced as compared with the structure using the conventional substrate by completing the semiconductor package having the chip stacked structure and the fan-out type by forming the rewiring line serving as the electrical input / The manufacturing cost can be greatly reduced.

또한, 종래의 패키지에 적용되던 기판과 하부칩을 제1전도성 범프를 매개로 연결하던 범핑 공정 등이 생략되어, 공수를 절감하여 생산성을 향상시킬 수 있고, 제조 비용 절감을 더욱 도모할 수 있다.
In addition, a bumping step of connecting the substrate and the lower chip to each other through the first conductive bump, which is applied to the conventional package, can be omitted, so that the productivity can be improved and the manufacturing cost can be further reduced.

도 1a 내지 도 1l은 본 발명에 따른 반도체 패키지 및 이의 제조 방법을 순서대로 도시한 도면,
도 2a 내지 도 2h는 종래의 반도체 패키지 및 이의 제조 방법을 순서대로 도시한 도면.FIGS. 1A to 1L illustrate a semiconductor package according to the present invention and a method of manufacturing the same in sequence;
2A through 2H show a conventional semiconductor package and a method of manufacturing the same in order.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 다수의 관통 실리콘 비아(14)가 일정 깊이로 형성된 웨이퍼 상태의 하부칩(10)을 구비한다.First, a plurality of through silicon vias 14 are provided on the lower chip 10 in a wafer state at a predetermined depth.

즉, 다수의 칩이 소잉라인을 경계로 가로 및 세로 방향을 따라 등간격으로 배열된 웨이퍼를 구비하고, 웨이퍼의 각 칩 즉, 하부칩(10)에 관통 실리콘 비아(14)를 형성한다.(도 1a 참조)That is, a plurality of chips are arranged at equally spaced intervals along the lateral and longitudinal directions with respect to the sawing line, and the through silicon vias 14 are formed in each chip of the wafer, that is, the lower chip 10. 1A)

상기 하부칩(10)은 상부칩과 기판 간의 전기적 신호 전달 역할을 하는 동시에 상부칩과 기판 간의 실질적인 접촉을 회피하여 상부칩과 기판 간의 서로 다른 열팽창계수에 따른 워피지 현상 발생시 상부칩이 기판으로부터 이탈되는 것을 완충시키는 역할을 하는 것으로서, 상부칩과 기판 간의 도전 경로가 되는 다수의 관통 실리콘 비아(14)가 형성된 구조로 구비된다.The lower chip 10 serves as an electrical signal transfer between the upper chip and the substrate and avoids substantial contact between the upper chip and the substrate to cause the upper chip to deviate from the substrate in the event of a warpage depending on different thermal expansion coefficients between the upper chip and the substrate And a plurality of through silicon vias 14 serving as a conductive path between the upper chip and the substrate are formed.

이때, 상기 관통 실리콘 비아(14)는 통상의 레이저 가공 방법 등을 이용하여 일정 깊이의 비아홀을 형성한 후, 비아홀내에 도전성 충진재를 도금 또는 충진시킨 구조를 갖는다.At this time, the through silicon vias 14 have a structure in which a via hole having a predetermined depth is formed using a conventional laser processing method or the like, and then a conductive filler is plated or filled in the via hole.

이어서, 일면에 접착수단(18)이 도포된 캐리어(16)를 상기 하부칩(10)의 범핑면에 임시로 부착시킨 다음, 하부칩(10)의 백면에 대하여 백그라인딩을 실시하되, 관통 실리콘 비아(14)가 노출될 때까지 백그라인딩을 실시한다.(도 1b 참조)Subsequently, the carrier 16, to which the adhesive means 18 is applied, is temporarily attached to the bumping surface of the lower chip 10, and then the back surface of the lower chip 10 is subjected to back grinding, Back grinding is performed until the via 14 is exposed (see FIG. 1B)

연이어, 상기 하부칩(10)의 백면을 그라인딩한 후, 웨이퍼 상태인 하부칩(10)을 개개의 칩 단위로 분리하는 단계가 진행된다.(도 1c 참조)Subsequently, a step of grinding the bottom surface of the lower chip 10 and then separating the lower chip 10, which is in a wafer state, into individual chip units proceeds (see FIG. 1C).

바람직하게는, 상기 웨이퍼 상태인 하부칩(10)을 개개의 칩 단위로 분리하는 단계는 스텔스 다이싱(Stealth Dicing) 공정을 이용하여 진행되고, 얇은 블레이드(Blade)나 레이저 빔(Laser Beam)을 이용한 쏘잉(Sawing) 공정을 이용할 수 있다.Preferably, the step of separating the lower chip 10 in the wafer state into individual chip units is performed using a stealth dicing process, and a thin blade or a laser beam A using sawing process can be used.

다음으로, 상기 상부칩(20)의 본딩패드(21)에 형성된 전도성 범프(28)를 상기 각 하부칩(10)의 관통 실리콘 비아(14)에 융착시켜 이루어지는 하부칩(10)에 대한 상부칩(20) 적층 단계가 진행된다.(도 1d 참조)Next, a conductive chip is formed by fusing the conductive bumps 28 formed on the bonding pads 21 of the upper chip 20 to the through silicon vias 14 of the respective lower chips 10, (20) lamination step proceeds (see Fig. 1D).

즉, 상기 상부칩(20)의 본딩패드(21)에 범핑 공정을 이용하여 전도성 범프(28)를 미리 형성시킨 상태에서, 상부칩(20)의 전도성 범프(28)를 하부칩(10)의 관통 실리콘 비아(14)의 선단면에 융착시킴으로써, 웨이퍼 상태인 각 하부칩(10)의 위에 상부칩(20)이 대응되며 적층된다.The conductive bump 28 of the upper chip 20 is electrically connected to the conductive bump 28 of the lower chip 10 in a state where the conductive bump 28 is previously formed on the bonding pad 21 of the upper chip 20 using a bumping process. The upper chip 20 is correspondingly stacked on each of the lower chips 10 in the wafer state by fusing them to the front end face of the through silicon vias 14. [

이어서, 서로 적층된 하부칩(10) 및 상부칩(20)을 캐리어(16)로부터 분리한 후, 상부칩(20)의 상면에 신장 가능한 필름(36)을 부착하는 단계와, 스텔스 다이싱에 의하여 서로 분리된 상태인 하부칩(10) 간의 간격이 보다 넓게 이격되도록 필름(36)을 좌우로 잡아당겨 늘려주는 단계가 진행됨으로써, 상부칩(20)들 간의 간격과 하부칩(10)들 간의 간격이 보다 넓어지게 된다.(도 1e 참조)Attaching a stretchable film 36 to the upper surface of the upper chip 20 after separating the lower chip 10 and the upper chip 20 stacked from each other from the carrier 16, As a result of the step of stretching the film 36 to the left and right so that the gap between the lower chips 10 separated from each other is wider than the distance between the upper chips 20, So that the interval becomes wider (see FIG.

이때, 상기 하부칩(10) 및 상부칩(20)들 간의 간격을 필름(36)을 이용하여 넓혀주는 이유는 서로 적층된 하부칩(10)과 상부칩(20)을 몰딩하는 공정후 낱개 단위로 패키지로 용이하게 소잉하기 위함에 있다.The gap between the lower chip 10 and the upper chips 20 is widened by using the film 36 after the process of molding the lower chip 10 and the upper chip 20 stacked one upon the other, So that it can be easily sacked into a package.

다음으로, 상기와 같이 캐리어(16)로부터 분리하여 필름 위에 부착된 적층 상태의 하부칩(10) 및 상부칩(20)을 하나씩 떼어내어, 몰딩용 캐리어(48) 위에 일정 간격으로 부착시킨다.(도 1f 참조)Next, the lower chip 10 and the upper chip 20 in the laminated state, which are separated from the carrier 16 and separated from the carrier 16, are removed one by one, and are attached at regular intervals on the molding carrier 48. 1F)

연이어, 상기 몰딩용 캐리어(48) 위에 몰딩 컴파운드 수지(26)를 일정 두께로 몰딩하여, 서로 적층된 하부칩(10) 및 상부칩(20)이 봉지되도록 한 몰딩 단계가 진행된다.(도 1g 참조)Subsequently, the molding compound resin 26 is molded on the molding carrier 48 to a predetermined thickness, and the molding process is performed so that the lower chip 10 and the upper chip 20 stacked with each other are sealed (see FIG. 1G Reference)

이러한 몰딩 단계 후, 몰딩용 캐리어(48)를 분리하면 하부칩(10)의 저면이 몰딩 컴파운드 수지(26)의 저면과 동일 평면을 이루면서 외부로 노출되는 상태가 된다.When the molding carrier 48 is separated after the molding step, the bottom surface of the lower chip 10 is flush with the bottom surface of the molding compound resin 26 and exposed to the outside.

이어서, 상기 몰딩용 캐리어(48)를 분리한 후, 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 재배선(40)을 형성하는 단계가 진행된다.Subsequently, after the carrier for molding 48 is separated, a step of forming a rewiring line 40 is performed on the bottom surface of the lower chip 10 and the bottom surface of the molding compound resin 26.

보다 상세하게는, 상기 재배선(40)은 통상의 도금 공정 등을 이용하여 형성될 수 있으며, 이때의 재배선(40)은 하부칩(10)의 저면을 통하여 노출된 다수의 관통 실리콘 비아(14) 중, 선택된 관통 실리콘 비아(14)의 하면에서 몰딩 컴파운드 수지(26)의 저면 영역의 원하는 위치까지 연장 형성된다.(도 1h 참조)The redistribution line 40 may be formed by a conventional plating process or the like and the redistribution line 40 may be formed by a plurality of through silicon vias exposed through the bottom surface of the lower chip 10. [ 14) to a desired position in the bottom surface region of the molding compound resin 26 from the lower surface of the selected through silicon via 14 (see FIG. 1 (h)).

이때, 상기 재배선(40)의 연장된 끝단부는 입출력단자(34)가 융착되는 입출력패드(42) 자리가 된다.At this time, the extending end of the rewiring line 40 becomes a seat of the input / output pad 42 to which the input / output terminal 34 is fused.

다음으로, 상기 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 재배선을 절연시키도록 패시베이션층(44)을 일정 두께로 도포하되, 재배선(40)의 입출력패드(42)를 제외하고 도포하여, 입출력단자(34)가 융착될 입출력패드(42)는 외부로 노출되는 상태가 되도록 한다.(도 1i 참조)Next, the passivation layer 44 is coated to a predetermined thickness so as to insulate rewiring lines from the bottom surface of the lower chip 10 and the bottom surface of the molding compound resin 26, and the input / output pads 42 And the input / output pads 42 to which the input / output terminals 34 are to be fused are exposed to the outside (see Fig. 1I).

연이어, 상기 재배선(40)의 끝단부에 형성된 입출력패드(42)에 솔더볼과 같은 입출력단자(34)를 융착시킨다.(도 1i 참조)Output terminal 34 such as a solder ball is fused to the input / output pad 42 formed at the end of the redistribution line 40 (see FIG.

이때, 본 발명의 반도체 패키지는 입출력단자가 융착되는 볼랜드를 포함하는 기판을 사용하지 않기 때문에, 입출력단자(34)가 입출력패드(42)에 융착되더라도 입출력단자(34)를 견고하게 잡아주지 못할 우려가 있다.In this case, the semiconductor package of the present invention does not use the board including the borland to which the input / output terminals are fused, so that even if the input / output terminal 34 is fused to the input / output pad 42, the input / output terminal 34 may not be firmly held .

따라서, 상기 패시베이션층(44)이 도포된 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 위치 고정용 몰딩수지(46)를 더 몰딩하는 단계를 진행함으로써, 위치 고정용 몰딩수지(46)가 입출력단자(34)의 측부를 감싸면서 견고하게 잡아줄 수 있도록 한다.(도 1j 참조)Therefore, by further performing the step of further molding the position fixing molding resin 46 over the bottom surface of the lower chip 10 to which the passivation layer 44 is applied and the bottom surface of the molding compound resin 26, So that the resin 46 can securely hold the side of the input / output terminal 34 (refer to FIG. 1J).

한편, 상기 몰딩 컴파운드 수지(26)의 상면에 대한 그라인딩을 실시하는 단계를 더 진행하여, 상부칩(20)의 상면이 외부로 노출되도록 함으로써, 상부칩(20)의 동작 중 발생되는 열을 외부로 방출시키는 열방출 효과를 극대화시킬 수 있다.(도 1k 참조)The upper surface of the upper chip 20 is exposed to the outside so that the heat generated during operation of the upper chip 20 can be radiated to the outside (See Fig. 1K).

마지막으로, 서로 적층된 하부칩(10)과 상부칩(20)을 포함하는 낱개의 반도체 패키지로 소잉하는 공정을 진행함으로써, 본 발명에 따른 반도체 패키지가 완성된다.(도 1l 참조)Finally, the semiconductor package according to the present invention is completed by sowing a single semiconductor package including the lower chip 10 and the upper chip 20 stacked with each other (see FIG. 11).

이상과 같은 본 발명에 따르면, 기존에 기판을 사용하는 것을 배제한 채, 하부칩 및 상부칩을 적층하는 단계와, 하부칩 및 상부칩을 몰딩하는 단계 후, 재배선을 형성하는 도금 공정을 이용하여 하부칩의 저면 및 몰딩 컴파운드 수지의 저면에 걸쳐 전기적 입출력 경로가 되는 재배선을 형성하고, 재배선의 입출력패드에 입출력단자를 융착시킴으로써, 칩 적층 구조이면서 웨이퍼 레벨의 팬 아웃 구조를 갖는 반도체 패키지를 제공할 수 있다.
According to the present invention, the steps of laminating the lower chip and the upper chip while excluding the use of the substrate, and the plating process of forming the re-wiring after the lower chip and the upper chip are molded A semiconductor package having a chip-stacked structure and a wafer-level fan-out structure is provided by forming rewiring lines to be electrical input / output paths through the bottom surface of the lower chip and the bottom surface of the molding compound resin and fusing the input / output terminals to the input / can do.

10 : 하부칩
12 : 제1전도성 범프
14 : 관통 실리콘 비아
15 : 패드
16 : 캐리어
18 : 접착수단
20 : 상부칩
21 : 본딩패드
22 : 제2전도성 범프
24 : 언더필 재료
26 : 몰딩 컴파운드 수지
28 : 전도성 범프
30 : 기판
32 : 볼랜드
34 : 입출력단자
36 : 필름
40 : 재배선
42 : 입출력패드
44 : 패시베이션층
46 : 위치 고정용 몰딩수지
48 : 몰딩용 캐리어10: Lower chip
12: first conductive bump
14: Through silicon Via
15: Pad
16: Carrier
18: Adhesion means
20: upper chip
21: bonding pad
22: second conductive bump
24: underfill material
26: Molding compound resin
28: Conductive bump
30: substrate
32: Borland
34: I / O terminal
36: Film
40: Cultivation line
42: Input / output pads
44: Passivation layer
46: Molding resin for fixing the position
48: Carrier for molding

Claims (11)

다수의 관통 실리콘 비아(14)가 형성된 하부칩(10)과;
상기 하부칩(10)의 관통 실리콘 비아(14)에 융착되는 전도성 범프(28)가 본딩패드(21)에 형성된 상부칩(20)과;
상기 하부칩(10)과 상부칩(20)이 상호 적층된 상태에서 하부칩(10) 및 상부칩(20)을 봉지시키며 몰딩된 몰딩 컴파운드 수지(26)와;
상기 하부칩(10)의 저면을 통하여 노출된 다수의 관통 실리콘 비아(14) 중, 선택된 관통 실리콘 비아(14)의 하면에서 몰딩 컴파운드 수지(26)의 저면 영역의 원하는 위치까지 연장 형성된 도전성 재배선(40)과;
상기 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 재배선(40)의 입출력패드(42)를 노출시키면서 나머지 재배선을 절연시키도록 도포된 패시베이션층(44)과;
상기 패시베이션층(44)이 도포된 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 입출력단자(34)의 위치 고정을 위하여 입출력단자(34)의 측부를 감싸주도록 몰딩된 위치 고정용 몰딩수지(46); 및
상기 도전성 재배선(40)의 연장된 끝단부에 형성된 입출력패드(42)에 융착되는 입출력단자(34);
를 포함하여 구성된 것을 특징으로 하는 반도체 패키지.
A lower chip (10) having a plurality of through silicon vias (14) formed therein;
An upper chip 20 formed on the bonding pad 21 with a conductive bump 28 fused to the through silicon via 14 of the lower chip 10;
A molding compound resin 26 which encapsulates the lower chip 10 and the upper chip 20 in a state where the lower chip 10 and the upper chip 20 are laminated to each other;
A plurality of through silicon vias 14 exposed through the bottom surface of the lower chip 10 and extending from the lower surface of the selected through silicon vias 14 to a desired position of the bottom surface area of the molding compound resin 26, (40);
A passivation layer 44 applied to the bottom surface of the lower chip 10 and the bottom surface of the molding compound resin 26 to expose input / output pads 42 of the rewiring lines 40 and insulate the remaining rewiring lines;
Output terminal 34 to cover the side surface of the input / output terminal 34 for fixing the position of the input / output terminal 34 over the bottom surface of the lower chip 10 to which the passivation layer 44 is applied and the bottom surface of the molding compound resin 26 A fixing molding resin 46; And
An input / output terminal (34) fused to an input / output pad (42) formed at an extended end of the conductive rewiring line (40);
The semiconductor package comprising:
삭제delete 삭제delete 청구항 1에 있어서,
상기 몰딩 컴파운드 수지(26)의 상면에 대한 그라인딩을 실시하여, 상부칩(20)의 상면이 외부로 노출된 것을 특징으로 하는 반도체 패키지.
The method according to claim 1,
And the upper surface of the upper chip (20) is exposed to the outside by grinding the upper surface of the molding compound resin (26).
다수의 관통 실리콘 비아(14)가 일정 깊이로 형성된 웨이퍼 상태의 하부칩(10) 제공 단계와;
상기 하부칩(10)을 캐리어(16)에 부착하여 관통 실리콘 비아(14)의 선단면이 노출되도록 하부칩(10)의 백면을 그라인딩한 후, 웨이퍼 상태인 하부칩(10)을 개개의 칩 단위로 분리하는 단계와;
상부칩(20)의 본딩패드(21)에 형성된 전도성 범프(28)를 상기 각 하부칩(10)의 관통 실리콘 비아(14)에 융착시켜 이루어지는 하부칩(10)에 대한 상부칩(20) 적층 단계와;
서로 적층된 하부칩(10) 및 상부칩(20)을 캐리어(16)로부터 분리하여 몰딩용 캐리어(48) 위에 일정 간격으로 부착시키는 단계와;
상기 몰딩용 캐리어(48) 위에 몰딩 컴파운드 수지(26)를 일정 두께로 몰딩하여, 서로 적층된 하부칩(10) 및 상부칩(20)이 봉지되도록 한 몰딩 단계와;
상기 몰딩용 캐리어(48)를 분리한 후, 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 재배선(40)을 형성하는 단계와;
상기 재배선(40)의 끝단부에 형성된 입출력패드(42)에 입출력단자(34)를 융착시키는 단계;
를 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
Providing a lower chip (10) in a wafer state in which a plurality of through silicon vias (14) are formed at a certain depth;
The lower chip 10 is attached to the carrier 16 to grind the white surface of the lower chip 10 so that the front end face of the silicon via 14 is exposed and then the lower chip 10, Separating into units;
The upper chip 20 is stacked on the lower chip 10 formed by fusing the conductive bumps 28 formed on the bonding pads 21 of the upper chip 20 to the through silicon vias 14 of the lower chips 10. [ ;
Attaching the lower chip 10 and the upper chip 20, which are laminated to each other, from the carrier 16 and attaching the lower chip 10 and the upper chip 20 at regular intervals on the molding carrier 48;
A molding step of molding the molding compound resin 26 on the molding carrier 48 to seal the lower chip 10 and the upper chip 20 laminated to each other;
Forming a rewiring line (40) over the bottom surface of the lower chip (10) and the bottom surface of the molding compound resin (26) after separating the molding carrier (48);
Connecting the input / output terminal (34) to the input / output pad (42) formed at the end of the rewiring line (40);
≪ / RTI >
청구항 5에 있어서,
상기 웨이퍼 상태인 하부칩(10)을 개개의 칩 단위로 분리하는 단계는 스텔스 다이싱 공정을 이용하여 진행되는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
Wherein the step of separating the lower chip (10) in the wafer state into individual chip units is performed using a stealth dicing process.
청구항 5에 있어서,
상기 서로 적층된 하부칩(10) 및 상부칩(20)을 캐리어(16)로부터 분리한 후, 상부칩(20)의 상면에 필름(36)을 부착하는 단계와, 서로 분리된 상태인 하부칩(10) 간의 간격이 보다 넓게 이격되도록 필름(36)을 좌우로 잡아당겨 늘려주는 단계가 더 진행되는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
Attaching a film (36) to an upper surface of the upper chip (20) after separating the lower chip (10) and the upper chip (20) stacked from each other from the carrier (16) Further comprising the step of pulling and stretching the film (36) to the left and right so that the gap between the film (10) is more widely spaced.
청구항 5에 있어서,
상기 재배선(40)은 하부칩(10)의 저면을 통하여 노출된 다수의 관통 실리콘 비아(14) 중, 선택된 관통 실리콘 비아(14)의 하면에서 몰딩 컴파운드 수지(26)의 저면 영역의 원하는 위치까지 연장 형성되는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
The rewiring line 40 is formed at a desired position of the bottom surface area of the molding compound resin 26 in the bottom surface of the selected through silicon via 14 among the plurality of through silicon via 14 exposed through the bottom surface of the lower chip 10 Of the semiconductor package.
청구항 5에 있어서,
상기 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 재배선(40)의 입출력패드(42)를 제외한 나머지 재배선을 절연시키도록 패시베이션층(44)을 도포하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
The step of applying the passivation layer 44 so as to insulate the rewiring lines other than the input / output pads 42 of the rewiring lines 40 from the bottom surface of the lower chip 10 and the bottom surface of the molding compound resin 26 Wherein the semiconductor package is a semiconductor package.
청구항 5에 있어서,
상기 입출력단자(34)의 측부를 감싸주도록 패시베이션층(44)이 도포된 하부칩(10)의 저면 및 몰딩 컴파운드 수지(26)의 저면에 걸쳐 위치 고정용 몰딩수지(46)를 몰딩하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.
The method of claim 5,
The step of molding the position fixing molding resin 46 over the bottom surface of the lower chip 10 to which the passivation layer 44 is applied and the bottom surface of the molding compound resin 26 so as to cover the side of the input / output terminal 34 ≪ / RTI >
청구항 5에 있어서,
상기 상부칩(20)의 상면이 외부로 노출되도록 몰딩 컴파운드 수지(26)의 상면에 대한 그라인딩을 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체 패키지 제조 방법.The method of claim 5,
Further comprising the step of grinding the top surface of the molding compound resin (26) so that the top surface of the top chip (20) is exposed to the outside.
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