KR20150090442A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR20150090442A
KR20150090442A KR1020140011094A KR20140011094A KR20150090442A KR 20150090442 A KR20150090442 A KR 20150090442A KR 1020140011094 A KR1020140011094 A KR 1020140011094A KR 20140011094 A KR20140011094 A KR 20140011094A KR 20150090442 A KR20150090442 A KR 20150090442A
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South Korea
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interposer
semiconductor package
ball
molding
support
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KR1020140011094A
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Korean (ko)
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KR101573311B1 (en
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박동주
김재윤
김진성
안예슬
한규완
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020140011094A priority Critical patent/KR101573311B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device which improves a structure of an interposer that configures a fan-in POP typed package to prevent the warpage phenomenon. To this end, the semiconductor device comprises: a lower semiconductor package including a semiconductor chip and a stacking ball attached onto a substrate to be conductible, a molding compound resin for encapsulating the conductive chip and the stacking ball, and a through mold via formed on the molding compound resin to expose the stacking ball; and an interposer connected to the stacking ball of the lower semiconductor package to be conductible, and stacked thereon, and connecting the lower semiconductor package and the upper semiconductor package to be conductible, wherein a molding support is integrally molded on a lower surface of the interposer, a connecting ball of the interposer is fused on the stacking ball of the lower semiconductor package, and then the molding support and the molding compound resin of the lower semiconductor package, which have the same material and thermal expansion coefficient, are adjacently arranged to each other.

Description

반도체 장치 및 이의 제조 방법{SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device,

본 발명은 반도체 장치 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 팬-인 피오피 타입의 패키지를 구성하는 인터포저의 구조를 개선하여, 워피지 현상을 방지할 수 있도록 한 반도체 장치 및 이의 제조 방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device which improves a structure of an interposer constituting a package of a fan-in type, ≪ / RTI >

각종 전자기기 제품의 경량화, 소형화, 고속화, 다기능화, 고성능화 등 복합화 추세에 따라, 전자기기내 탑재되는 반도체 소자들에 대한 높은 신뢰성을 요구하고 있으며, 그에 따라 웨이퍼 레벨의 칩 스케일 패키지, 인터포저에 여러개의 칩을 한꺼번에 부착하여 기판에 탑재시킨 칩 적층형 패키지, 인너포저를 사이에 두고 상하로 적층되는 패키지 온 패키지(POP, Package On Package) 등 다양한 구조의 반도체 패키지가 개발되고 있다.In order to meet the demands for high reliability of semiconductor devices mounted in electronic devices in accordance with the tendency of composite electronic devices such as weight reduction, miniaturization, high speed, multifunction, and high performance, wafer level chip scale packages and interposers A semiconductor package having various structures such as a chip stacked package in which a plurality of chips are mounted together on a substrate and a package on package (POP) stacked on top of each other with an inner gap interposed therebetween are being developed.

여기서, 종래의 패키지 온 패키지의 구성 및 그 제조 과정을 살펴보면 다음과 같다.Hereinafter, the structure of a conventional package-on-package and its manufacturing process will be described.

첨부한 도 3은 종래의 패키지 온 패키지를 나타낸 단면도이다.3 is a cross-sectional view of a conventional package-on-package.

도 3에서, 도면부호 100은 하부 반도체 패키지를 나타내고, 도면부호 300은 상부 반도체 패키지를 나타내며, 도면부호 200은 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 인터포저를 나타낸다.In FIG. 3, reference numeral 100 denotes a lower semiconductor package, reference numeral 300 denotes an upper semiconductor package, reference numeral 200 denotes an interposer for electrically connecting the lower semiconductor package 100 and the upper semiconductor package 300 .

먼저, 상기 하부 반도체 패키지(100)를 제조하고자, 기판(102)의 상면 중앙영역에 반도체 칩(104)이 도전성 범프(106)를 매개로 전기적 신호 교환 가능하게 적층 부착되고, 또한 기판(102)의 상면 테두리 영역에는 적층용 볼(108)이 도전 가능하게 부착된다.A semiconductor chip 104 is laminated on the central region of the upper surface of the substrate 102 in such a manner that the semiconductor chip 104 is electrically signal exchangeable via the conductive bumps 106, A stacking ball 108 is attached to the top surface of the substrate 110 in a conductive manner.

이어서, 상기 기판(102)의 상면에 걸쳐 몰딩 컴파운드 수지(110)가 몰딩되는 단계가 진행되어, 반도체 칩(104) 및 적층용 볼(108)이 봉지되는 바, 반도체 칩(104)의 상면은 열방출을 위하여 외부로 노출되도록 한다.The molding compound resin 110 is molded on the upper surface of the substrate 102 to seal the semiconductor chip 104 and the stacking ball 108. The upper surface of the semiconductor chip 104 Exposed to the outside for heat release.

연이어, 상기 몰딩 컴파운드 수지(110)의 상면에 레이저 가공에 의한 일정 깊이의 관통 몰드 비아(112: TMV, Through Mold Via)가 형성되는 바, 이 관통 몰드 비아(112)를 통하여 적층용 볼(108)이 노출되는 상태가 된다.Through-mold vias 112 having a predetermined depth are formed on the upper surface of the molding compound resin 110 by laser processing. Through the through vias 112, the lamination balls 108 ) Is exposed.

다음으로, 상기와 같이 제조된 하부 반도체 패키지(100)의 관통 몰드 비아(112)에 인터포저(200)를 적층하는 단계가 진행된다.Next, a step of laminating the interposer 200 on the through-mold via 112 of the lower semiconductor package 100 manufactured as described above proceeds.

상기 인터포저(200)는 실리콘 재질로서, 관통 실리콘 비아 또는 재배선(미도시됨) 등을 이용하여 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 매개체 역할을 한다.The interposer 200 is a silicon material and acts as an intermediary for electrically connecting the lower semiconductor package 100 and the upper semiconductor package 300 using through silicon vias or rewiring lines (not shown).

상기 인터포저(200)의 상면에는 상부 반도체 패키지(300)의 입출력단자(302)가 접속 연결되는 도전성 패드(202)가 노출되고, 저면에는 도전성 패드(202)와 통상의 관통 실리콘 비아 또는 재배선(미도시됨)에 의하여 도전 가능하게 연결되는 랜드가 형성되며, 이 랜드에 접속용 볼(204)이 융착된다.A conductive pad 202 to which the input and output terminals 302 of the upper semiconductor package 300 are connected is exposed on the upper surface of the interposer 200 and a conductive pad 202 and a common through silicon via or re- (Not shown), and a connecting ball 204 is fused to the land.

따라서, 상기 접속용 볼(204)을 관통 몰드 비아(112)내에 삽입하여 적층용 볼(108)과 접촉되게 한 후, 리플로우 공정에 의하여 상호 융착되도록 함으로써, 하부 반도체 패키지(100)에 대한 인터포저(200)의 적층이 이루어진다.Therefore, the connecting balls 204 are inserted into the through-mold vias 112 to be brought into contact with the lamination balls 108 and then fused to each other by a reflow process, The deposition of the phosphor 200 is performed.

이어서, 상기 인터포저(200)의 도전성 패드(202) 위에 상부 반도체 패키지(300)의 입출력단자(302)를 융착시킴으로써, 상부 반도체 패키지(300)의 적층이 이루어진다.The input and output terminals 302 of the upper semiconductor package 300 are fused to the conductive pads 202 of the interposer 200 to stack the upper semiconductor package 300.

한편, 상기 인터포저(200)의 도전성 패드(202) 위에 상부 반도체 패키지(300)가 적층되지 않고, 복수의 반도체 칩이 적층 부착되기도 한다.On the other hand, the upper semiconductor package 300 is not stacked on the conductive pad 202 of the interposer 200, but a plurality of semiconductor chips are stacked.

그러나, 상기한 구성으로 이루어진 종래의 패키지 온 패키지는 다음과 같은 문제점이 있다.However, the conventional package-on-package having the above-described configuration has the following problems.

상기 인터포저(200)의 접속용 볼(204)과 하부 반도체 패키지(100)의 적층용 볼(108)을 상호 접합시키는 리플로우 공정 등에서 열이 발생하는 바, 발생된 열이 하부 반도체 패키지(100)의 반도체 칩(104)과 몰딩 컴파운드 수지(110), 그리고 그 위의 인터포저(200)에 열이 전달된다.Heat is generated in a reflow process or the like in which the connecting balls 204 of the interposer 200 and the stacking balls 108 of the lower semiconductor package 100 are bonded together and the generated heat is transferred to the lower semiconductor package 100 Heat is transferred to the semiconductor chip 104, the molding compound resin 110, and the interposer 200 thereon.

이때, 상기 반도체 칩(104)과 몰딩 컴파운드 수지(110), 그리고 그 위의 인터포저(200)는 서로 다른 열패창계수를 갖기 때문에 인터포저(200)의 에지부가 휘어지는 워피지(휘어짐: warpage) 현상이 발생된다.Since the semiconductor chip 104, the molding compound resin 110, and the interposer 200 thereon have different thermal window coefficients, the warpage of the edge of the interposer 200 is warped, A phenomenon occurs.

이렇게 인터포저에 워피지 현상이 발생하면, 인터포저의 접속용 볼(204)이 적층용 볼(108)에 제대로 융착(interconnection)되지 않는 넌-웨트(non-wet) 불량 현상이 발생하는 문제점이 따른다.
If a warpage phenomenon occurs in the interposer, a non-wet defect phenomenon occurs in which the interposer connecting balls 204 are not intermixed properly with the stacking balls 108 Follow.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 안출한 것으로서, 인터포저의 저부에 하부 반도체 패키지의 몰딩 컴파운드 수지와 동일한 열팽창계수를 갖는 몰딩지지체를 몰딩해줌으로써, 인터포저의 워피지 현상을 방지할 수 있도록 한 반도체 장치 및 이의 제조 방법을 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide a molding supporting body having a thermal expansion coefficient equal to that of a molding compound resin of a lower semiconductor package, And a method of manufacturing the same.

상기한 목적을 달성하기 위한 본 발명은: 기판과, 기판 위에 도전 가능하게 부착된 반도체 칩 및 적층용 볼과, 반도체 칩과 적층용 볼을 봉지하는 몰딩 컴파운드 수지와, 적층용 볼이 노출되도록 몰딩 컴파운드 수지에 형성된 관통 몰드 비아를 포함하는 하부 반도체 패키지와; 상기 하부 반도체 패키지의 적층용 볼에 도전 가능하게 연결되며 적층되어, 하부 반도체 패키지와 상부 반도체 패키지를 도전 가능하게 연결하는 인터포저; 를 포함하되, 상기 인터포저의 저면에 몰딩 지지체를 일체로 몰딩하고, 인터포저의 접속용 볼이 하부 반도체 패키지의 적층용 볼에 융착된 후, 동일한 재질 및 열팽창계수를 갖는 몰딩 지지체와 하부 반도체 패키지의 몰딩 컴파운드 수지가 서로 인접 배열되도록 한 것을 특징으로 하는 반도체 장치를 제공한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a semiconductor chip electrically conductively attached to the substrate; a lamination ball; a molding compound resin for encapsulating the semiconductor chip and the lamination ball; A lower semiconductor package including through mold vias formed in a compound resin; An interposer electrically connected to the stacking balls of the lower semiconductor package and stacked to conductively connect the lower semiconductor package and the upper semiconductor package; Wherein the mold supporting body is integrally molded on the bottom surface of the interposer and the connecting balls of the interposer are fused to the lamination balls of the lower semiconductor package and thereafter the mold supporting body and the lower semiconductor package having the same material and thermal expansion coefficient, And the molding compound resin is arranged adjacent to each other.

바람직하게는, 상기 인터포저의 저면에 형성된 랜드에는 몰딩지지체와 수평을 이루도록 그라인딩된 지지볼이 부착되고, 이 지지볼에 접속용 볼이 융착된 것을 특징으로 한다.Preferably, the ground formed on the bottom surface of the interposer is provided with a grinding support ball so as to be horizontal with the molding support, and the connection ball is fused to the support ball.

상기한 목적을 달성하기 위한 본 발명은: 상면에 도전성 패드가 형성되고, 저면에 랜드가 형성된 인터포저 제공 단계와; 상기 인터포저의 랜드에 지지볼을 부착하는 단계와; 상기 지지볼이 봉지되도록 인터포저의 저면에 몰딩지지체를 일정 두께로 몰딩하는 단계와; 상기 몰딩지지체 및 지지볼을 일정 두께로 그라인딩하는 단계와; 그라인딩에 의하여 노출된 지지볼의 평탄면에 접속용 볼을 융착시키는 단계; 를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법을 제공한다.According to an aspect of the present invention, there is provided an interposer comprising: an interposer providing a conductive pad on a top surface thereof and a land on a bottom surface thereof; Attaching a support ball to a land of the interposer; Molding the molding support to a predetermined thickness on the bottom surface of the interposer so that the support balls are sealed; Grinding the molding support and the support balls to a predetermined thickness; Fusing a connecting ball to the flat surface of the support ball exposed by grinding; The semiconductor device manufacturing method of the present invention includes the steps of:

바람직하게는, 상기 인터포저의 접속용 볼을 하부 반도체 패키지의 관통 몰드 비아에 삽입하여 적층용 볼에 융착시키는 동시에 인터포저의 저면에 몰딩된 몰딩 지지체가 동일한 재질 및 열팽창계수를 갖는 하부 반도체 패키지의 몰딩 컴파운드 수지와 인접 배열되도록 한 인터포저 적층 단계를 더 포함하는 것을 특징으로 한다.
Preferably, the connecting balls of the interposer are inserted into the through-mold vias of the lower semiconductor package to be fused to the lamination balls, and at the same time, the molding support body molded on the bottom surface of the interposer has the same material and thermal expansion coefficient And an interposer lamination step in which the molding compound resin is arranged adjacent to the molding compound resin.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면, 하부 반도체 패키지와 상부 반도체 패키지 또는 하부 반도체 패키지와 적층 칩 간을 도전 가능하게 연결하도록 하부 반도체 패키지에 적층되는 인터포저를 워피지 방지가 가능한 구조로 개선하되, 인터포저의 저부에 하부 반도체 패키지의 몰딩 컴파운드 수지와 동일한 열팽창계수를 갖는 몰딩지지체를 몰딩시킨 구조로 개선함으로써, 패키지 온 패키지의 워피지 현상을 방지할 수 있다.According to the present invention, an interposer laminated on a lower semiconductor package to conductively connect a lower semiconductor package and an upper semiconductor package or a lower semiconductor package and a stacked chip is improved to a structure capable of preventing warpage, It is possible to prevent the warpage phenomenon of the package on package by improving the structure in which the molding support having the same thermal expansion coefficient as the molding compound resin of the lower semiconductor package is molded.

즉, 제조 공정 중 발생되는 열이 인터포저와 하부 반도체 패키지쪽으로 전달되더라도, 동일한 재질 및 열팽창계수를 갖는 인터포저의 몰딩지지체와 하부 반도체 패키지의 몰딩 컴파운드 수지가 서로 인접 배열되는 상태가 되므로, 인터포저만이 휘어지는 워피지 현상을 방지할 수 있다.That is, even if the heat generated during the manufacturing process is transferred to the interposer and the lower semiconductor package, the molding support of the interposer having the same material and thermal expansion coefficient and the molding compound resin of the lower semiconductor package are arranged adjacent to each other, It is possible to prevent a warpage phenomenon in which only a warp occurs.

또한, 워퍼지가 발생되는 원인인 열 응력을 인터포저의 몰딩지지체에서 잡아주므로, 인터포저의 수평 상태가 견고하게 유지될 수 있다.
Further, since the thermal stress, which is the cause of the wobble, is held by the molding support of the interposer, the horizontal state of the interposer can be firmly maintained.

도 1은 본 발명에 따른 반도체 장치의 인터포저 제조 과정을 나타낸 단면도,
도 2는 본 발명에 따른 반도체 장치의 인터포저를 하부 반도체 패키지에 적층하는 것을 나타낸 단면도,
도 3은 종래의 반도체 장치를 나타낸 단면도.1 is a cross-sectional view illustrating a process of fabricating an interposer of a semiconductor device according to the present invention,
FIG. 2 is a cross-sectional view illustrating the lamination of an interposer of a semiconductor device according to the present invention to a lower semiconductor package,
3 is a sectional view showing a conventional semiconductor device.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 하부 반도체 패키지와 상부 반도체 패키지가 인터포저에 의하여 도전 가능하게 적층되는 패키지 온 패키지로서, 인터포저의 저부에 하부 반도체 패키지의 몰딩 컴파운드 수지와 동일한 열팽창계수를 갖는 몰딩지지체를 몰딩해줌으로써, 인터포저의 워피지 현상을 방지할 수 있도록 한 점에 주안점이 있다.The present invention relates to a package-on-package, in which a lower semiconductor package and an upper semiconductor package are electrically stacked by an interposer, wherein a molding support having a thermal expansion coefficient equal to that of the molding compound resin of the lower semiconductor package is molded at the bottom of the interposer, There is one point to be able to prevent the warpage phenomenon of the interposer.

첨부한 도 1은 본 발명에 따른 반도체 장치의 인터포저 제조 과정을 나타낸 단면도이고, 도 2는 본 발명에 따른 반도체 장치의 인터포저를 하부 반도체 패키지에 적층하는 것을 나타낸 단면도이다.FIG. 1 is a cross-sectional view illustrating a process of fabricating an interposer of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view illustrating stacking of an interposer of a semiconductor device according to the present invention in a lower semiconductor package.

먼저, 상기 하부 반도체 패키지(100)를 제조하고자, 기판(102)의 상면 중앙영역에 반도체 칩(104)이 도전성 범프(106)를 매개로 전기적 신호 교환 가능하게 적층 부착되고, 또한 기판(102)의 상면 테두리 영역에는 적층용 볼(108)이 도전 가능하게 부착된다.A semiconductor chip 104 is laminated on the central region of the upper surface of the substrate 102 in such a manner that the semiconductor chip 104 is electrically signal exchangeable via the conductive bumps 106, A stacking ball 108 is attached to the top surface of the substrate 110 in a conductive manner.

이어서, 상기 기판(102)의 상면에 걸쳐 몰딩 컴파운드 수지(110)가 몰딩되는 단계가 진행되어, 반도체 칩(104) 및 적층용 볼(108)이 봉지되는 바, 반도체 칩(104)의 상면은 열방출을 위하여 외부로 노출되도록 한다.The molding compound resin 110 is molded on the upper surface of the substrate 102 to seal the semiconductor chip 104 and the stacking ball 108. The upper surface of the semiconductor chip 104 Exposed to the outside for heat release.

연이어, 상기 몰딩 컴파운드 수지(110)의 상면에 레이저 가공에 의한 일정 깊이의 관통 몰드 비아(112: TMV, Through Mold Via)가 형성되는 바, 이 관통 몰드 비아(112)를 통하여 적층용 볼(108)이 노출되는 상태가 된다.Through-mold vias 112 having a predetermined depth are formed on the upper surface of the molding compound resin 110 by laser processing. Through the through vias 112, the lamination balls 108 ) Is exposed.

다음으로, 상기와 같이 제조된 하부 반도체 패키지(100)의 관통 몰드 비아(112)에 인터포저(200)를 적층하는 단계가 진행되는 바, 인터포저(200)는 실리콘 재질로서, 관통 실리콘 비아 또는 재배선(미도시됨) 등을 이용하여 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 매개체 역할을 한다.Next, the interposer 200 is laminated on the through-mold via 112 of the lower semiconductor package 100 manufactured as described above. The interposer 200 is a silicon material, And serves as an intermediary for electrically connecting the lower semiconductor package 100 and the upper semiconductor package 300 using rewiring lines (not shown).

본 발명에 따른 인터포저(200)는 저면에 몰딩 지지체(210)가 일정 두께로 몰딩된 구조로 구비되며, 인터포저(200)의 접속용 볼(204)이 하부 반도체 패키지(100)의 적층용 볼(108)에 융착될 때, 동일한 재질 및 열팽창계수를 갖는 몰딩 지지체(210)가 하부 반도체 패키지(100)의 몰딩 컴파운드 수지(110) 위에 인접 배열된다.The interposer 200 according to the present invention has a structure in which the molding support 210 is molded to a predetermined thickness on the bottom surface and the connecting balls 204 of the interposer 200 are stacked on the lower semiconductor package 100 When fused to the ball 108, a molding support 210 having the same material and thermal expansion coefficient is disposed adjacent to the molding compound resin 110 of the lower semiconductor package 100.

여기서, 본 발명에 따른 인터포저를 제조하는 과정을 좀 더 상세하게 설명하면 다음과 같다.Hereinafter, the process of manufacturing the interposer according to the present invention will be described in more detail.

도 1에서 보듯이, 먼저 상면에 도전성 패드(202)가 형성되고, 저면에 랜드(206)가 형성된 인터포저(200)를 구비한 다음, 이 인터포저(200)의 랜드(206)에 지지볼(212)을 융착시킨다.1, an interposer 200 having a conductive pad 202 formed on an upper surface thereof and a land 206 formed on a bottom surface of the interposer 200 is mounted on a land 206 of the interposer 200, (212).

다음으로, 상기 인터포저(200)의 저면에 걸쳐 일정 두께의 몰딩지지체(210)를 몰딩하는 동시에 몰딩지지체(210)내에 지지볼(212)이 봉지되는 상태가 되도록 한다.Next, the molding support body 210 having a predetermined thickness is molded on the bottom surface of the interposer 200, and the support balls 212 are sealed in the molding support body 210.

연이어, 상기 몰딩지지체(210) 및 지지볼(212)을 일정 두께로 그라인딩하여, 몰딩지지체(210)와 지지볼(212)의 그라인딩면이 서로 수평을 이루는 평평한 상태가 되도록 한다.Subsequently, the molding support 210 and the support ball 212 are ground to a predetermined thickness so that the molding support 210 and the support ball 212 are in a flat state in which the grinding surfaces of the molding support 210 and the support ball 212 are parallel to each other.

이어서, 그라인딩에 의하여 노출된 지지볼(212)의 평탄면에 하부 반도체 패키지와의 전기적 접속을 위한 접속용 볼(204)을 융착시키는 단계가 진행된다.Then, a step of fusing the connection ball 204 for electrical connection with the lower semiconductor package is performed on the flat surface of the support ball 212 exposed by the grinding.

이와 같이, 상기 인터포저(200)의 저면에 형성된 랜드(206)에 지지볼(212)을 부착한 다음, 몰딩지지체(210)로 몰딩하고, 다시 그라인딩을 통하여 노출된 지지볼(212)의 평탄면에 접속용 볼(204)을 융착함으로써, 본 발명의 인터포저가 완성된다.As described above, the support ball 212 is attached to the land 206 formed on the bottom surface of the interposer 200, and then molded with the molding support 210. Then, the support ball 212 exposed through the grinding is flattened The connection ball 204 is fused to the surface of the interposer of the present invention.

이렇게 완성된 인터포저(200)를 도 1에서 보듯이 하부 반도체 패키지(100)에 적층하게 된다.The completed interposer 200 is stacked on the lower semiconductor package 100 as shown in FIG.

즉, 상기 인터포저(200)의 접속용 볼(204)을 하부 반도체 패키지(100)의 관통 몰드 비아(112)에 삽입하여 적층용 볼(108)에 융착시킴으로써, 하부 반도체 패키지(100)에 대한 인터포저(200)의 적층이 이루어지고, 이와 동시에 인터포저(200)의 저면에 몰딩된 몰딩 지지체(210)가 동일한 재질 및 열팽창계수를 갖는 하부 반도체 패키지(100)의 몰딩 컴파운드 수지(110)와 인접 배열되는 상태가 된다.That is, by inserting the connecting balls 204 of the interposer 200 into the through-mold vias 112 of the lower semiconductor package 100 and fusing them to the stacking balls 108, The interposer 200 is laminated and at the same time the molding supporting body 210 molded on the bottom surface of the interposer 200 is molded with the molding compound resin 110 of the lower semiconductor package 100 having the same material and thermal expansion coefficient They are arranged adjacent to each other.

따라서, 제조 공정 중 발생되는 열이 인터포저(200)와 하부 반도체 패키지(100)쪽으로 전달되더라도, 동일한 재질 및 열팽창계수를 갖는 인터포저(200)의 몰딩지지체(210)와 하부 반도체 패키지(100)의 몰딩 컴파운드 수지(110)가 서로 인접 배열되는 상태가 되므로, 인터포저(200)만이 휘어지는 워피지 현상을 방지할 수 있고, 또한 워퍼지가 발생되는 원인인 열 응력을 인터포저(200)의 몰딩지지체(210)에서 잡아주게 되므로, 인터포저의 수평 상태가 견고하게 유지될 수 있다.
Therefore, even if the heat generated during the manufacturing process is transferred to the interposer 200 and the lower semiconductor package 100, the molding support 210 of the interposer 200 having the same material and thermal expansion coefficient, Since the molding compound resin 110 of the interposer 200 is arranged adjacent to the interposer 200, it is possible to prevent the warpage phenomenon in which only the interposer 200 is warped, So that the horizontal state of the interposer can be firmly maintained.

100 : 하부 반도체 패키지
102 : 기판
104 : 반도체 칩
106 : 도전성 범프
108 : 적층용 볼
110 : 몰딩 컴파운드 수지
112 : 관통 몰드 비아
200 : 인터포저
202 : 도전성 패드
204 : 접속용 볼
206 : 랜드
210 : 몰딩지지체
212 : 지지볼
300 : 상부 반도체 패키지
302 : 입출력단자100: lower semiconductor package
102: substrate
104: semiconductor chip
106: conductive bump
108:
110: Molding compound resin
112: Through Mold Via
200: interposer
202: conductive pad
204: connecting ball
206: Land
210: molding support
212: support ball
300: upper semiconductor package
302: I / O terminal

Claims (4)

기판(102)과, 기판(102) 위에 도전 가능하게 부착된 반도체 칩(104) 및 적층용 볼(108)과, 반도체 칩(104)과 적층용 볼(108)을 봉지하는 몰딩 컴파운드 수지(110)와, 적층용 볼(108)이 노출되도록 몰딩 컴파운드 수지(110)에 형성된 관통 몰드 비아(112)를 포함하는 하부 반도체 패키지(100)와;
상기 하부 반도체 패키지(100)의 적층용 볼(108)에 도전 가능하게 연결되며 적층되어, 하부 반도체 패키지(100)와 상부 반도체 패키지(300)를 도전 가능하게 연결하는 인터포저(200);
를 포함하되,
상기 인터포저(200)의 저면에 몰딩 지지체(210)를 일체로 몰딩하고, 인터포저(200)의 접속용 볼(204)이 하부 반도체 패키지(100)의 적층용 볼(108)에 융착된 후, 동일한 재질 및 열팽창계수를 갖는 몰딩 지지체(210)와 하부 반도체 패키지(100)의 몰딩 컴파운드 수지(110)가 서로 인접 배열되도록 한 것을 특징으로 하는 반도체 장치.
A semiconductor chip 104 and a stacking ball 108 electrically conductive on the substrate 102 and a molding compound resin 110 for sealing the semiconductor chip 104 and the stacking ball 108 And a through-mold via 112 formed in the molding compound resin 110 such that the stacking ball 108 is exposed;
An interposer 200 electrically connected to the stacking ball 108 of the lower semiconductor package 100 and stacked to conductively connect the lower semiconductor package 100 and the upper semiconductor package 300;
, ≪ / RTI &
The molding supporting body 210 is integrally molded on the bottom surface of the interposer 200 and the connecting balls 204 of the interposer 200 are fused to the stacking balls 108 of the lower semiconductor package 100 , The molding support body (210) having the same material and thermal expansion coefficient and the molding compound resin (110) of the lower semiconductor package (100) are arranged adjacent to each other.
청구항 1에 있어서,
상기 인터포저(200)의 저면에 형성된 랜드(206)에는 몰딩지지체(210)와 수평을 이루도록 그라인딩된 지지볼(212)이 부착되고, 이 지지볼(212)에 접속용 볼(204)이 융착된 것을 특징으로 하는 반도체 장치.
The method according to claim 1,
A grinding support ball 212 is attached to the land 206 formed on the bottom surface of the interposer 200 so as to be horizontal with the molding support body 210. The connection ball 204 is welded to the support ball 212 Wherein the semiconductor device is a semiconductor device.
상면에 도전성 패드(202)가 형성되고, 저면에 랜드(206)가 형성된 인터포저(200) 제공 단계와;
상기 인터포저(200)의 랜드(206)에 지지볼(212)을 부착하는 단계와;
상기 지지볼(212)이 봉지되도록 인터포저(200)의 저면에 몰딩지지체(210)를 일정 두께로 몰딩하는 단계와;
상기 몰딩지지체(210) 및 지지볼(212)을 일정 두께로 그라인딩하는 단계와;
그라인딩에 의하여 노출된 지지볼(212)의 평탄면에 접속용 볼(204)을 융착시키는 단계;
를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.
Providing an interposer (200) having a conductive pad (202) formed on its upper surface and a land (206) formed on its lower surface;
Attaching a support ball (212) to a land (206) of the interposer (200);
Molding the molding support 210 to a predetermined thickness on the bottom surface of the interposer 200 so that the support ball 212 is sealed;
Grinding the molding support 210 and the support ball 212 to a predetermined thickness;
Fusing the connecting balls 204 to the flat surface of the support balls 212 exposed by grinding;
Wherein the semiconductor device is a semiconductor device.
청구항 3에 있어서,
상기 인터포저(200)의 접속용 볼(204)을 하부 반도체 패키지(100)의 관통 몰드 비아(112)에 삽입하여 적층용 볼(108)에 융착시키는 동시에 인터포저(200)의 저면에 몰딩된 몰딩 지지체(210)가 동일한 재질 및 열팽창계수를 갖는 하부 반도체 패키지(100)의 몰딩 컴파운드 수지(110)와 인접 배열되도록 한 인터포저 적층 단계를 더 포함하는 것을 특징으로 하는 반도체 장치 제조 방법.The method of claim 3,
The connecting balls 204 of the interposer 200 are inserted into the through vias 112 of the lower semiconductor package 100 to be fused to the stacking balls 108, Wherein the molding support (210) is arranged adjacent to the molding compound resin (110) of the lower semiconductor package (100) having the same material and thermal expansion coefficient.
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Publication number Priority date Publication date Assignee Title
CN111052368A (en) * 2017-09-28 2020-04-21 英特尔公司 Active silicon-on-package semiconductor package
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