KR101099578B1 - Stack Chip Package using RDL and TSV - Google Patents

Stack Chip Package using RDL and TSV Download PDF

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KR101099578B1
KR101099578B1 KR1020090105427A KR20090105427A KR101099578B1 KR 101099578 B1 KR101099578 B1 KR 101099578B1 KR 1020090105427 A KR1020090105427 A KR 1020090105427A KR 20090105427 A KR20090105427 A KR 20090105427A KR 101099578 B1 KR101099578 B1 KR 101099578B1
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chip
redistribution
stacked
tsv
molding resin
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KR20110048733A (en
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임호정
이지훈
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앰코 테크놀로지 코리아 주식회사
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Abstract

본 발명은 재배선 및 TSV를 이용한 적층 칩 패키지에 관한 것으로서, 더욱 상세하게는 TSV가 형성된 하부칩과, 이 하부칩의 상면에 동일 수평선상을 이루며 재배선에 의하여 적층되는 다수개의 메모리 칩으로 구성되는 새로운 구조의 재배선 및 TSV를 이용한 적층 칩 패키지에 관한 것이다.The present invention relates to a stacked chip package using redistribution and TSV, and more particularly, to a lower chip on which TSV is formed, and a plurality of memory chips stacked by redistribution on the same horizontal line on the upper surface of the lower chip. The present invention relates to a multilayer chip package using a redistribution and TSV.

이를 위해, 본 발명은 기판과; 전체 면적에 걸쳐 다수의 관통 실리콘 비아가 소정의 배열로 형성된 구조로서, 상기 기판상에 탑재되는 하부칩과; 상기 하부칩의 관통 실리콘 비아와 상기 기판상의 전도성패턴간을 통전 가능하게 연결하는 플립칩과; 상기 하부칩을 포함하여 기판상에 몰딩되는 하부 몰딩수지와; 일측단부는 상기 하부칩의 관통 실리콘 비아와 연결되면서 하부 몰딩수지의 표면상에 소정의 배열로 형성되는 재배선과; 상기 재배선의 타측단부에 전도성범프를 매개로 통전 가능하게 연결되면서 상기 하부 몰딩수지의 표면상에 적층되는 다수의 상부칩과; 상기 상부칩 및 재배선을 봉지하도록 하부 몰딩수지의 전체 표면에 걸쳐 몰딩되는 상부 몰딩수지; 를 포함하여 구성된 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지를 제공한다.To this end, the present invention is a substrate; A structure in which a plurality of through silicon vias are formed in a predetermined arrangement over an entire area, the lower chip mounted on the substrate; A flip chip electrically connecting a through silicon via of the lower chip to a conductive pattern on the substrate; A lower molding resin molded on a substrate including the lower chip; A redistribution line having one end portion connected to the through silicon via of the lower chip and formed in a predetermined arrangement on the surface of the lower molding resin; A plurality of upper chips stacked on the surface of the lower molding resin while being electrically connected to the other end of the redistribution via conductive bumps; An upper molding resin molded over the entire surface of the lower molding resin to encapsulate the upper chip and the redistribution line; It provides a stacked chip package using a redistribution and TSV, characterized in that configured to include.

반도체 패키지, 재배선, TSV, 기판, 하부칩, 상부칩, 몰딩수지 Semiconductor Package, Rewiring, TSV, Substrate, Lower Chip, Upper Chip, Molding Resin

Description

재배선 및 ＴＳＶ를 이용한 적층 칩 패키지{Stack Chip Package using RDL and TSV}Stacked chip package using redistribution and TSS {Stack Chip Package using RDL and TSV}

본 발명은 재배선 및 TSV를 이용한 적층 칩 패키지에 관한 것으로서, 더욱 상세하게는 TSV(Through Silicon Via, 이하 관통 실리콘 비아로 칭함)가 형성된 하부칩과, 이 하부칩의 상면에 동일 수평선상을 이루며 재배선에 의하여 적층되는 다수개의 상부칩으로 구성되는 새로운 구조의 재배선 및 TSV를 이용한 적층 칩 패키지에 관한 것이다.The present invention relates to a stacked chip package using redistribution and TSV. More particularly, the present invention relates to a lower chip on which a TSV (Through Silicon Via, hereinafter referred to as a through silicon via) is formed, and formed on the same horizontal line on the upper surface of the lower chip. The present invention relates to a redistribution of a new structure consisting of a plurality of upper chips stacked by redistribution and a stacked chip package using a TSV.

반도체 집적회로의 패키징 기술중 3차원 적층 패키지는 동일한 기억 용량의 칩을 복수개 적층한 패키지로서, 이를 통상 적층 칩 패키지(Stack Chip Package)라 한다.The three-dimensional stacked package of the packaging technology of a semiconductor integrated circuit is a package in which a plurality of chips having the same storage capacity are stacked, which is commonly referred to as a stacked chip package.

기존의 적층 칩 반도체 패키지는 기판의 칩부착영역에 복수개의 칩이 적층 부착되는 조건에서, 각 칩의 본딩패드와 기판의 전도성회로패턴간을 전기적 신호 교환을 위한 와이어로 통전 가능하게 연결하는 구조로 제조됨에 따라, 결국 패키지 내에 와이어 본딩을 위한 공간이 필요하고, 또한 와이어가 연결되는 기판의 전도성회로패턴 면적이 필요하여, 결국 반도체 패키지의 크기 및 높이가 증가되는 단점이 있다.Existing multilayer chip semiconductor package is a structure that connects electrically between a bonding pad of each chip and a conductive circuit pattern of the substrate with a wire for electrical signal exchange under the condition that a plurality of chips are stacked and attached to the chip attachment region of the substrate. As it is manufactured, eventually a space for wire bonding in the package is required, and also a conductive circuit pattern area of the substrate to which the wire is connected is required, which in turn increases the size and height of the semiconductor package.

이러한 점을 감안하여, 와이어 대신 관통 실리콘 비아를 이용하여 칩을 적층할 수 있는 구조 즉, 칩 내에 관통 실리콘 비아를 형성하고, 이 관통 실리콘 비아를 통해 여러개의 칩을 수직방향으로 쌓아 올리는 적층 칩 패키지가 제안되고 있다.In view of this, a stacked chip package in which a chip is stacked using a through silicon via instead of a wire, that is, a through silicon via is formed in the chip, and the plurality of chips are stacked vertically through the through silicon via. Is being proposed.

첨부한 도 3은 종래에 칩에 관통 실리콘 비아(TSV) 형성하는 과정을 설명하는 단면도이다.3 is a cross-sectional view illustrating a process of forming a through silicon via (TSV) in a chip.

먼저, 웨이퍼 레벨에서 각 칩(100)의 본딩패드(123)에서 그 인접부분에 수직홀(112)을 형성하고, 이 수직홀(112)의 표면에 절연막(미도시됨)을 형성한다.First, a vertical hole 112 is formed in the bonding pad 123 of each chip 100 at the wafer level, and an insulating film (not shown) is formed on the surface of the vertical hole 112.

상기 절연막 상에 씨드 금속막을 형성한 상태로, 상기 수직홀(112) 내에 전해도금 공정을 통해 전해 물질, 즉 전도성 금속(114)을 매립해서 관통 실리콘 비아(116)를 형성하게 되고, 이때 칩(100)의 본딩패드와 전도성 금속(114)은 재배선(RDL:ReDistribution Line) 등을 이용하여 전기적으로 연결된다.In the state where the seed metal film is formed on the insulating layer, an electrolytic material, ie, a conductive metal 114, is embedded in the vertical hole 112 to form a through silicon via 116. The bonding pad of the 100 and the conductive metal 114 are electrically connected using a redistribution line (RDL).

다음으로, 웨이퍼의 후면을 백그라인딩(back grinding)하여 상기 관통 실리콘 비아(116)에 매립된 전도성 금속(114)의 하단부를 외부로 노출시킨다.Next, the back surface of the wafer is back ground to expose the lower end portion of the conductive metal 114 embedded in the through silicon via 116 to the outside.

이어서, 기판 상에 적어도 둘 이상의 칩을 관통 실리콘 비아(116)의 전도성 금속(114)를 통해 신호 교환 가능하게 수직으로 쌓아올려 적층시킨다.Subsequently, at least two or more chips are stacked and stacked vertically on the substrate so as to be signal exchangeable through the conductive metal 114 of the through silicon via 116.

보다 상세하게는, 서로 적층된 상부칩(100a)과 하부칩(100b)간의 전기적 연 결 구조를 보면, 상부칩(100a)의 관통 실리콘 비아(116)를 통해 저부로 노출된 전도성 금속(114)과, 하부칩(100b)의 관통 실리콘 비아(116)를 통해 상부로 노출된 전도성 금속(114)간이 전도성 범프(118)에 의하여 서로 전기적으로 연결된다.More specifically, in the electrical connection structure between the upper chip 100a and the lower chip 100b stacked on each other, the conductive metal 114 exposed to the bottom through the through-silicon vias 116 of the upper chip 100a. And the conductive metal 114 exposed upward through the through silicon vias 116 of the lower chip 100b are electrically connected to each other by the conductive bumps 118.

그러나, 여러개의 칩을 수직방향으로 적층함에 따라 각 칩에 관통 실리콘 비아를 형성하여 서로 전기적으로 연결하는 구조가 복잡해지는 단점이 있다.However, as a plurality of chips are stacked in a vertical direction, a structure in which through silicon vias are formed on each chip and electrically connected to each other is complicated.

특히, 관통 실리콘 비아를 형성하는 공정수가 증가함과 더불어 제조비용이 증가하는 단점이 있으며, 또한 여러개의 칩이 수직방향으로 적층됨에 따라 패키지의 두께도 증가되는 단점이 있다.In particular, the number of processes for forming through silicon vias increases, as well as an increase in manufacturing cost. Also, as a plurality of chips are stacked in a vertical direction, a thickness of a package also increases.

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 관통 실리콘 비아가 형성된 펑션 칩인 하부칩과, 이 하부칩의 상면에 동일 수평선상을 이루며 재배선에 의하여 적층되는 다수개의 메모리 칩인 상부칩들로 구성하여, 칩이 적층된 상태에서 패키지의 높이를 최소화시킬 수 있고, 수직방향으로만 적층되는 칩에 비하여 동일수평선상에 칩이 적층됨에 따라 열방출 면적이 고르게 분산되어 열방출 효과를 크게 얻을 수 있는 새로운 구조의 재배선 및 TSV를 이용한 적층 칩 패키지를 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and includes a lower chip which is a function chip having through silicon vias formed thereon, and an upper chip which is a plurality of memory chips stacked on the upper surface of the lower chip by a redistribution line. In this case, the height of the package can be minimized in the state where the chips are stacked, and as the chips are stacked on the same horizontal line as the chips stacked only in the vertical direction, the heat dissipation area is evenly distributed, thereby obtaining a large heat dissipation effect. The purpose of the present invention is to provide a multilayer chip package using a new structure redistribution and TSV.

상기한 목적을 달성하기 위한 본 발명은 기판과; 전체 면적에 걸쳐 다수의 관통 실리콘 비아가 소정의 배열로 형성된 구조로서, 상기 기판상에 탑재되는 하부칩과; 상기 하부칩의 관통 실리콘 비아와 상기 기판상의 전도성패턴간을 통전 가능하게 연결하는 플립칩과; 상기 하부칩을 포함하여 기판상에 몰딩되는 하부 몰딩수지와; 일측단부는 상기 하부칩의 관통 실리콘 비아와 연결되면서 하부 몰딩수지의 표면상에 소정의 배열로 형성되는 재배선과; 상기 재배선의 타측단부에 전도성범프를 매개로 통전 가능하게 연결되면서 상기 하부 몰딩수지의 표면상에 적층되는 다수의 상부칩과; 상기 상부칩 및 재배선을 봉지하도록 하부 몰딩수지의 전체 표면에 걸쳐 몰딩되는 상부 몰딩수지; 를 포함하여 구성된 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지를 제공한다.The present invention for achieving the above object and a substrate; A structure in which a plurality of through silicon vias are formed in a predetermined arrangement over an entire area, the lower chip mounted on the substrate; A flip chip electrically connecting a through silicon via of the lower chip to a conductive pattern on the substrate; A lower molding resin molded on a substrate including the lower chip; A redistribution line having one end portion connected to the through silicon via of the lower chip and formed in a predetermined arrangement on the surface of the lower molding resin; A plurality of upper chips stacked on the surface of the lower molding resin while being electrically connected to the other end of the redistribution via conductive bumps; An upper molding resin molded over the entire surface of the lower molding resin to encapsulate the upper chip and the redistribution line; It provides a stacked chip package using a redistribution and TSV, characterized in that configured to include.

본 발명의 바람직한 구현예로서, 상기 하부 몰딩수지상에 4개의 상부칩이 적층 부착되되, 각 상부칩의 모서리 영역이 하부칩의 각 모서리 영역과 겹쳐지도록 적층되는 것을 특징으로 한다.As a preferred embodiment of the present invention, four upper chips are stacked and attached to the lower molding resin, and the edge regions of each upper chip are stacked to overlap each corner region of the lower chip.

특히, 상기 하부칩은 펑션 칩이고, 상기 상부칩들은 메모리 칩인 것을 특징으로 한다.In particular, the lower chip is a function chip, the upper chip is characterized in that the memory chip.

또한, 상기 하부 몰딩수지는 재배선의 형성 두께를 고려하여 하부칩의 높이보다 높게 몰딩되는 것을 특징으로 한다.In addition, the lower molding resin is characterized in that the molding is higher than the height of the lower chip in consideration of the thickness of the redistribution.

본 발명의 바람직한 구현예로서, 상기 재배선은: 하부칩의 관통 실리콘 비아와 연결되면서 하부칩의 각 모서리 영역내까지 연장되는 단배선과; 하부칩의 관통 실리콘 비아와 연결되면서 하부칩의 상면에서 벗어난 소정 위치까지 연장되는 장배 선으로 구성되는 것을 특징으로 한다.In a preferred embodiment of the present invention, the redistribution includes: a single wiring connected to the through silicon via of the lower chip and extending into each corner region of the lower chip; It is characterized in that it is connected to the through-silicon vias of the lower chip is composed of a long line extending to a predetermined position deviating from the upper surface of the lower chip.

특히, 상기 재배선은 하부 몰딩수지상에 레이저 가공을 이용하여 경로홈을 형성하고, 경로홈내에 스퍼터링 또는 플레이팅에 의하여 형성되는 것을 특징으로 한다.In particular, the redistribution is characterized in that the path groove is formed by laser processing on the lower molding resin, and formed by sputtering or plating in the path groove.

본 발명의 바람직한 구현예로서, 상기 하부칩의 모서리 영역과 겹쳐지는 상부칩의 모서리영역내에 배열된 본딩패드가 상기 단배선의 타측단부와 전도성범프를 매개로 연결되고, 상기 하부칩의 상면에서 벗어난 영역에서의 상부칩의 본딩패드가 상기 장배선의 타측단부와 전도성범프를 매개로 연결되는 것을 특징으로 한다.In a preferred embodiment of the present invention, the bonding pads arranged in the corner region of the upper chip overlapping the corner region of the lower chip are connected to the other end of the short wiring via the conductive bumps, and deviate from the upper surface of the lower chip. Bonding pads of the upper chip in the region is characterized in that connected to the other end of the long wiring via the conductive bumps.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above problem solving means, the present invention provides the following effects.

본 발명에 따르면, 관통 실리콘 비아가 형성된 펑션 칩인 하부칩을 기판상에 부착하고, 하부칩의 상면 모서리 위치에 동일 수평선상을 이루며 재배선에 의하여 적층되는 다수개의 메모리 칩인 상부칩을 적층함으로써, 기존의 관통 실리콘 비아만을 이용하여 여러개의 칩을 수직으로 적층하던 패키지에 비하여 그 두께를 현격하게 줄여서 경박단소화를 실현할 수 있다.According to the present invention, by attaching a lower chip, which is a function chip on which a through silicon via is formed, on a substrate, and stacking the upper chip, which is a plurality of memory chips stacked by redistribution on the same horizontal line at the upper edge of the lower chip, By using only through-silicon vias, the thickness can be significantly reduced compared to a package in which several chips are stacked vertically, thereby realizing light and small size reduction.

특히, 하부칩의 각 모서리 위치에 겹쳐지면서 다수개의 상부칩이 수평방향을 따라 넓게 분포되는 식으로 적층됨에 따라, 각 칩의 열방출 면적이 고르게 분산되는 동시에 증대되어 열방출 효과를 크게 얻어낼 수 있다.In particular, as a plurality of upper chips are stacked in such a manner that they are widely distributed along the horizontal direction while overlapping the corners of the lower chips, the heat dissipation area of each chip is evenly distributed and increased to obtain a large heat dissipation effect. have.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명에 따른 재배선 및 TSV를 이용한 적층 칩 패키지 및 그 제조 방법을 설명하는 종단면도이고, 도 2는 본 발명에 따른 재배선 및 TSV를 이용한 적층 칩 패키지를 나타내는 횡단면도이다.1 is a longitudinal cross-sectional view illustrating a multilayer chip package using a redistribution and TSV and a method of manufacturing the same according to the present invention, and FIG. 2 is a cross-sectional view illustrating a multilayer chip package using a redistribution and TSV according to the present invention.

먼저, 인쇄회로기판과 같은 기판(10)상에 중앙부에 구획된 칩부착영역에 전체 면적에 걸쳐 소정의 배열을 이루며 다수의 관통 실리콘 비아(14)가 형성된 하부칩(12)을 부착한다.First, a lower chip 12 having a plurality of through silicon vias 14 formed in a predetermined arrangement over the entire area is attached to a chip attaching region partitioned at a central portion on a substrate 10 such as a printed circuit board.

즉, 상기 하부칩(14)의 저면을 통해 노출된 관통 실리콘 비아(14)와 상기 기판(10)상의 전도성패턴(16)간을 플립칩(18)을 이용하여 통전 가능하게 연결시킴으로써, 기판(10)상에 하부칩(12)의 부착이 이루어진다.That is, the through silicon via 14 exposed through the bottom surface of the lower chip 14 and the conductive pattern 16 on the substrate 10 are electrically connected using the flip chip 18 to enable the substrate ( Attachment of the lower chip 12 is made on 10).

다음으로, 기판(10)상에 몰딩 공정이 진행됨에 따라, 상기 하부칩(12)을 봉지시키면서 기판(10)의 전체 표면에 걸쳐 하부 몰딩수지(20)가 형성되는 바, 이 하부 몰딩수지(20)는 재배선(30)의 형성 두께만큼 하부칩(12)의 높이보다 높게 몰딩되도록 한다.Next, as the molding process proceeds on the substrate 10, the lower molding resin 20 is formed over the entire surface of the substrate 10 while encapsulating the lower chip 12. 20 to be molded higher than the height of the lower chip 12 by the thickness of the redistribution (30).

이어서, 상기 하부 몰딩수지(20)의 표면에 다수의 재배선(30)을 형성하게 되는데, 각 재배선(30)의 형성을 위하여 우선 하부 몰딩수지(20)의 표면에 레이저 가공을 이용하여 재배선의 경로가 되는 경로홈을 오목하게 가공하고, 이 경로홈내에 스퍼터링 또는 플레이팅 방법을 이용하여 도전 재질의 재배선을 증착하게 된다.Subsequently, a plurality of redistribution lines 30 are formed on the surface of the lower molding resin 20. For the formation of each redistribution line 30, cultivation is performed on the surface of the lower molding resin 20 using laser processing. The path grooves serving as the paths of the lines are recessed, and the redistribution of the conductive material is deposited by sputtering or plating in the path grooves.

이때, 각 재배선(30)의 일측단부는 하부칩(12)의 관통 실리콘 비아(14)중 하나와 통전 가능하게 연결되는 상태가 되고, 타측단부는 하부 몰딩수지(20)의 표면상에 형성된 경로홈내에 소정의 배열을 이루며 연장 형성되어 상부칩(22)과의 접속단자 역할을 하게 된다.At this time, one end of each redistribution 30 is in a state that is electrically connected to one of the through-silicon vias 14 of the lower chip 12, the other end is formed on the surface of the lower molding resin (20) It extends in a predetermined arrangement in the path groove and serves as a connection terminal with the upper chip 22.

특히, 총 4개의 상부칩(22)이 하부칩(12)의 각 모서리 영역상에 적층됨에 따라, 상기 재배선(30)을 단배선(32)과 장배선(34)으로 구분하여 형성하게 된다.In particular, as a total of four upper chips 22 are stacked on each corner area of the lower chip 12, the redistribution 30 is divided into a single wiring 32 and a long wiring 34. .

보다 상세하게는, 상기 재배선(32)의 각 단배선(32)은 그 일측단부가 하부칩(12)의 관통 실리콘 비아(14)중 하나와 통전 가능하게 연결되는 동시에 타측단부는 하부칩(12)의 각 모서리 영역내까지 연장되고, 또한 상기 재배선(32)의 각 장배선(34)은 그 일측단부가 하부칩(12)의 관통 실리콘 비아(14)중 하나와 통전 가능하게 연결되는 동시에 타측단부는 하부칩(12)의 상면에서 벗어난 소정 위치까지 연장된다.In more detail, each single end wiring 32 of the redistribution wire 32 has one end thereof electrically connected to one of the through-silicon vias 14 of the bottom chip 12 while the other end thereof has a bottom chip ( 12 and extends into each corner region of the redistribution 32, and one end of each of the redistribution lines 32 is electrically connected to one of the through silicon vias 14 of the lower chip 12. At the same time, the other end extends to a predetermined position deviating from the upper surface of the lower chip 12.

다음으로, 상기 하부 몰딩수지(20)의 상면에 걸쳐 총 4개의 상부칩(22)을 동일 수평선상을 이루도록 소정의 배열로 부착하게 된다.Next, a total of four upper chips 22 over the upper surface of the lower molding resin 20 is attached in a predetermined arrangement to form the same horizontal line.

즉, 상기 하부 몰딩수지(20)상에 총 4개의 상부칩(22)이 적층 부착되되, 각 상부칩(22)의 한쪽 모서리 영역이 하부칩(12)의 각 모서리 영역과 겹쳐지도록 적층된다.That is, a total of four upper chips 22 are stacked and attached to the lower molding resin 20 so that one corner region of each upper chip 22 overlaps each corner region of the lower chip 12.

이때, 상기 상부칩(22)의 본딩패드(36)가 재배선(30)의 타측단부에 전도성범프(23)를 매개로 통전 가능하게 연결된다.In this case, the bonding pads 36 of the upper chip 22 may be electrically connected to the other end of the redistribution line 30 via the conductive bumps 23.

보다 상세하게는, 상기 하부칩(12)의 모서리 영역과 겹쳐지는 상부칩(22)의 한쪽 모서리영역내의 각 본딩패드(36)가 상기 재배선의 각 단배선(32)의 타측단부와 전도성범프(38)를 매개로 연결되고, 또한 상기 하부칩(12)의 상면에서 벗어난 영역에서의 상부칩(22)의 나머지 각 본딩패드(36)가 상기 장배선(34)의 타측단부와 전도성범프(38)를 매개로 통전 가능하게 연결된다.More specifically, each bonding pad 36 in one corner region of the upper chip 22 overlapping the corner region of the lower chip 12 may have the other end portion and the conductive bump ( 38, and the remaining bonding pads 36 of the upper chip 22 in the region deviated from the upper surface of the lower chip 12 are connected to the other end of the long wiring 34 and the conductive bumps 38. It is connected so that it can be energized.

한편, 상기 하부칩(12)은 펑션 칩이고, 하부칩(12)상에 각 모서리 영역에 적층되는 총 4개의 상부칩(22)은 메모리 칩으로 적용된다.Meanwhile, the lower chip 12 is a function chip, and a total of four upper chips 22 stacked in each corner area on the lower chip 12 are applied as memory chips.

마지막으로, 상기 상부칩(22)들과 재배선(30)을 봉지하도록 하부 몰딩수지(20)의 전체 표면이 상부 몰딩수지(24)로 몰딩된다.Finally, the entire surface of the lower molding resin 20 is molded into the upper molding resin 24 to encapsulate the upper chips 22 and the rewiring 30.

이와 같이, 본 발명에 따른 칩 적층형 패키지는 펑션 칩인 하부칩의 각 모서리 영역에 다수개의 메모리 칩인 상부칩을 동일 수평선상을 이루도록 적층함으로써, 기존의 관통 실리콘 비아만을 이용하여 여러개의 칩을 수직으로만 적층하던 패키지에 비하여 그 두께를 현격하게 줄여서 경박단소화를 실현할 수 있고, 특히 다수개의 상부칩이 수평방향을 따라 넓게 분포되는 식으로 적층됨에 따라, 각 칩의 열방출 면적이 고르게 분산되며 증대되어 열방출 효과를 크게 얻어낼 수 있다.As described above, the chip stack package according to the present invention stacks a plurality of memory chips on the same horizontal line on each corner of a lower chip as a function chip to form a plurality of chips vertically using only through-silicon vias. Compared to the stacked package, the thickness of the chip can be significantly reduced, and thus, the thin and small can be realized. In particular, as the plurality of upper chips are stacked in a wide manner along the horizontal direction, the heat dissipation area of each chip is evenly distributed and increased. A large heat dissipation effect can be obtained.

도 1은 본 발명에 따른 재배선 및 TSV를 이용한 적층 칩 패키지 및 그 제조 방법을 설명하는 종단면도,1 is a longitudinal cross-sectional view illustrating a multilayer chip package using a redistribution and TSV and a method of manufacturing the same according to the present invention;

도 2는 본 발명에 따른 재배선 및 TSV를 이용한 적층 칩 패키지를 나타내는 횡단면도,2 is a cross-sectional view showing a stacked chip package using a redistribution and TSV according to the present invention,

도 3은 종래의 TSV 형성 과정 및 TSV를 통한 칩 적층 과정을 설명하는 단면도.3 is a cross-sectional view illustrating a conventional TSV forming process and chip stacking process through TSV.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 기판 12 : 하부칩10: substrate 12: lower chip

14 : 관통 실리콘 비아 16 : 전도성패턴14: through silicon via 16: conductive pattern

18 : 플립칩 20 : 하부 몰딩수지18: flip chip 20: lower molding resin

22 : 상부칩 23 : 전도성범프22: upper chip 23: conductive bump

24 : 상부 몰딩수지 30 : 재배선24: upper molding resin 30: redistribution

32 : 단배선 34 : 장배선32: single wiring 34: long wiring

36 : 본딩패드36: bonding pad

Claims (7)

기판(10)과;A substrate 10; 전체 면적에 걸쳐 다수의 관통 실리콘 비아(14)가 배열되어 있는 구조로서, 상기 기판(10)상에 탑재되는 하부칩(12)과;A structure in which a plurality of through silicon vias 14 are arranged over an entire area, the lower chip 12 mounted on the substrate 10; 상기 하부칩(12)의 관통 실리콘 비아(14)와 상기 기판(10)상의 전도성패턴(16)간을 통전 가능하게 연결하는 플립칩(18)과;A flip chip 18 for electrically connecting the through silicon via 14 of the lower chip 12 to the conductive pattern 16 on the substrate 10; 상기 하부칩(12)을 포함하여 기판(10)상에 몰딩되는 하부 몰딩수지(20)와;A lower molding resin 20 molded on the substrate 10 including the lower chip 12; 일측단부는 상기 하부칩(12)의 관통 실리콘 비아(14)와 연결되면서 하부 몰딩수지(20)의 표면상에 소정의 배열로 형성되는 재배선(30)과;One side end is connected to the through-silicon via 14 of the lower chip 12, the redistribution line 30 is formed in a predetermined arrangement on the surface of the lower molding resin (20); 상기 재배선(30)의 타측단부에 전도성범프(23)를 매개로 통전 가능하게 연결되면서 상기 하부 몰딩수지(20)의 표면상에 적층되는 다수의 상부칩(22)과;A plurality of upper chips 22 stacked on the surface of the lower molding resin 20 while being electrically connected to the other end of the redistribution line via conductive bumps 23; 상기 상부칩(22) 및 재배선(30)을 봉지하도록 하부 몰딩수지(20)의 전체 표면에 걸쳐 몰딩되는 상부 몰딩수지(24);An upper molding resin 24 molded over the entire surface of the lower molding resin 20 to encapsulate the upper chip 22 and the redistribution 30; 를 포함하여 구성된 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.Stacked chip package using a redistribution and TSV, characterized in that configured to include. 청구항 1에 있어서,The method according to claim 1, 상기 하부 몰딩수지(20)상에 총 4개의 상부칩(22)이 적층 부착되되, 각 상부 칩(22)의 모서리 영역이 하부칩(12)의 각 모서리 영역과 겹쳐지도록 적층되는 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.A total of four upper chips 22 are stacked and attached to the lower molding resin 20, and the corner regions of each upper chip 22 are stacked to overlap each corner region of the lower chip 12. Stacked chip package with redistribution and TSV. 청구항 1 또는 청구항 2에 있어서,The method according to claim 1 or 2, 상기 하부칩(12)은 펑션 칩이고, 상기 상부칩(22)들은 메모리 칩인 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.The lower chip (12) is a function chip, the upper chip (22) is a stacked chip package using a redistribution and TSV, characterized in that the memory chip. 청구항 1에 있어서,The method according to claim 1, 상기 하부 몰딩수지(20)는 재배선(30)의 형성 두께만큼 하부칩(12)의 높이보다 높게 몰딩되는 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.The lower molding resin 20 is laminated chip package using the redistribution and TSV, characterized in that the molding is formed higher than the height of the lower chip 12 by the thickness of the redistribution (30). 청구항 1에 있어서, 상기 재배선(30)은: The method of claim 1, wherein the redistribution 30 is: 하부칩(12)의 관통 실리콘 비아(14)와 연결되면서 하부칩(12)의 각 모서리 영역내까지 연장되는 단배선(32)과;A single interconnection 32 connected to the through silicon via 14 of the lower chip 12 and extending into each corner region of the lower chip 12; 하부칩(12)의 관통 실리콘 비아(14)와 연결되면서 하부칩(12)의 상면에서 벗어난 위치까지 연장되는 장배선(34)으로 구성되는 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.Stacked chip package using a redistribution and TSV, characterized in that consisting of a long wiring 34 is connected to the through-silicon via 14 of the lower chip 12 to extend to a position away from the upper surface of the lower chip 12. 청구항 1에 있어서, 상기 재배선(30)은 하부 몰딩수지(20)상에 레이저 가공을 이용하여 배선경로가 되는 경로홈을 형성하고, 경로홈내에 스퍼터링 또는 플레이팅에 의하여 형성되는 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.The method of claim 1, wherein the redistribution (30) is formed on the lower molding resin 20 by forming a path groove that becomes a wiring path using laser processing, and is formed by sputtering or plating in the path groove Stacked chip package with redistribution and TSV. 청구항 5에 있어서,The method according to claim 5, 상기 하부칩(12)의 모서리 영역과 겹쳐지는 상부칩(22)의 모서리영역내의 본딩패드(36)가 상기 단배선(32)의 타측단부와 전도성범프(38)를 매개로 연결되고, 상기 하부칩(12)의 상면에서 벗어난 영역에서의 상부칩(22)의 본딩패드(36)가 상기 장배선(34)의 타측단부와 전도성범프(38)를 매개로 연결되는 것을 특징으로 하는 재배선 및 TSV를 이용한 적층 칩 패키지.A bonding pad 36 in the corner region of the upper chip 22 overlapping the corner region of the lower chip 12 is connected to the other end of the short wiring 32 and the conductive bump 38 by the medium. Redistribution, characterized in that the bonding pad 36 of the upper chip 22 in the region deviated from the upper surface of the chip 12 is connected to the other end of the long wiring 34 and the conductive bump 38 through a medium; Stacked chip package using TSV.
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