KR101538539B1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
KR101538539B1
KR101538539B1 KR1020130071150A KR20130071150A KR101538539B1 KR 101538539 B1 KR101538539 B1 KR 101538539B1 KR 1020130071150 A KR1020130071150 A KR 1020130071150A KR 20130071150 A KR20130071150 A KR 20130071150A KR 101538539 B1 KR101538539 B1 KR 101538539B1
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South Korea
Prior art keywords
interposer
semiconductor die
layer
encapsulant
penetrating electrode
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KR1020130071150A
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Korean (ko)
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KR20140147588A (en
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김도형
한승철
박정수
이성민
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020130071150A priority Critical patent/KR101538539B1/en
Publication of KR20140147588A publication Critical patent/KR20140147588A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Disclosed herein is a semiconductor device capable of enhancing durability by encapsulating not only a semiconductor die but also a peripheral region of an interposer and using only interposers and semiconductor dies of good products to improve process efficiency and a manufacturing method thereof .
For example, the method may include providing a plurality of interposers, the plurality of interposers including a penetrating electrode, a first rewiring layer electrically connected to the penetrating electrode at an upper portion of the penetrating electrode, and a dielectric layer protecting the penetrating electrode and the first rewiring layer, Attaching a semiconductor die to a first rewiring layer exposed at an upper portion of the interposer; encapsulating the interposer and the semiconductor die with an encapsulant; removing the carrier and lowering the lower portion of the interposer Forming a second redistribution layer electrically connected to the penetrating electrode exposed at a lower portion of the interposer and forming a solder bump electrically connected to the second redistribution layer; A method of manufacturing a semiconductor device is disclosed.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device and a manufacturing method thereof.

Generally, after a semiconductor die is mounted on an interposer, the semiconductor device, which is stacked on another semiconductor die or substrate, is called a 2.5D package. In an interposer of a conventional 2.5D package, a plurality of through silicon vias (TSV) are formed so that an electrical signal can flow between the upper semiconductor die and the lower semiconductor die or substrate.

Korean Patent Registration No. 10-0349283 (published on Aug. 21, 2002)

The present invention provides a semiconductor device capable of enhancing durability by encapsulating not only a semiconductor die but also a peripheral region of an interposer and using only interposers and semiconductor dies of good products to improve process efficiency and a manufacturing method thereof .

A method of manufacturing a semiconductor device according to the present invention includes preparing a plurality of interposers including a penetrating electrode, a first rewiring layer electrically connected to the penetrating electrode at an upper portion of the penetrating electrode, and a dielectric layer protecting the penetrating electrode and the first rewiring layer Attaching a plurality of interposers to the carrier, connecting the semiconductor die to the first rewiring layer exposed at the top of the interposer, encapsulating the interposer and the semiconductor die with encapsulant, Forming a second re-wiring layer electrically connected to the penetrating electrode exposed at the lower portion of the interposer, and a step of forming a second re-wiring layer electrically connected to the second re-wiring layer And forming a solder bump.

Here, the dielectric layer may be a silicon oxide film, a silicon nitride film, or a polymer film.

And solder is formed on the first rewiring layer exposed at the top of the interposer, and the semiconductor die can be connected to the solder.

Also, underfill can be filled between the semiconductor die and the interposer after the semiconductor die attach step.

Further, the second rewiring layer may be formed in multiple layers.

Further, the second rewiring layer may be formed as a single layer.

Further, the second rewiring layer can be protected by a dielectric layer.

In addition, the encapsulant may be formed to surround the side surface of the interposer except the lower surface of the interposer and the entire semiconductor die.

In addition, the encapsulant may be ground so that the top surface of the semiconductor die is exposed after the solder bump forming step.

Also, a heat sink may be attached to the top surface of the encapsulant and the exposed semiconductor die.

A semiconductor device according to the present invention includes a penetrating electrode, an interposer including a first rewiring layer electrically connected to the penetrating electrode at an upper portion of the penetrating electrode, a dielectric layer protecting the first rewiring layer and the penetrating electrode, An encapsulant encapsulating the interposer and the semiconductor die, a second re-wiring layer electrically connected to the penetrating electrode exposed in the lower portion of the interposer, and a second re-wiring layer electrically connected to the first re- And a solder bump connected to the solder bump.

Here, the encapsulant may be formed to surround the entire side of the interposer and the entire semiconductor die except the lower surface of the interposer and the upper surface of the semiconductor die.

And a heat sink may be attached to the top surface of the encapsulant and the exposed semiconductor die.

Also, the encapsulant may be formed to surround the entire interposer and the semiconductor die except the lower surface of the interposer.

Further, the second rewiring layer may be formed in multiple layers.

Further, the second rewiring layer may be formed as a single layer.

The semiconductor device and the method of manufacturing the same according to the present invention can improve the durability by encapsulating not only the semiconductor die but also the peripheral region of the interposer, and the efficiency of the process can be improved by using only interposer and semiconductor die of good products.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
3 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
5 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
6 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
7 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.
8 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
9A to 9I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
10A to 10D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described.

1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 140, a re-wiring layer 150a A solder bump 160 and a heat sink 170. The solder bump 160 is formed of a solder bump 160,

The interposer 110 includes a through silicon electrode 111, a body 113 having the penetrating electrode 111, and a body 113 electrically connected to the penetrating electrode at an upper portion of the penetrating electrode 111. A first redistribution layer 112 and a dielectric layer 113a and 113b for protecting the penetrating electrode 111 and the first redistribution layer 112. [ The dielectric layers 113a and 113b include a first dielectric layer 113a for protecting the penetrating electrode 111 and a second dielectric layer 113b for protecting the first redistribution layer 112. [ In addition, the body 113 may be any one selected from the group consisting of silicon, glass, and the like, but the present invention is not limited thereto.

The penetrating electrode 111 is formed to penetrate the upper surface and the lower surface of the body 113. That is, the top and bottom surfaces of the penetrating electrode 111 are exposed by the body 113. The first rewiring layer 112 is formed on the exposed upper surface of the penetrating electrode 111 and is electrically connected to the penetrating electrode 111. The first redistribution layer 112 may have a multi-layer structure and is formed toward the upper portion of the interposer 110. The upper surface of the first redistribution layer 112 is exposed by the second dielectric layer 113b. In other words, the first rewiring layer 112 formed on the second dielectric layer 113b is exposed by the second dielectric layer 113b. In addition, the first rewiring layer 112 formed on the upper surface of the second dielectric layer 113b may be formed to have a relatively large width so that bumping can be easily performed later. In this way, a portion having a relatively large width can be defined as a pad or a land. In addition, a solder 114 may be formed on the upper surface of the first redistribution layer 112 for electrical connection with a semiconductor die to be attached later.

The material of the penetrating electrode 111 and the first redistribution layer 112 may be formed of any one selected from ordinary copper, aluminum, and the like. The dielectric layers 113a and 113b may be formed of any one selected from the group consisting of a silicon oxide film, a silicon nitride film, a polymer film, and the like. However, the present invention is not limited to these materials.

The semiconductor die 120 may be a conventional memory, a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), and the like, but the present invention is not limited thereto. The semiconductor die 120 includes a connection terminal 121 to be electrically connected to the interposer 110. The connection terminal 121 includes a kappa pillar 121a and a solder cap 121b formed at an end of the kappa pillar 121a. Of course, the connection terminal 121 may include a common solder bump. The solder cap 121b of the connection terminal 121 is connected to the solder 114 formed on the upper surface of the first redistribution layer 112. Thus, the semiconductor die 120 is electrically connected to the first redistribution layer 112 facing the top of the interposer 110.

The underfill 130 is filled between the interposer 110 and the semiconductor die 120. More specifically, the underfill 130 surrounds the lower side of the semiconductor die 120 as well as between the interposer 110 and the semiconductor die 120. This underfill 130 not only improves the physical and mechanical bonding force between the interposer 110 and the semiconductor die 120 but also improves the mechanical and mechanical coupling between the interposer 110 and the semiconductor die 120, Thereby preventing the separator 110 and the semiconductor die 120 from being separated.

The encapsulant 140 encapsulates the interposer 110 and the semiconductor die 120 such that the semiconductor die 120 is protected from the external environment. More specifically, the encapsulant 140 is formed to cover the side surface and the upper surface of the interposer 110 except for the lower surface of the interposer 110 and the upper surface of the semiconductor die 120, . That is, the encapsulant 140 surrounds all areas between the lower surface of the interposer 110 and the upper surface 120 of the semiconductor die, and the lower surface of the interposer 110 and the upper surface of the semiconductor die 120 Lt; / RTI > Here, since the semiconductor die 120 is entirely encapsulated, a more reliable semiconductor device can be realized. In addition, since the encapsulant 140 is formed to cover the peripheral region including the side surface of the interposer 110, the encapsulant 140 is not easily deformed by force or impact applied from the outside, and is durable.

The second rewiring layer 150a is electrically connected to the penetrating electrode 111 exposed from the lower portion of the interposer 110. [ That is, the second redistribution layer 150a is formed on the lower surface of the exposed through-hole electrode 111 and is electrically connected to each other. The second redistribution layer 150a may be formed in a multi-layered structure and is directed toward a lower portion of the semiconductor device 100. The second rewiring layer 150a is protected by a third dielectric layer 150b and the second rewiring layer 150a formed on the inner side of the third dielectric layer 150b is protected by the third dielectric layer 150b Exposed. That is, the second rewiring layer 150a exposed from the upper surface of the third dielectric layer 150b is connected to the penetrating electrode 111, and the second rewiring layer 150a exposed from the lower surface of the third dielectric layer 150b ) Are connected to the solder bumps to be described later. In addition, the third dielectric layer 150b may be formed to cover the lower surface of the interposer 110 and the entire lower surface of the encapsulant 140. Meanwhile, an insulating layer 151 may be additionally formed on the lower surface of the third dielectric layer 150b. The insulating layer 151 is formed to cover a bottom surface of the third dielectric layer 150b and a bottom surface of the second redistribution layer 150a. The insulating layer 151 is formed to cover only a part of the lower surface of the second redistribution layer 150a so that the second redistribution layer 150a is formed to cover the second redistribution layer 150a, Lt; / RTI > The second rewiring layer 150a and the third dielectric layer 150b are insulated from the outside by the insulating layer 151. [

The material of the second redistribution layer 150a may be formed of any one selected from ordinary copper, aluminum, and the like. The third dielectric layer 150c may be formed of any one selected from the group consisting of a silicon oxide film, a silicon nitride film, a polymer film, and the like. However, the present invention is not limited to these materials.

The solder bumps 160 are connected to the second rewiring layer 150a exposed by the insulating layer 151. [ At this time, an under bump metal may be formed on the second redistribution layer 150a exposed by the insulating layer 151, and a solder bump 160 may be connected to the under bump metal although not shown in the figure.

The heat sink 170 is attached to the upper surface of the semiconductor die 120 and the upper surface of the encapsulant 140. That is, the heat sink 170 is formed to cover the upper portion of the semiconductor device. By attaching the heat sink 170 to the upper surface of the semiconductor device 100, the heat radiation performance of the semiconductor die 120 can be improved.

Thus, the semiconductor device 100 according to an embodiment of the present invention is completed in the form of, for example, a flip chip. Thus, although not shown, such a flip chip type semiconductor device 100 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 100 according to the present invention may be directly mounted on a mother board, a main board, or the like.

As described above, the semiconductor device 100 according to an embodiment of the present invention is encapsulated not only in the semiconductor die 120 but also in the peripheral region including the side surface of the interposer 110, It is possible to improve the reliability of the device.

In addition, since the heat sink 170 is attached to the upper surface of the semiconductor device 100 according to the embodiment of the present invention, the heat radiation performance of the device can be improved.

2 is a cross-sectional view illustrating a semiconductor device 200 according to another embodiment of the present invention.

Referring to FIG. 2, a semiconductor device 200 according to another embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 140, a re-wiring layer 250a A solder bump 160 and a heat sink 170. The solder bump 160 is formed of a solder bump 160, Portions having the same configurations and operations as those of the above-described embodiment are denoted by the same names and reference numerals, and differences from the foregoing embodiments will be mainly described below.

In the above embodiment, a second rewiring layer having a multilayer structure is formed on the lower surface of the penetrating electrode facing the lower portion of the semiconductor device. However, in the semiconductor device 200 according to another embodiment of the present invention, the second redistribution layer 250a may have a single-layer structure. Of course, the second redistribution layer 250a is protected by the third dielectric layer 250b. Since the second redistribution layer 250a is formed in a single layer structure, the manufacturing process of the semiconductor device 200 can be simplified, and a cost reduction effect can be obtained.

In this manner, the semiconductor device 200 according to another embodiment of the present invention is completed, for example, in the form of a flip chip. Thus, although not shown, such flip chip type semiconductor device 200 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 200 according to the present invention may be directly mounted on a mother board, a main board, or the like.

The semiconductor device 200 according to another embodiment of the present invention is encapsulated not only in the semiconductor die 120 but also in the peripheral region including the side surface of the interposer 110 so that the durability against external force or impact It is possible to improve the reliability of the device.

In addition, since the heat sink 170 is attached to the upper surface of the semiconductor device 200 according to another embodiment of the present invention, the heat radiation performance of the device can be improved.

3 is a cross-sectional view illustrating a semiconductor device 300 according to another embodiment of the present invention.

3, a semiconductor device 300 according to another embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 340, a re-wiring layer 150a, (Hereinafter referred to as a second re-wiring layer in order to distinguish from the re-wiring layer inside the interposer) and the solder bump 160. Parts having the same configurations and operations as those of the above-described embodiment are denoted by the same names and similar reference numerals, and differences from the preceding embodiments will be mainly described below.

In the semiconductor device 300 according to another embodiment of the present invention, a second redistribution layer 150a having a multilayer structure is formed on the lower surface of the penetrating electrode 111 facing the lower portion of the device. Also, the upper surface of the semiconductor device 300 is formed to be covered with the encapsulant 340. More specifically, the encapsulant 340 surrounds the sides and top surfaces of the interposer 110, the semiconductor die 120, and the entire surface of the underfill 130. It is possible to protect the semiconductor die 120 more reliably from the external environment by covering the whole of the semiconductor die 120 including the upper surface of the semiconductor die 120. [

In this manner, the semiconductor device 300 according to another embodiment of the present invention is completed in the form of, for example, a flip chip. Thus, although not shown, such a flip chip type semiconductor device 300 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 300 according to the present invention may be directly mounted on a mother board, a main board, or the like.

The semiconductor device 300 according to another embodiment of the present invention includes the upper surface of the semiconductor die 120 and is encapsulated to a peripheral region including a side surface of the interposer 110 to be subjected to an external force or impact It is possible to improve the reliability of the device.

4 is a cross-sectional view illustrating a semiconductor device 400 according to another embodiment of the present invention.

4, a semiconductor device 400 according to another embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 440, a rewiring layer 250a, (Hereinafter referred to as a second re-wiring layer in order to distinguish from the re-wiring layer inside the interposer) and the solder bump 160. Parts having the same configurations and operations as those of the above-described embodiment are denoted by the same names and similar reference numerals, and differences from the preceding embodiments will be mainly described below.

In the semiconductor device 400 according to another embodiment of the present invention, a second redistribution layer 250a having a single-layer structure is formed on the lower surface of the penetrating electrode 111 facing the lower portion of the device. Of course, the second redistribution layer 250a is protected by the third dielectric layer 250b. Since the second redistribution layer 250a is formed in a single layer structure, the manufacturing process of the semiconductor device 400 can be simplified, and the cost reduction effect can also be obtained. Also, the upper surface of the semiconductor device 400 is covered with the encapsulant 440. More specifically, the encapsulant 440 encapsulates the side surfaces and the upper surface of the interposer 110, the entire surface of the semiconductor die 120 and the underfill 430. It is possible to protect the semiconductor die 120 more reliably from the external environment by covering the whole of the semiconductor die 120 including the upper surface of the semiconductor die 120 by the encapsulant 440.

In this manner, the semiconductor device 400 according to another embodiment of the present invention is completed, for example, in the form of a flip chip. Thus, although not shown, such a flip-chip type semiconductor device 400 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 400 according to the present invention may be directly mounted on a mother board, a main board, or the like.

The semiconductor device 400 according to another embodiment of the present invention includes the upper surface of the semiconductor die 120 and is encapsulated to a peripheral region including a side surface of the interposer 110 to be subjected to external force or impact It is possible to improve the reliability of the device.

5 is a cross-sectional view illustrating a semiconductor device 500 according to another embodiment of the present invention.

5, a semiconductor device 500 according to another embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 540, a re-wiring layer 150a, (Hereinafter referred to as a second re-wiring layer in order to distinguish from the re-wiring layer inside the interposer) and the solder bump 160. Parts having the same configurations and operations as those of the above-described embodiment are denoted by the same names and similar reference numerals, and differences from the preceding embodiments will be mainly described below.

In the semiconductor device 500 according to another embodiment of the present invention, a second redistribution layer 150a having a multilayer structure is formed on the lower surface of the penetrating electrode 111 facing the lower portion of the device. The encapsulant 540 is formed to surround the interposer 110 and the semiconductor die 120 such that the upper surface of the semiconductor die 120 is exposed. More specifically, the encapsulant 540 encapsulates the sides and top surfaces of the interposer 110, the sides of the semiconductor die 120, and the entire surface of the underfill 130. The upper surface of the semiconductor die 120 is exposed to the outside by the encapsulant 540 so that the heat generated in the semiconductor die 120 can be more easily discharged to the outside.

In this manner, the semiconductor device 500 according to another embodiment of the present invention is completed in the form of, for example, a flip chip. Thus, although not shown, such a flip-chip type semiconductor device 500 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 500 according to the present invention may be directly mounted on a mother board, a main board, or the like.

The semiconductor device 500 according to another embodiment of the present invention is encapsulated not only in the semiconductor die 120 but also in the peripheral region including the side surface of the interposer 110 to provide durability against external force or impact It is possible to improve the reliability of the device.

6 is a cross-sectional view illustrating a semiconductor device 600 according to another embodiment of the present invention.

6, a semiconductor device 600 according to another embodiment of the present invention includes an interposer 110, a semiconductor die 120, an underfill 130, an encapsulant 640, a rewiring layer 250a, (Hereinafter referred to as a second re-wiring layer in order to distinguish from the re-wiring layer inside the interposer) and the solder bump 160. Parts having the same configurations and operations as those of the above-described embodiment are denoted by the same names and similar reference numerals, and differences from the preceding embodiments will be mainly described below.

In the semiconductor device 600 according to another embodiment of the present invention, the second rewiring layer 250a having a single-layer structure is formed on the lower surface of the penetrating electrode 111 facing the lower portion of the device. Of course, the second redistribution layer 250a is protected by the third dielectric layer 250b. Since the second redistribution layer 250a is formed in a single layer structure, the manufacturing process of the semiconductor device 600 can be simplified, and the cost reduction effect can also be obtained. The encapsulant 640 is formed to surround the interposer 110 and the semiconductor die 120 such that the upper surface of the semiconductor die 120 is exposed. More specifically, the encapsulant 640 encapsulates the side surface and top surface of the interposer 110, the side surface of the semiconductor die 120, and the entire surface of the underfill 130. The upper surface of the semiconductor die 120 is exposed to the outside by the encapsulant 640 so that the heat generated from the semiconductor die 120 can be more easily discharged to the outside.

In this manner, the semiconductor device 600 according to another embodiment of the present invention is completed in the form of, for example, a flip chip. Thus, although not shown, such a flip-chip type semiconductor device 600 can be mounted on a conventional semiconductor device or on a circuit board for a semiconductor package. Of course, the semiconductor device 600 according to the present invention may be directly mounted on a mother board, a main board, or the like.

The semiconductor device 600 according to another embodiment of the present invention is encapsulated not only in the semiconductor die 120 but also in the peripheral region including the side surface of the interposer 110 so that the durability against external force or impact It is possible to improve the reliability of the device.

7 is a cross-sectional view showing a semiconductor device 700 according to another embodiment of the present invention.

7, a semiconductor device 700 according to another embodiment of the present invention includes a semiconductor device 100 (herein, defined as a flip chip device), a circuit board 710, an underfill 720, A cover 730, a thermally conductive adhesive 740, and a solder ball 750.

The flip chip device 100 has the bumps 160 formed on the lower surface thereof as described above, and these bumps 160 are mounted on the circuit board 710. In this case, it is also possible that the flip chip device 100 shown in FIG. 1, as well as the devices shown in FIGS. 2 to 6, are mounted.

The circuit board 710 includes a circuit pattern 711 and an insulating layer 712. In addition, the passive element 760 may be mounted on the circuit board 710. The bumps 160 of the flip chip device 100 are electrically connected to the circuit pattern 711 of the circuit board 710 as described above.

The underfill 720 is filled between the flip chip device 100 and the circuit board 710. That is, the underfill 720 surrounds the sides of the interposer 110 and the encapsulant 140 of the flip chip device 100 while wrapping the bumps 160. Therefore, the flip chip device 100 and the circuit board 710 are not separated from each other by the stress due to the difference in thermal expansion coefficient between the flip chip device 100 and the circuit board 710. [

The cover 730 is attached to the circuit board 710 and substantially surrounds the flip chip device 100. Thus, the flip chip device 100 is protected from the external environment by the cover 730. The cover 730 may be formed of a metal, a ceramic, or an equivalent thereof to improve the heat radiation performance, but the present invention is not limited thereto.

The thermally conductive adhesive 740 is interposed between the flip chip device 100 and the cover 730, the cover 730, and the circuit board 710. This thermally conductive adhesive 740 allows heat generated from the flip chip device 100 to be quickly transferred to the cover 730. Of course, the thermally conductive adhesive 740 also serves to fix the cover 730 to the flip chip device 100 and the circuit board 710.

The solder ball 750 is connected to the lower surface of the circuit board 710. That is, the solder ball 750 is electrically connected to the circuit pattern 711 of the circuit board 710. The solder ball 750 serves to mount the semiconductor device 700 according to the present invention on a motherboard or a main board of an electronic device such as a computer, a smart phone, or the like.

In this manner, the semiconductor device 700 according to another embodiment of the present invention is encapsulated not only in the semiconductor die 120 but also in the peripheral region including the side surface of the interposer 110, (100), a flip-chip device, which is highly durable to the semiconductor device (100).

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.

8 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 8, a method of manufacturing a semiconductor device according to the present invention includes preparing an interposer S10, attaching a carrier S20, connecting a semiconductor die S30, encapsulating S40, A solder bump forming step S70, a second grinding step S80, a solder bump forming step S70, a second solder bump forming step S70, a second solder bump forming step S70, , And a heat sink attaching step (S90).

9A to 9I are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.

Referring to FIGS. 8 and 9A, a through silicon 111, a body 113 having the penetrating electrode 111, a penetrating electrode 111 and a through hole 111 are formed on the penetrating electrode 111, An interposer 110 including a first re-distribution layer (RDL) 112 electrically connected and a dielectric layer 113a and 113b protecting the penetrating electrode 111 and the first re-distribution layer 112 is prepared The interposer preparation step S10 is performed. The dielectric layers 113a and 113b include a first dielectric layer 113a for protecting the penetrating electrode 111 and a second dielectric layer 113b for protecting the first redistribution layer 112. [ In addition, the body 113 may be any one selected from the group consisting of silicon, glass, and the like, but the present invention is not limited thereto.

The penetrating electrode 111 is formed by etching the body 113 from the upper surface to the lower side by a predetermined depth and then filling the etched region with any one selected from ordinary copper, aluminum, and the like, It does not limit the material. According to this process, the upper surface of the penetrating electrode 111 is exposed by the body 113.

The first rewiring layer 112 is formed on the upper surface of the penetrating electrode 111 and is electrically connected to each other. The first redistribution layer 112 may have a multi-layer structure and is formed toward the upper portion of the interposer 110. Of course, the first rewiring layer 112 is protected by the second dielectric layer 113b and the first rewiring layer 112 formed on the second dielectric layer 113b is exposed by the second dielectric layer 113b. do. In addition, the first rewiring layer 112 formed on the upper surface of the second dielectric layer 112 may be formed to have a relatively large width so that bumping can be easily performed later. In this way, a portion having a relatively large width can be defined as a pad or a land. In addition, a solder 114 may be formed on the upper surface of the first redistribution layer 112 for electrical connection with a semiconductor die to be attached later.

The material of the first redistribution layer 112 may be the same as the material of the penetrating electrode 111, and may be formed of any one selected from ordinary copper, aluminum, and the like. The dielectric layers 113a and 113b may be formed of any one selected from the group consisting of a silicon oxide film, a silicon nitride film, a polymer film, and the like. However, the present invention is not limited to these materials.

Meanwhile, the interposer 110 is formed by cutting out interposer wafers in which a plurality of interposers are formed integrally with individual interposers, and then selecting only good products. The method of manufacturing a semiconductor device according to the present invention can make the manufacturing process of the semiconductor device more efficient and improve the yield of the manufacturing process by using only the interposer of the good product.

8 and 9B, a carrier attaching step (S20) for attaching the interposer 110 to the carrier 115 is performed. At this time, although only one interposer 110 is shown in the drawing, a plurality of good quality interposers are arranged and attached on the carrier 115 in practice. The carrier 115 can firmly fix the interposer 110, thereby facilitating a process to be performed later.

Referring to FIGS. 8 and 9C, a semiconductor die connection step S30 is performed to connect the semiconductor die 120 to the first rewiring layer 112 exposed at the top of the interposer 110. FIG. Here, the semiconductor die 120 may be a general memory, a graphics processing unit (GPU), a central processing unit (CPU), and the like, but is not limited thereto.

The semiconductor die 120 includes connection terminals 121 for electrical connection to the interposer 110. The connection terminal 121 includes a kappa pillar 121a and a solder cap 121b formed at an end of the kappa pillar 121a. Of course, the connection terminal 121 may include a common solder bump. The solder cap 121b of the connection terminal 121 is connected to the solder 114 formed on the upper surface of the first redistribution layer 112. Thus, the semiconductor die 120 is electrically connected to the first redistribution layer 112 facing the top of the interposer 110.

After the connection of the semiconductor die 120 to the interposer 110, the underfill 130 is filled between the interposer 110 and the semiconductor die 120. More specifically, the underfill 130 surrounds the lower side of the semiconductor die 120 as well as between the interposer 110 and the semiconductor die 120. The underfill 130 not only improves the physical and mechanical bonding force between the interposer 110 and the semiconductor die 120 but also improves the mechanical and mechanical coupling strength between the interposer 110 and the semiconductor die 120, So that the interposer 110 and the semiconductor die 120 are not separated from each other.

Meanwhile, the semiconductor die connection step S30 may be performed by selecting only the good semiconductor die 120 in the same manner as the semiconductor device preparation step S10. By using only the interposer and the semiconductor die of the good article, the manufacturing method of the semiconductor device according to the present invention can make the manufacturing process of the semiconductor device more efficiently and the yield of the manufacturing process can be improved.

Referring to FIGS. 8 and 9D, an encapsulation step S40 is performed to encapsulate the interposer 110 and the semiconductor die 120 into the encapsulant 140. The encapsulant 140 is formed to cover the entire interposer 110 and the semiconductor die 120 except the lower surface of the interposer 110 attached to the carrier 115. More specifically, the encapsulant 140 surrounds the sides and top surfaces of the interposer 110, the semiconductor die 120, and the entire surface of the underfill 130. It is possible to protect the interposer 110 and the semiconductor die 120 from the external environment by the encapsulant 140.

8 and 9E, a first grinding step (S50) is performed in which the carrier 115 is removed and the lower part of the interposer 110 is ground so that the penetrating electrode 111 is exposed. Here, after the carrier 115 is first removed, the lower portion of the interposer 110 may be ground. The interposer 110 is ground and removed until the penetrating electrode 111 facing the lower portion of the interposer 110 is exposed at the lower surface of the interposer 110. Since the encapsulant 140 firmly fixes the side surface and the upper surface of the interposer 110 except the lower surface of the interposer 110 and the entire semiconductor die 120, ) Is not grinding, a separate WSS (Wafer Support System) is not required. That is, it is possible to manufacture a more simplified semiconductor device.

Referring to FIGS. 8 and 9F, a second rewiring layer forming step S60 for forming a second rewiring layer 150a electrically connected to the penetrating electrode 111 exposed at a lower portion of the interposer 110 . The second rewiring layer 150a is formed on the lower surface of the exposed through-hole electrode 111 and is electrically connected to each other. The second redistribution layer 150a may be formed in a multi-layered structure and is directed downwardly of the interposer 110. [ The second rewiring layer 150a is protected by the third dielectric layer 150b and the second rewiring layer 150a formed on the upper and lower surfaces of the third dielectric layer 150b is protected by the third dielectric layer 150b. . In addition, an insulating layer 151 is additionally formed on the lower surface of the third dielectric layer 150b. The insulating layer 151 is formed to cover a bottom surface of the third dielectric layer 150b and a bottom surface of the second redistribution layer 150a. The insulating layer 151 is formed to cover only a part of the lower surface of the second redistribution layer 150a so that the second redistribution layer 150a is formed to cover the second redistribution layer 150a, Lt; / RTI > The second rewiring layer 150a and the third dielectric layer 150b are insulated from the outside by the insulating layer 151. [

The material of the second redistribution layer 150a may be formed of any one selected from ordinary copper, aluminum, and the like. The third dielectric layer 150c may be formed of any one selected from the group consisting of a silicon oxide film, a silicon nitride film, a polymer film, and the like. However, the present invention is not limited to these materials.

Referring to FIGS. 8 and 9G, a solder bump forming step S70 is performed to form a solder bump 160 electrically connected to the second redistribution layer 150a. The solder bumps 160 are connected to the second rewiring layer 150a exposed by the insulating layer 151. [ At this time, an under bump metal may be formed on the second redistribution layer 150a exposed by the insulating layer 151, and a solder bump 160 may be connected to the under bump metal although not shown in the figure.

On the other hand, after the solder bump forming step S70 is performed according to the case, the manufacturing process of the semiconductor device may be completed. In this case, it is possible to protect the semiconductor die 120 more reliably from the external environment by covering the whole of the semiconductor die 120 including the upper surface of the semiconductor die 120 . In addition, a more simplified manufacturing process can save time and cost.

Referring to FIGS. 8 and 9H, a second grinding step S80 is performed to grind the encapsulant 140 such that the upper surface of the semiconductor die 120 is exposed. That is, the encapsulant 140 on the semiconductor die 120 is ground and removed until the top surface of the semiconductor die 120 is exposed.

On the other hand, after the second grinding step S80 is performed as occasion demands, the manufacturing process of the semiconductor device may be completed. In this case, the upper surface of the semiconductor die 120 is exposed to the outside by the encapsulant 140, so that the heat generated from the semiconductor die 120 can be more easily discharged to the outside. In addition, a more simplified manufacturing process can save time and cost.

8 and 9I, a heat sink attaching step S90 is performed in which a heat sink 170 is attached to the upper surface of the encapsulant 140 and the exposed semiconductor die 120. FIG. The heat sink 170 may be attached to the upper surface of the semiconductor device to improve the heat radiation performance of the semiconductor die 120.

In addition, although not shown in the drawing, singulation of the encapsulant 140 after the solder bump forming step S70, after the second grinding step S80, or after the heat sink attaching step S90, So that a semiconductor device is provided.

As described above, the method of manufacturing a semiconductor device according to an embodiment of the present invention includes encapsulating not only the semiconductor die 120 but also the peripheral region including the side surface of the interposer 110, A semiconductor device having a high durability and capable of improving the reliability of the device is provided.

Further, by using only the good interposer 110 and the semiconductor die 120, the manufacturing process of the semiconductor device can be more efficiently performed, and the yield of the manufacturing process can be improved.

In addition, a method of manufacturing a semiconductor device according to an embodiment of the present invention provides a semiconductor device capable of improving heat radiation performance by attaching a heat sink 170 to an upper surface thereof.

9A to 9D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention. Hereinafter, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to FIG. The method of manufacturing a semiconductor device according to another embodiment of the present invention may be performed in the same manner as in the previous embodiment up to the first grinding step (S50). Portions having the same configuration and operation as those of the above-described embodiment are denoted by the same reference numerals, and differences from the foregoing embodiment will be mainly described below.

7 and 9A, a second rewiring layer forming step S60 for forming a second rewiring layer 250a electrically connected to the penetrating electrode 111 exposed at the lower portion of the interposer 110 . The second redistribution layer 250a is formed on the lower surface of the exposed through-hole electrode 111 and is electrically connected to each other. The second redistribution layer 250a may have a single layer structure and is exposed by the third dielectric layer 250b. Since the second redistribution layer 250a is formed in a single layer structure, the manufacturing process of the semiconductor device 200 can be simplified, and a cost reduction effect can be obtained. In addition, an insulating layer 251 is additionally formed on the lower surface of the third dielectric layer 250b. The insulating layer 251 is formed to cover a bottom surface of the third dielectric layer 250b and a bottom surface of the second redistribution layer 250a. The insulating layer 251 is formed to cover only a part of the lower surface of the second redistribution layer 250a and is then formed in a predetermined region of the lower surface of the second redistribution layer 250a for attachment of the solder bumps to the second redistribution layer 250a. Lt; / RTI > The second rewiring layer 250a and the third dielectric layer 250b are insulated from the outside by the insulating layer 251. [

The material of the second redistribution layer 250a may be formed of any one selected from ordinary copper, aluminum, and the like. The third dielectric layer 250c may be formed of any one selected from the group consisting of a silicon oxide layer, a silicon nitride layer, a polymer layer, and the like. However, the present invention is not limited to these materials.

Referring to FIGS. 7 and 9B, a solder bump forming step S70 is performed to form a solder bump 260 electrically connected to the second redistribution layer 250a. The solder bumps 260 are connected to the second redistribution layer 250a exposed by the insulating layer 251. [ At this time, an under bump metal may be formed on the second rewiring layer 250a exposed by the insulating layer 251, and a solder bump 260 may be connected to the under bump metal although not shown in the drawing.

On the other hand, after the solder bump forming step S70 is performed according to the case, the manufacturing process of the semiconductor device may be completed. In this case, it is possible to protect the semiconductor die 120 more reliably from the external environment by covering the whole of the semiconductor die 120 including the upper surface of the semiconductor die 120 . In addition, a more simplified manufacturing process can save time and cost.

Referring to FIGS. 7 and 9C, a second grinding step S80 is performed to grind the encapsulant 140 such that the upper surface of the semiconductor die 120 is exposed. That is, the encapsulant 140 on the semiconductor die 120 is ground and removed until the top surface of the semiconductor die 120 is exposed.

On the other hand, after the second grinding step S80 is performed as occasion demands, the manufacturing process of the semiconductor device may be completed. In this case, the upper surface of the semiconductor die 120 is exposed to the outside by the encapsulant 140, so that the heat generated from the semiconductor die 120 can be more easily discharged to the outside. In addition, a more simplified manufacturing process can save time and cost.

7 and 8H, a heat sink attaching step S90 is performed in which a heat sink 170 is attached to the upper surface of the encapsulant 140 and the exposed semiconductor die 120. FIG. The heat sink 170 may be attached to the upper surface of the semiconductor device to improve the heat radiation performance of the semiconductor die 120.

In addition, although not shown in the drawing, singulation of the encapsulant 140 after the solder bump forming step S70, after the second grinding step S80, or after the heat sink attaching step S90, So that a semiconductor device is provided.

As described above, the method of manufacturing a semiconductor device according to an embodiment of the present invention encapsulates not only the semiconductor die 120 but also the peripheral region of the interposer 110, so that the durability against external force or impact is high. And provides a semiconductor device capable of improving the reliability of the device.

Further, by using only the good interposer 110 and the semiconductor die 120, the manufacturing process of the semiconductor device can be more efficiently performed, and the yield of the manufacturing process can be improved.

In addition, a method of manufacturing a semiconductor device according to an embodiment of the present invention provides a semiconductor device capable of improving heat radiation performance by attaching a heat sink 170 to an upper surface thereof.

It is to be understood that the present invention is not limited to the above-described embodiment, but may be embodied in various forms without departing from the spirit or scope of the invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100, 200, 300, 400, 500, 600; Semiconductor device
110; Interposer 111; Penetrating electrode
112; First rewiring layers 113a and 113b; The first and second dielectric layers
120; A semiconductor die 130; Underfill
140; Encapsulation 150a; The second re-
150b; A third dielectric layer 160; Solder bump
170; Heat Sink

Claims (16)

Preparing a plurality of interposers including a penetrating electrode, a first rewiring layer electrically connected to the penetrating electrode at an upper portion of the penetrating electrode, and a dielectric layer protecting the penetrating electrode and the first rewiring layer;
Attaching a carrier to a lower portion of the plurality of interposers;
Connecting a semiconductor die to a first rewiring layer exposed at an upper portion of the interposer;
Encapsulating an upper portion of the carrier encapsulant to encapsulate the entire interposer and semiconductor die;
A grinding step of removing the carrier and simultaneously grinding a lower portion of the encapsulant and a lower portion of the interposer to expose the penetrating electrode;
Forming a second rewiring layer electrically connected to the penetrating electrode exposed at the lower portion of the interposer and another dielectric layer covering the lower portion of the encapsulant and the lower portion of the interposer while protecting the second rewiring layer; And
Forming a solder bump electrically connected to the second rewiring layer,
Wherein the lower portion of the encapsulant, the lower portion of the interposer, and the penetrating electrode exposed from the lower portion of the interposer are all located on the same plane. The method according to claim 1,
Wherein the dielectric layer is a silicon oxide film, a silicon nitride film, or a polymer film. The method according to claim 1,
Wherein a solder is formed on a first rewiring layer exposed at an upper portion of the interposer, and the semiconductor die is connected to the solder. The method according to claim 1,
Wherein the underfill is filled between the semiconductor die and the interposer after the semiconductor die attach step. The method according to claim 1,
Wherein the second rewiring layer is formed in a multilayered structure. The method according to claim 1,
Wherein the second redistribution layer is formed as a single layer. delete delete The method according to claim 1,
Wherein the encapsulant is ground so that an upper surface of the semiconductor die is exposed after the solder bump forming step. 10. The method of claim 9,
Wherein a heat sink is attached to an upper surface of the encapsulant and the exposed semiconductor die. An interposer including a penetrating electrode, a first rewiring layer electrically connected to the penetrating electrode at an upper portion of the penetrating electrode, and a dielectric layer protecting the penetrating electrode and the first rewiring layer;
A semiconductor die connected to a first rewiring layer exposed at an upper portion of the interposer;
An encapsulant encapsulating the interposer and the semiconductor die;
A second rewiring layer electrically connected to a penetrating electrode exposed at a lower portion of the interposer; And
And a solder bump electrically connected to the second rewiring layer,
The encapsulant exposes the lower surface of the interposer and is formed to surround the interposer and the semiconductor die,
The bottom of the encapsulant, the bottom of the interposer, and the penetrating electrode exposed at the bottom of the interposer are all coplanar,
Further comprising a dielectric layer covering the bottom of the encapsulant and the bottom of the interposer to protect the second rewiring layer. 12. The method of claim 11,
Wherein the encapsulant is formed to expose only the bottom surface of the interposer and the top surface of the semiconductor die and surround the interposer and the semiconductor die. 13. The method of claim 12,
And a heat sink is attached to the upper surface of the encapsulant and the exposed semiconductor die. 12. The method of claim 11,
Wherein the encapsulant exposes only the lower surface of the interposer and surrounds the interposer and the semiconductor die. 12. The method of claim 11,
Wherein the second redistribution layer is formed in a multilayer structure. 12. The method of claim 11,
Wherein the second redistribution layer is formed as a single layer.
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