KR101530964B1 - Microstrip line combined by inductive and capacitive perturbations and wireless circuit apparatus using the same - Google Patents

Abstract

Disclosed are a microstrip line combined by inductive and capacitive perturbations and a wireless circuit apparatus using the same. A microstrip line includes a first dielectric layer; a transmission line formed on one side of the first dielectric layer; a second dielectric layer and a ground conductor layer which are successively formed on the back of the first dielectric layer. It includes a defect ground structure (DGS) formed by a window on the ground conductor layer, and a substrate integrated artificial dielectric (SIAD) structure formed by plated via holes which penetrate a second dielectric layer. Thereby, a new structure where the DGS and the SIAD are combined with an optimal shape is suggested. A circuit can be minimized by maximally reducing the length of a line. At the same time, electrical performance can be maintained by a similar line width to a standard type.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microstrip line coupled to an inductive and capacitive putter, and a wireless circuit device using the microstrip line.

The present invention relates to a microstrip line and a wireless circuit device using the microstrip line. More particularly, the present invention relates to a microstrip line capable of minimizing a line length and miniaturizing a circuit, and simultaneously maintaining an electrical performance with a line width similar to a standard line. To a wireless circuit device.

The microstrip line is a transmission line structure widely used in the microwave field, and its type includes a standard microstrip line, a defected ground structure (hereinafter referred to as DGS) in which a window is inserted into the ground plane of a standard microstrip line ), And a substrate integrated organic dielectric (hereinafter referred to as SIAD) in which a plurality of via holes are inserted into a ground plane of a standard microstrip line. SIAD is also called an arbitrary dielectric structure (ADS).

1 is a view showing a printed circuit board in a general raw board state.

Referring to FIG. 1, upper and lower conductor layers 30 and 50 having a thickness T are applied to both surfaces of a dielectric layer 10 having a dielectric constant ∈ _r and a thickness H. A standard microstrip line is fabricated from a planar printed circuit board as in Fig.

2A is a top perspective view of a conventional standard microstrip line, and FIG. 2B is a bottom perspective view of FIG. 2A.

2A and 2B, the remaining portion excluding the transmission line 40 of the line width W1 having a specific characteristic impedance Zc in the upper surface conductor layer 30 of FIG. 1 as the pattern surface is removed do. The broadly applied lower surface conductor layer 50 is the ground plane.

The characteristic impedance Zc and the physical length are determined by the thickness H of the dielectric layer 10 and the relative dielectric constant? _R and the line width W1 of the transmission line 40.

FIG. 3A is a top perspective view of a conventional DGS microstrip line, and FIG. 3B is a bottom perspective view of FIG. 3A. 3C is a partial perspective view of the ground plane of FIG. 3A.

DGS can be formed by etching a certain type of window 60 on the bottom surface of the conductor layer 50, which is the ground plane of the microstrip line.

FIGS. 4A and 4B illustrate a technical idea that the length of the microstrip line can be reduced by inserting the DGS, and the size of the wireless circuit can be reduced when the DGS is applied.

4A illustrates a standard microstrip line having an electrical length of? 1 and a physical length of L1 at a certain frequency.

) 전기적 길이는 거의 같게 유지되며(

), 이러한 원리에 의해 결과적으로 회로의 크기를 줄일 수 있다.4B, when the DGS is implemented by inserting one or more windows 60 on the ground plane of the microstrip line, the physical length is reduced at the same frequency

) The electrical length remains almost the same (

), And as a result, the size of the circuit can be reduced by this principle.

4B illustrates a case where two windows 60 are formed on the bottom surface of the conductive layer 50 which is the ground plane. D denotes a distance between two windows 60, and W2 denotes a line width corresponding to a specific characteristic impedance when the window 60 is inserted.

In other words, when one or more windows 60 are formed in a standard microstrip line and a plurality of DGSs are inserted, the electrical length of the line becomes longer than that before the insertion of the DGS, It is possible to reduce the physical length. This principle is also called the slow-wave effect.

DGS inserted in a standard microstrip line is a typical example of an inductive perturbation structure since the equivalent inductance is mainly added to the line.

5 is a top perspective view showing a printed circuit board in a disc shape in which two dielectric layers 11 and 12 are butted against each other.

The printed circuit board of FIG. 1 has one dielectric layer 10, whereas the printed circuit board of FIG. 5 is composed of two dielectric layers 11 and 12. The other two printed circuit boards have the same structure.

The dielectric constant of the first and second dielectric layers 11 and 12 is represented by? _R1 and? _R2 , and the thicknesses of the two dielectric layers 11 and 12 are expressed by? _R1 and? _R2 , respectively, since two dielectric materials having different dielectric constants and thicknesses can be used in principle. Are denoted as H1 and H2. When the same dielectric material is used for the two dielectric layers 11 and 12, the relative permittivity is the same so that? _R1 =? _R2 . If the thicknesses of the two dielectric layers 11 and 12 are the same, H1 = H2. The thicknesses of the upper and lower conductor layers 31 and 51 are represented by T, but the influence of T on the overall characteristics is insignificant.

FIG. 6A is a top perspective view of a conventional SIAD microstrip line implemented from the printed circuit board of FIG. 5, and includes a transmission line 32 on a pattern side, first and second dielectric layers 11 and 12, Layer 51 is shown. W3 is a line width corresponding to a specific characteristic impedance.

6B is a bottom perspective view of FIG. 6A showing a plurality of via holes 52 formed on the ground plane, and a plurality of plated via holes 52 are formed in the second dielectric layer 12 having a thickness of H2 ) Is visually expressed in a two-dimensional periodically inserted structure.

6C is a partial perspective view illustrating the ground plane of FIG. 6A. FIG. 6D is a side cross-sectional view exemplarily showing a state in which the via hole is enlarged in the structure of FIG. 6A. FIG.

In a printed circuit board structure having two dielectric layers 11 and 12, when a plurality of via holes 52 plated in only the second dielectric layer 12 having a thickness H2 are two-dimensionally periodically inserted (see Figs. 6B and 6D) The electrical length of the line is increased compared to the standard microstrip line of the same physical length. In this case, it has already been known that the line width is reduced with respect to the same characteristic impedance.

6D, the plated via hole 52 is formed by drilling a cylindrical hole in the second dielectric layer 12, plating the inner wall of the cylindrical hole with a metal surface having a thin thickness, And is joined to the conductor layer 51 on the ground plane.

In Fig. 6D, a thick solid line indicates a metal surface. and d represents the diameter of the via hole 52. p means the repeated periodic pitch and should be greater than d. Since the thickness of the metal surface is relatively thin, if it is neglected, the portion corresponding to 'p-d' is the portion having the dielectric material.

The SIAD inserted in a standard microstrip line is a typical example of a capacitive perturbation structure because it adds an equivalent capacitance to the line.

The DGS microstrip line and the SIAD microstrip line described above have a propagation delay effect in which the electrical length increases when the physical length is the same as that of the standard type.

Therefore, in order to match the electrical lengths of the lines equally, the physical length must be reduced. By virtue of this principle, the physical length of the line can be reduced, thereby miniaturizing the circuit.

'로 표현된다. 여기서 L과 C는 각각 선로의 단위 길이당 등가 인덕턴스와 등가 커패시턴스를 나타낸다.On the other hand, the characteristic impedance Zc of the line is'

'. Where L and C represent the equivalent inductance and equivalent capacitance per unit length of the line, respectively.

Since the inductance L is dominantly increased by the window 60 etched on the ground plane of the DGS microstrip line, the characteristic impedance Zc is increased when the line width is the same as that of the standard microstrip line. In the SIAD microstrip line, the equivalent capacitance C is predominantly increased by the plated via hole 52, so that the characteristic impedance Zc is reduced when the line width is equal to that of the standard microstrip line.

In other words, the DGS microstrip line can reduce the length of the line compared to the standard type, but the linewidth of the line must be increased to match the same characteristic impedance. In the SIAD microstrip line, the length of the line can be reduced compared to the standard type, but the line width of the line must be reduced to achieve the same characteristic impedance.

Since the role of DGS and SIAD on the line width or characteristic impedance value is complementary, it is common to exclusively apply the structure of either DGS or SIAD exclusively. For example, when it is difficult to realize a high characteristic impedance with a standard microstrip line structure, it can be solved by inserting DGS. On the contrary, when it is difficult to realize a low characteristic impedance, it can be solved by a SIAD structure.

However, when the DGS or SIAD microstrip line is selectively applied, discontinuity is increased in the layout of the microwave circuit using the line when the line width variation is larger than that of the standard type, thereby deteriorating the performance of the circuit.

Therefore, even if the miniaturization effect of the circuit due to the propagation delay effect is obtained by using any one of the DGS microstrip line and the SIAD microstrip line, there is a possibility that the performance may be adversely affected by a change in line width of the line.

Double-sided microstrip line with common defective ground structure and wireless circuit device including the same Document Type and Number: WIPO Patent Application No. 10-1144565 B1 Issued on May 11, 2012,

M. Coulombe, et al., "Substrate Integrated Artificial Dielectric (SIAD) Structure for Miniaturized Microstrip Circuits ", IEEE. Antenna and Wireless Propagation Letters, vol. 6, pp. 575-579, Dec. 2007.

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the problems of the prior art as described above, and its object is to propose a new structure of a microstrip line combining DGS and SIAD in an optimal form and a radio circuit device using the same.

Another object of the present invention is to provide a microstrip line and a wireless circuit device using the microstrip line, which can reduce the physical length of the line as much as possible, thereby increasing the degree of integration and downsizing the circuit, as compared with a standard microstrip line or a DGS or SIAD microstrip line .

Another object of the present invention is to prevent the adverse effect of the performance due to the design change of the line width by having the line width most similar to the line width of the standard type microstrip line at the minimum line width variation, that is, the same characteristic impedance, as compared with the standard line type microstrip line. And a radio circuit device using the same.

Another object of the present invention is to provide a microstrip line and a wireless circuit device using the microstrip line that can simultaneously realize the circuit miniaturization and the minimum wire width design change compared to the standard type.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not to be construed as limiting the invention as defined by the appended art. It will be possible.

According to an aspect of the present invention, there is provided a microstrip line comprising: a first dielectric layer; A transmission line formed on one surface of the first dielectric layer; A defected ground structure (DGS) including a second dielectric layer and a ground conductor layer sequentially formed on the back surface of the first dielectric layer, the ground structure being formed by a window on the ground conductor layer; (Substrate Integrated Artificial Dielectric) structure formed by a plurality of plated via holes.

In the microstrip line according to the present invention, a structure in which the defect ground structure and the substrate integrated parasitic structure together are a coupling structure, a structure having only the defect ground structure in the coupling structure is a first structure, The transmission line length and the line width of the coupling structure are W and L, the transmission line length and the line width of the first structure are W1 and L1, the second structure is the second structure, Assuming that the transmission line length and line width of the structure are W2 and L2, W can be designed to satisfy 'W2 <W <W1' and L can be designed to satisfy L <L2 <L1.

In the microstrip line according to the present invention, the line width W of the coupling structure may be designed to have an intermediate value closer to the line width W2 of the second structure than the line width W1 of the first structure.

The microstrip line according to the present invention may include one or more windows of a geometrical shape as a defect ground structure on the ground conductor layer.

The microstrip line according to the present invention may include at least one geometric window having two defective areas and connection slots connecting the two defective areas as a fault ground structure on the ground conductor layer.

In the microstrip line according to the present invention, the window may be formed in a symmetrical shape in which the shape and size of the two defective areas are the same as each other, or in an asymmetric shape in which the shape and size of the two defective areas are different from each other.

A wireless circuit device using a microstrip line according to the present invention includes: a first dielectric layer; A transmission line formed on one surface of the first dielectric layer; A defected ground structure (DGS) including a second dielectric layer and a ground conductor layer sequentially formed on the back surface of the first dielectric layer, the ground structure being formed by a window on the ground conductor layer; (Substrate Integrated Artificial Dielectric) structure formed by a plurality of plated via holes.

According to the present invention, it is possible to provide a microstrip line having a novel structure in which DGS and SIAD are combined in an optimal form, and a radio circuit device using the same.

In addition, according to the present invention, the physical length of the line can be minimized as compared with a standard microstrip line or a DGS or SIAD microstrip line, thereby increasing the degree of integration and downsizing the circuit.

In addition, according to the present invention, when the minimum line width variation, that is, the same characteristic impedance, as compared with the standard microstrip line is used, the line width of the standard microstrip line is most similar to that of the standard microstrip line, .

In addition, according to the present invention, it is possible to reduce the length of a line to reduce the size of a circuit and simultaneously realize an effect of maintaining electrical performance with a line width similar to that of a standard type.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a printed circuit board in a state of a conventional disk; Fig.
2A and 2B are diagrams showing a configuration of a conventional standard type microstrip line.
Figs. 3A to 3C are diagrams showing a configuration of a conventional DGS microstrip line. Fig.
FIGS. 4A and 4B are diagrams comparing physical / electrical lengths of conventional standard type and DGS microstrip lines. FIG.
5 is a view showing a printed circuit board in a state of a disk including two dielectric layers.
6A to 6D are diagrams showing the configuration of a conventional SIAD microstrip line.
7A to 7D are diagrams showing the structure of a microstrip line coupled with an inductive and capacitive putter according to an embodiment of the present invention.
FIG. 8 is an exemplary view showing an actual fabrication state of a microstrip line coupled with an inductive and capacitive putter according to an embodiment of the present invention; FIG.
9 is a view showing transmission characteristics of the microstrip line shown in FIG. 8;
10A and 10B are diagrams illustrating a wireless circuit device using a microstrip line according to the technical idea of the present invention.
11 is a view for explaining an effect of the radio circuit device shown in Figs. 10A and 10B; Fig.
12A and 12B illustrate another embodiment of a radio circuit device using a microstrip line according to the technical idea of the present invention.
13 is a view for explaining the effect of the radio circuit device shown in Figs. 12A and 12B; Fig.

Since both DGS and SIAD have the effect of lengthening the electrical length in the microstrip line, when these two structures are used together, the electrical length is further increased.

Therefore, by inserting DGS and SIAD into a standard microstrip line, the physical length can be greatly reduced in order to maintain a constant electrical length, so that the circuit can be miniaturized as compared with the case where only standard / DGS / SIAD only exists.

In addition, as described above, when DGS is inserted into a standard microstrip line, the characteristic impedance is increased and the line width is increased, whereas when the SIAD is inserted, the characteristic impedance is lowered and the line width is reduced.

Therefore, if DGS and SIAD, which have a complementary effect on the line width, are inserted together in a standard microstrip line, the line width reduced by the SIAD is complemented by the DGS, thereby achieving the line width most similar to the standard type.

In this invention, the DGS and SIAD are combined in the optimal form to minimize the line width variation compared to the standard microstrip line, that is, the line width most similar to the standard type when the same characteristic impedance is used, A microstrip line with a new structure capable of downsizing the microstrip line is proposed.

Further, when the DGS and the SIAD are simply combined, the characteristic impedance of the line largely differs from that before coupling. Therefore, there is a need to determine the new line width by calculating the characteristic impedance after coupling. The line width design of the line will also be described later.

Hereinafter, a microstrip line coupled with inductive and capacitive putters according to a preferred embodiment of the present invention and its effect will be described in detail with reference to FIGS. 7A to 9 attached hereto.

FIGS. 7A to 7D are views showing the configuration of a microstrip line coupled with inductive and capacitive puttering according to an embodiment of the present invention.

7A, the microstrip line according to an embodiment of the present invention includes a first dielectric layer 111, a transmission line 130 formed on one surface of the first dielectric layer 111, a first dielectric layer 111 and the second dielectric layer 112 and the ground conductor layer 150 sequentially formed on the back surface of the second dielectric layer 111. [

7A, two dielectric layers 111 and 112 are bonded to each other, a transmission line 130 is formed on an upper surface (pattern surface) thereof, and a ground conductor (ground plane) is formed on a lower surface Layer 150 is constructed.

FIG. 7B is a bottom perspective view of FIG. 7A to assist visual understanding of the window 160 and the plurality of via holes 170. FIG. 7C is a partial perspective view illustrating the ground plane of FIG. 7A in order to assist a visual understanding of the three-dimensional shape of the ground conductor layer 150. FIG.

7D is a cross-sectional side view illustrating a state in which the via hole 170 and the two windows 160 are formed in the structures of FIGS. 7A and 7B. The two dielectric layers 111 and 112, the two windows 160, A ground plane constituted by a plurality of plated via holes 170, a ground conductor layer 150, and a pattern plane on which the transmission line 130 is formed.

With this configuration, the combination of the DGS formed by the window 160 on the ground conductor layer 150 and the SIAD formed by the plurality of plated via holes 170 passing through the second dielectric layer 112 Microstrip line is formed.

Specifically, in order to implement DGS, a part of the region is etched away from the ground conductor layer 150 into a predetermined geometrical shape to form one or more windows 160 on the ground plane.

In one embodiment, the dumbbell-shaped window 160 is constructed by connecting two defective areas of a rectangle in a connecting slot (a portion constituted by SW x SL) for convenience. However, the present invention is not limited to the illustrated embodiment, 160 can be configured in a variety of geometric shapes.

SL, SW, A, and B shown in FIG. 7C (b) refer to the dimensions of the dumbbell window 160.

A plurality of plated via holes 170 having a diameter of d and a spacing of p being constant are periodically passed through the second dielectric layer 112 (here, d <p), and the diameter of the cylindrical via hole 170 The SIAD can be formed by thinly plating the inner wall or filling the via hole 170 with metal to electrically contact the ground conductor layer 150 therethrough.

At this time, the relative dielectric constants of the dielectric materials constituting the two dielectric layers 111 and 112 may be different from each other (? _R1 ?? _R2 ) or may be equal to each other (? _R1 =? _R2 ). Also, the thicknesses of the two dielectric layers 111 and 112 may be different from each other (H1? H2) or may be equal to each other (H1 = H2).

The thickness T of the metal surface constituting the ground conductor layer 150 and the transmission line 130 and the thickness of the metal surface plated on the inner wall of the cylinder constituting the via hole 170 have any value, 170 are filled with a metal component, the technical idea of the present invention can be similarly applied.

As described above, DGS has an effect that the inductance per unit length of the line increases, and the propagation delay effect occurs, and the line width increases with respect to the same characteristic impedance. SIAD has the effect of increasing the capacitance per unit length of the line, causing the propagation delay effect, and also reducing the line width with respect to the same characteristic impedance.

Therefore, the microstrip line with the combined structure of DGS and SIAD can change the line width to the line width of the standard type again for the same characteristic impedance while generating the propagation delay effect to the greatest extent.

As a result, according to the microstrip line of the coupled structure according to the technical idea of the present invention, it is most advantageous for miniaturization of the circuit, and the layout discontinuity due to the change of the linewidth design of the microwave circuit using the microstrip line, Can be minimized.

In order to confirm and verify the effect of the microstrip line having such a coupling structure, a computer simulation and experimental results of the embodiment of the present invention shown in FIGS. 7A to 7D will be described As follows.

In the simulation and experiment, a microstrip line with a reduced physical length was designed and compared with a microstrip line with a different type of microstrip line, that is, with only standard / DGS / with only SIAD.

Accordingly, according to the technical idea of the present invention, the simulation and the experimental results of the four types of microstrip lines of the coupled microstrip line in which the DGS and the SIAD are combined together Are presented illustratively.

For simplicity, these four types of microstrip lines are abbreviated as standard type / basic DGS / basic SIAD / combination structure, respectively.

The following Table 1 compares the line width and length (λ / 4) at 1 GHz for four 50 Ω microstrip lines of the standard / basic DGS / basic SIAD / coupling structure.

track Line width
(mm) lambda / 4 @ 1 GHz
(mm) Standard type contrast
% Of length (%) Remarks
(Z _C = 50?) Standard type 2.87 53.71 - 2A, Basic DGS 3.87 44.31 82.5 4B, W2 Basic SIAD 1.28 41.92 78 6A, Joint structure 1.68 33.77 62.9 7A,

The design results and meanings of Table 1 will be described as follows.

First, in the coupling structure shown in FIGS. 7A to 7D, the thicknesses H1 and H2 of the two dielectric layers 111 and 112 are designed to be 5 mils and 31 mils, respectively (1 mil = 0.001 inch = 0.0254 mm). The dielectric constant of the two dielectric layers 111 and 112 is ε _r1 = ε _r2 and the same dielectric material is used. The thickness T of the metal surface constituting the transmission line 130 and the ground conductor layer 150 is 0.018 mm Respectively. The diameter d of the via hole 170 was 0.8 mm, and the constant distance p between the via holes 170 was 1.3 mm.

Referring to (b) of FIG. 7C, a dumbbell window having A = B = 3 mm, SL = 3.28 mm, and SW = 0.5 mm is used as the window 160 constituting the DGS. Two such dumbbell-shaped windows were used on the ground plane, and the spacing between the two windows was designed as D = 8.1 mm.

Under these basic conditions, a microstrip line with a characteristic impedance (Z _C ) of 50 Ω was designed at a frequency of 1 GHz, combining DGS and SIAD together. The resulting line width (W in FIG. 7A) and the length of λ / 4 Are respectively 1.68 mm and 33.77 mm.

In order to compare this with the standard / basic DGS / basic SIAD, the microstrip line with Z _C of 50 Ω as the standard microstrip line was designed at a frequency of 1 GHz. The line width (W 1 in FIG. and the length of? / 4 is 2.87 mm and 53.71 mm, respectively.

That is, it can be seen that the length of? / 4 obtained from the microstrip line of the coupled structure is only 62.9% (= 33.77 mm / 53.71 mm) as compared with the standard microstrip line.

On the other hand, even if ε _r1 = ε _r2 = 2.2 at the substrate of Figure 6a it is also ε _r = 2.2, inde same structure as the case of H = 36mils, Z _C = in a standard micro-strip line design also with 6a in 2a substrate 50Ω , The line width (W3 in FIG. 6A) and the length of? / 4 at the frequency of 1 GHz are 2.87 mm and 53.71 mm, respectively.

Third, a microstrip line with a Z _C of 50 Ω is designed for the basic DGS. In this case, the line width (W 2 in FIG. 4B) and the length of λ / 4 at a frequency of 1 GHz are 3.87 mm and 44.31 mm, respectively. The length of? / 4 is 82.5% of the standard type.

Fourth, we designed a microstrip line with a Z _C of 50 Ω for the basic SIAD. As a result, the line width (W3 in Fig. 6A) and the length of λ / 4 at 1 GHz are 1.28 mm and 41.92 mm, respectively. The length of λ / 4 is 78% of the standard type.

In order to compare the effects at various characteristic impedances, microstrip lines were designed for several characteristic impedance (Z _C ) values which are frequently used, and the results are summarized in Table 2.

Z _C Line width (mm) Standard type Basic DGS Basic SIAD Joint structure lambda / 4 @ 1 GHz (mm) 35Ω Line width (mm) 4 7.37 2 3.05 lambda / 4 @ 1 GHz (mm) 52.87 37.51 40.32 29.3 50Ω Line width (mm) 2.87 3.87 1.28 1.68 lambda / 4 @ 1 GHz (mm) 53.71 44.31 41.92 33.77 70Ω Line width (mm) 1.03 2.14 0.72 0.95 lambda / 4 @ 1 GHz (mm) 53.66 47.41 44.32 37.6 100Ω Line width (mm) 0.43 One 0.33 0.36 lambda / 4 @ 1 GHz (mm) 54.63 50.71 47.32 42

As shown in Table 2, the physical length of the line is shorter than that of the standard type / basic DGS / basic SIAD, and the line width is similar to that of the standard type. .

That is, the microstrip line of the coupled structure according to the present invention has a transmission line length which is the smallest value compared to the basic DGS and the basic SIAD, as well as the standard type at a specific characteristic impedance by combining the DGS and the SIAD together.

In addition, in order to satisfy the same characteristic impedance as those of the standard type, basic DGS and basic SIAD, the line width design method based on the simulation and experimental results discussed above, The line is designed to have a line width of medium value compared to the basic DGS and the basic SIAD, and maintains a line width that does not largely deviate from the standard type.

For example, for a 50 Ω characteristic impedance in Table 1, the length of λ / 4 of the coupling structure is 33.77 mm, which is the smallest value compared to the standard type / basic DGS / basic SIAD, and the line width of the coupling structure is 1.68 mm, And a line width of 1.28 mm in the case of the basic SIAD. Other basic conditions required for designing the microstrip line, such as the relative dielectric constant of the substrate, the height, the thickness of the metal surface, and the like, are the same.

Thus, the transmission line length and line width of the coupling structure applying the technical idea of the present invention to the same characteristic impedance are W and L, the transmission line length and line width of the basic DGS are W1 and L1, the transmission line length and line width of the basic SIAD W2 and L2, W is designed so as to satisfy 'W2 <W <W1', and L is designed to satisfy 'L <L2 <L1'.

Furthermore, as can be seen from the results of Tables 1 and 2, the line width W in the coupling structure has an intermediate value between the line width W1 of the basic DGS and the line width W2 of the basic SIAD, Can be designed to have a median value closer to the line width W2 of the SIAD.

8 is a photograph of a microstrip line having a line width and a length of 1.68 mm and a length of 33.77 mm and Z _C = 50 Ω, respectively, by applying the coupling structure shown in Table 1 with DGS and SIAD according to an embodiment of the present invention (A) and (b), respectively.

FIG. 9 shows a result of measuring the transmission characteristics of the coupled structure microstrip line shown in FIG. 8 using a direct vector network analyzer.

S11 and S21 show the reflection coefficient and the transmission coefficient (loss value), respectively, and show reflection coefficient of less than 28.4dB at 1GHz and a loss value of 0.155dB, indicating that the characteristic as a 50Ω microstrip line is well represented.

Hereinafter, one embodiment of a radio circuit device using a microstrip line according to the technical idea of the present invention will be described in detail with reference to FIGS. 10A to 11 attached hereto.

As described above, both the DGS and the SIAD inserted in the standard microstrip line are complementary to the line width while reducing the length of the line. Therefore, the combination of the two structures greatly reduces the length of the line without changing the characteristic impedance greatly, which is very advantageous for miniaturization of the circuit.

By using the proposed microstrip line, it is possible to reduce the size of the high frequency band wireless circuit device such as the Wilkinson power divider and increase the degree of integration.

In this embodiment, a Wilkinson power divider that is miniaturized using a microstrip line having a combination structure of DGS and SIAD is designed according to the technical idea of the present invention, and the effect is designed by using a power divider designed with other types of microstrip lines .

FIG. 10A shows an example of a Wilkinson power distributor designed at a center frequency of 1 GHz, which is an embodiment in which a microstrip line having a coupled structure with DGS and SIAD is applied to a microwave band wireless circuit device.

(b) shows a ground conductive layer 250 on the lower surface, a window 260 in the form of a dumbbell, and a plurality of plated via holes 270 arranged periodically. Are illustrated. The arrangement of the transmission line 230 and the window 260 is shown separately in FIG. 10B for the sake of understanding.

The core area of the Wilkinson power divider layout was designed to be 469.91 mm2. The Wilkinson power divider layout is well known, where the critical area is defined as the area of the basic 2-way Wilkinson power divider that eliminates the line portion connected to the input terminal and the two output terminals in the layout, And the area of the portion constituting the closed curved surface due to the isolation resistance. In the case of a line connected to the input and output terminals, the length can be arbitrarily adjusted according to the convenience. Therefore, it is not known when comparing the sizes of the circuits. It is well known that the sizes of the circuits are compared with the core area.

In this embodiment, a Wilkinson power divider layout is designed at the same frequency using three different types of microstrip lines to compare with the Wilkinson power divider using the microstrip line coupled with the inductive and capacitive puttering shown in FIG. Respectively.

In the three Wilkinson power divider layouts designed with a standard microstrip line at the same center frequency 1 GHz, a microstrip line with DGS only, and a microstrip line with only SIAD, the core area was 877.74 mm 2, 744.15 mm 2, and 581.44 mm 2, respectively.

In other words, the core area of 469.91mm2 was the smallest when the microstrip line with the combined structure of both DGS and SIAD was designed, and the core area was only 53.54% compared with the standard microstrip line.

FIG. 11 is a diagram for comparing the core area in the Wilkinson power divider layout. In the case of designing with a microstrip line having only DGS (TL11), designing with a microstrip line having only SIAD (TL12), DGS and SIAD (TL13), which is designed as a microstrip line of a coupled structure.

When designing with a standard microstrip line, the core area is of course the largest, so it is not shown here.

When the line portion connected to the input and output terminals is removed, it can be seen that the Wilkinson power divider designed as a microstrip line having a combination structure including both DGS and SIAD proposed in the present invention is the smallest at the same frequency.

Although a symmetric Wilkinson power divider is taken as an example in the present embodiment, the technical idea of the present invention can be applied to design of an asymmetric power divider.

Hereinafter, another embodiment of the radio circuit device using the microstrip line according to the technical idea of the present invention will be described in detail with reference to FIGS. 12A to 13 attached hereto.

In this embodiment, a miniaturized branch line hybrid coupler is designed using a microstrip line in which both DGS and SIAD are combined, and this is compared with the case of designing with a different type of microstrip line.

12A shows a photograph of a branch line hybrid coupler designed at a center frequency of 1 GHz by applying a microstrip line combining both DGS and SIAD.

(b) shows a ground conductive layer 350 on the lower surface, a dumbbell window 360, and a plurality of plated via holes 370 arranged periodically. . For the sake of understanding, the arrangement of the transmission line 330 and the window 360 is separately shown in FIG. 12B.

According to the technical idea of the present invention, in the layout of the branch line hybrid coupler designed by applying the microstrip line having DGS and SIAD together, the core area was 1,373.1 mm 2.

The layout of the branch line hybrid coupler is well known. Here, the core area refers to the area of a portion of the circuit that forms the closed curved surface from the layout of the basic branch line hybrid coupler after removing the line portion connected to the four terminals.

It is well known that the line connected to the four terminals can be arbitrarily adjusted in length depending on the convenience, and thus can not be taken into consideration when comparing the sizes of the circuits. It is well known that the circuit size is compared with the core area.

In order to confirm the effect of the branch line hybrid coupler shown in Figs. 12A and 12B, several branch line hybrid coupler layouts were designed at the same frequency by different kinds of microstrip lines, and their core area areas were compared with each other.

The core areas of the two other branch-line hybrid coupler layouts, with DGS only microstrip lines with SIAG only, and microstrip lines with SIAD only at 1 GHz, were 2,547.6 mm2 and 1,969 mm2, respectively.

As a result, the size of the microstrip line with both DGS and SIAD was the smallest at 1,373.1 mm 2, and the core area was 53.9% compared with the case of the microstrip line including only DGS, The area of core area was only 70% compared with the case of design by line.

FIG. 13 is a diagram for comparing core area according to microstrip line type in the layout of a branch line hybrid coupler. In the case of designing a microstrip transmission line with only DGS (TL21) and a microstrip line with only SIAD (TL22), and a microstrip line with both DGS and SIAD (TL23).

When designing with a standard microstrip line, the core area is of course the largest, so it is not shown here.

When the line portion connected to each terminal is removed, it can be seen that the branch line hybrid coupler designed as a microstrip line having a combination structure including both DGS and SIAD according to the present invention is the smallest at the same frequency.

The configuration of the microstrip line coupled with the inductive and capacitive putter according to the present invention and the structure of the wireless circuit device using the microstrip line are not limited to the above-described embodiments, and various modifications may be made within the scope of the technical idea of the present invention. can do.

For example, in the drawings of this specification including Figs. 7B, 10A, 12A, and the like, a dumbbell-type window constructed by connecting two rectangular defect regions with connection slots (a portion composed of SW x SL) The window can be composed of various other geometric shapes.

For example, the shape of the two defective areas on both sides of the window may be a circle, a polygon (N square, N is an integer of 3 or more) such as a circle, a triangle / a pentagon / a hexagon / an octagon, an eddy type, a sector type, a zigzag type, Type (peanut type or snowman type) or the like.

Further, when the window is a dumbbell shape, both side defect regions may be formed in a symmetrical shape having the same shape and size, or may be formed in an asymmetric shape in which the shape and size of both side defect regions are different from each other.

Further, the connection slot connecting the defect regions on both sides may be a curved, curved shape rather than an elongated straight shape. It is also possible to connect symmetrical or asymmetric defective areas on both sides with one or more connection slots of two or more.

The overall shape of the window may be a shape other than a dumbbell shape, that is, a polygon (N square, N is an integer of 3 or more), an annular shape, a fan shape, a zigzag shape, a donut shape such as a circle, a triangle, a square / pentagon / A geometric pattern of various shapes such as a shape of a circle, a shape of a circle (a peanut shape or a snowman shape), or the like.

The embodiments of the wireless circuit device referred to in this specification are only a few examples of applying the technical idea of the present invention, and they are applicable to various types of microwave circuits / components for various systems such as mobile communication, satellite communication, In the miniaturization design, the microstrip line coupled with the technical idea of the present invention, that is, the inductive and capacitive putter, can be applied.

In addition, various frequency band filters, power dividers and combiners, directional couplers, branch line hybrid couplers, ring hybrid couplers, which constitute various circuits / components including baluns, amplifiers, frequency mixers, oscillators, frequency multipliers and dividers, and the like. A microstrip line to which a capacitive putter is coupled can be applied.

111 and 112: first and second dielectric layers
130: transmission line
150: ground conductor layer
160: Window
170: Beer hole

Claims (7)

A first dielectric layer; A transmission line formed on one surface of the first dielectric layer; A second dielectric layer sequentially formed on a back surface of the first dielectric layer, and a ground conductor layer,
A substrate integrated dielectric dielectric (SIAD) formed by a defected ground structure (DGS) formed by a window on the ground conductor layer and a plurality of plated via holes penetrating the second dielectric layer, Microstrip line with structure together. The method according to claim 1,
The structure having only the defect ground structure and the substrate integrated parasitic structure together is a coupling structure, a structure having only the defect ground structure of the coupling structure is a first structure, and a structure having only the substrate integrated parasitic structure 2 structure,
Assuming that the transmission line length and line width of the coupling structure are W and L, the transmission line length and the line width of the first structure are W1 and L1, the transmission line length and the line width of the second structure are W2 and L2, respectively, with respect to the same characteristic impedance when doing,
W is designed to satisfy 'W2 <W <W1', and L is designed to satisfy 'L <L2 <L1'. 3. The method of claim 2,
Wherein the line width W of the coupling structure is designed to have a median value closer to the line width W2 of the second structure than the line width W1 of the first structure. The method according to claim 1,
And a defective ground structure on the ground conductor layer, wherein the defective ground structure includes at least one window of a geometric shape. The method according to claim 1,
And a defective ground structure on the ground conductor layer, wherein the defective ground structure includes at least one geometrical window composed of two defective areas and connection slots connecting the two defective areas. 6. The method of claim 5,
Wherein the window is formed in a symmetrical shape in which the shape and size of the two defective areas are the same, or the shape and size of the two defective areas are formed in different asymmetric shapes. A first dielectric layer; A transmission line formed on one surface of the first dielectric layer; A second dielectric layer sequentially formed on a back surface of the first dielectric layer, and a ground conductor layer,
A substrate integrated dielectric dielectric (SIAD) formed by a defected ground structure (DGS) formed by a window on the ground conductor layer and a plurality of plated via holes penetrating the second dielectric layer, And a microstrip line.

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