KR101509423B1 - Multi Chip System with Plurality of Interfaces Port - Google Patents

Abstract

Disclosed is a multi-reception chip system having multiple interface ports. A technology for minimizing the number of input/output (I/O) pins is applied to the multiple-reception chip system. A structure of the multiple-reception chip system can easily respond to various applications. Therefore, the number of the pins, increased as the number of applied slave chips is increased, can be reduced. Moreover, an interface between an application processor chip and the slave chip and an interface between the slave chips can be simplified. The multi-reception chip system includes: a slave group which communicates through an interface for diversity; and a master which controls input and output conditions of each slave to vary.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multi-

The present embodiment relates to a technique for minimizing the number of input / output (I / O) pins in a multi-receiving chip system or for simplifying a pin map.

It should be noted that the following description merely provides background information related to the present embodiment and does not constitute the prior art.

1 is a block diagram schematically showing a conventional multi-chip system 100 for a 4-diversity application. The conventional multi-chip system 100 for four-diversity includes a slave group 110 and a master chip (e.g., an application processor) 120. The slave group 110 includes a slave chip 0 112, a slave chip 1 114, a slave chip 2 116 and a slave chip 3 118. The diversity interface between the slaves 112 to 118 included in the slave group 110 includes a user defined bus including a clock, a valid value Vaild and bit data.

The conventional multi-chip system 100 includes two or more slave chips (slave chip 0 112 to slave chip 3 118) performing the same function and a master chip 120 controlling two or more slave chips . Each of the slave chips (slave chip 0 (112) to slave chip 3 (118)) are connected in series to each other for diversity. For example, the slave chips (slave chip 0 112 to slave chip 3 118) use identification pins of fixed chip IDs (for example, fixed chip ID 0 to fixed chip ID 3) Or pins connected in series transmit and receive predetermined pattern data to internally generate the IDs of the respective slave chips (slave chip 0 (112) to slave chip 3 (118)). The slave chip 0 (118) transmits the final combined signal of the diversity signal to the master chip (120) and outputs TS (Transport Stream) data.

A technique for distinguishing the slave chips (slave chip 3 112 to slave chip 0 118) in the conventional multi-chip system 100 will be described. There is a technique of distinguishing slave chips using a separate CS (Chip Select) or using pins for chip ID identification in the slave group 110 in order to distinguish the slaves included in the slave group 110 in the master chip 120 do. There is also a technique of separating an interface port by a method of automatically generating a chip ID after transmitting and receiving a pattern determined by the diversity path in the slave group 110 or allocating an additional CS in the slave group 110 . There is also a technology for automatically generating a chip ID using the port control of the slaves included in the slave group 110.

However, in the related art, there is a problem that diversity data is transmitted / received between slaves included in the slave group 110 while supporting various interface modes, thereby increasing the number of pins and complicating the pin map.

The present embodiment can reduce the number of pins that are increased according to the number of slave chips due to a technique for minimizing input / output (I / O) pins and a system structure that is easy to cope with various applications. The main purpose is to provide a multi-chip system that can simplify the interface between the interface and the slave chips.

According to an aspect of the present invention, there are provided a diversity interface (S-I) having two or more slaves transmitting and receiving a diversity signal in series and having a plurality of interface ports for each of the slaves, A slave group communicating with the slave group; And a master for controlling an input / output (I / O) state of each of the slaves in the slave group by using the diversity interface.

The interface for diversity includes an A interface port INT_A including an A master interface and an A slave interface; And a B interface port (INT_B) including a B master interface and a B slave interface, wherein the A interface port switches to the A master interface or the A slave interface according to a control command of the master, Can switch to the B master interface or the B slave interface according to the control command of the master.

The A interface port INT_A and the B interface port INT_B may support at least one of a serial peripheral interface (SPI), an inter-integrated circuit (I2C), and a secure digital I / O (SDIO).

The master of the multi-chip system selects one of the master interface and the slave interface included in the diversity interface, and switches the master interface or the slave interface. The input / output (I / O) The number of pins can be minimized.

The master of the multi-chip system uses the diversity interface to communicate with one of the master interface and the slave interface according to the operation mode of each of the slaves. In accordance with the maximum data transmission rate (Max Data Rate) for diversity communication It is possible to variably select the data bit width (Data Bit Width).

The master of the multi-chip system sets the A interface port (INT_A) and the B interface port (INT_B) included in the diversity interface after a reset command and sets the A interface port (INT_A) as a slave interface The B interface port INT_B may be set as a master interface or a slave interface and the port status of the B interface port INT_B may be set as a slave interface or a master interface by using the A interface port INT_A.

The master of the multi-chip system indicates the initial state for the RF or baseband configuration register as the diversity interface when the slave group is operated in 2-diversity, (Slave Chip 0) of the slave operating in the 2-diversity mode, the second interface (INT_A) of the second slave (slave chip 0) A slave (slave chip 1) can not access to the first slave (slave chip 0) because a status register set in the idle period in which the diversity path is time- Lt; / RTI >

The master of the multi-chip system is configured such that, when the slave group is operated in 2-diversity, when accessing the internal register of the second slave (slave chip 1), the B interface port of the second slave (slave chip 1) INT_B) to access the second slave of the 2-diversity slaves.

The master of the multi-chip system uses the B interface port (INT_B) of the slaves operating in the 2-diversity mode when the slave group is operated in 2-diversity, so that each of the 2-diversity slaves You can change the interface type to the initial state.

The master of the multi-chip system may be configured such that when the slave group is operated in two-diversity, the two slaves operating in the 2-divergence mode are each in a single mode to implement a dual receiver function .

The master of the multi-chip system is configured such that, when the slave group is operated in 2-diversity, in the dual receiver state, the interface port (INT_A) of the first slave (slave chip 0) (Transport Stream) data of a slave in which trouble has occurred to the B interface port (INT_B) of the second slave (slave chip 1), and a first A It is possible to receive the TS data using the interface port INT_A.

The master of the multi-chip system indicates an initial state for the RF or baseband configuration register when the slave group is operated in 4-diversity, and when the interface type between the slaves is changed after the setting of the initial state is completed , It becomes impossible to access the remaining slaves using the first interface port (INT_A) of the first slave (slave chip 0) of the 4-diversity slave, so that the diversity path is set in the time- One status register can be transmitted to the first slave (slave chip 0).

The master of the multi-chip system may be configured such that, when the slave group is operated in 4-diversity, if it is desired to access the internal register of one of the 4-diversity slaves, the 4th slave (slave chip 3) Diversity-enabled slave can be accessed by using the B interface port INT_B of the 4-diversity-enabled slave.

The master of the multi-chip system uses the B interface port (INT_B) of the slaves operating in the 4-diversity mode when the slave group is operated in 4-diversity, so that each of the 4-diversity operated slaves You can change the interface type to the initial state.

The master of the multi-chip system may be configured such that, when the slave group is operated in 4-diversity, three slaves of the 4-diversity slave operate in the diversity mode to implement the dual receiver function, The slave can be operated in the single mode.

The master of the multi-chip system is configured such that when the slave group is operated in 4-diversity, a problem arises in the interface port (INT_A) of the first slave (slave chip 0) and the interface with the master in the dual receiver state (Slave chip 3) of the slave operated in the 4-diversity operates in the single mode and receives the TS data into the B interface port INT_B of the fourth slave (slave chip 3), and the 4th slave (Slave chip 0) to the third slave (slave chip 2) in the diversity mode and sets the A interface port INT_A of the first slave (slave chip 0) to the diversity mode It is possible to receive the TS data.

The master of the multi-chip system is configured such that, when the slave group is operated in 2-diversity, the first slave (slave chip 0) and the second slave (slave chip 1) among the 2-diversity slaves The interface port for diversity can be accessed in the reverse direction by inverting the interface port of the first slave (slave chip 0) in a time period in which data is not transmitted to the second slave (slave chip 1).

As described above, according to the present embodiment, since the technology for minimizing the input / output (I / O) pin and the system structure that is easy to cope with various applications can reduce the number of pins increased according to the number of slave chips, The interface with the chip and the interface between the slave chips can be simplified.

According to the present embodiment, the diversity interface between the slave chips can be realized by an SPI (Serial Peripheral Interface) bus that supports various data bits, thereby minimizing the number of input / output (I / O) pins, And the interface between the slave chips can be simplified. Further, in a diversity environment, there is an effect that a master can access all slave chips without a chip ID for distinguishing a slave. Further, there is an effect that the dual receiver function can be supported even in the diversity mode of the multi-receiving chip system.

1 is a block diagram schematically showing a conventional multi-chip system for four-diversity use.
2A and 2B are diagrams illustrating a 4-wire SPI bus configuration along with a standard input / output (I / O) SPI bus.
3 shows a 3-wire SPI bus configuration along with a single input / output (I / O) SPI bus.
4 shows a 4-wire SPI bus configuration along with a double input / output (I / O) SPI bus.
5 is a diagram illustrating a six-wire SPI bus configuration along with a quad input / output (I / O) SPI bus.
6A and 6B are block diagrams schematically showing a multi-chip system having a plurality of interface ports according to the present embodiment.
7A to 7E are diagrams showing interface ports at the time of 2-diversity operation according to the present embodiment.
8A to 8E are views showing interface ports at the time of 4-diversity operation according to the present embodiment.
FIG. 9 is a diagram showing the inversion of the interface ports at the time of 2-diversity operation according to the present embodiment.
10 is a diagram illustrating a 2-diversity and 4-diversity pin map supporting SPI and TSIF according to the present embodiment.

Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings.

2A and 2B are diagrams illustrating a 4-wire SPI bus configuration along with a standard input / output (I / O) SPI bus.

2A and 2B are exemplary diagrams illustrating a 4-wire Serial Peripheral Interface (SPI) bus configuration. FIG. 2A is an exemplary diagram showing a configuration in which each slave 212 to 218 has a unique SPI_CS (Chip Select). 2B is a configuration in which SPI_CS is shared by the slaves 212 to 218 if the slaves 212 to 218 can be distinguished by the chip ID.

The slave group 210 shown in FIGS. 2A and 2B uses signals of SPI_CLK (SPI CLOCK), SPI_MOSI (Master Out Slave In), SPI_MISO (Master In Slave Out) and SPI_CS. SPI_CLK denotes a synchronization clock output from the master chip 220. The data exchange between the master chip 220 and the slave group 210 proceeds based on the SPI_CLK. SPI_MOSI is a line for sending information to the slave group 210 as an output of the master chip 220. On the other hand, SPI_MISO is a line for receiving information of the slave group 210 by the master chip 220 as an output of the slave group 210. The SPI_CS is a signal for selecting one of the slave groups 210 as an output of the master chip 220.

As shown in FIGS. 2A and 2B, the SPI_MOSIs of the master chip 220 and the slave group 210 are connected to each other and the SPI_MISOs are connected to each other. The SPI_CS is connected to the SPI_CS of the slave group 210 as an output of the master chip 220 for the master chip 220 to select any one of the slave groups 210. The slave group 210 can be activated only while the SPI_CS input is '0'.

Below. Describe the SPI communication process. To proceed with the communication, the master chip 220 first outputs '0' to the SPI_CS to activate the corresponding slave. Next, the master chip 220 outputs a clock for synchronization with the SPI_CLK, and outputs the data to the SPI_MOSI bit by bit according to the clock. At the same time, the master chip 220 reads the SPI_MISO bit by bit according to the clock outputted by the master chip 220 itself. In other words, the master chip 220 outputs the data to the SPI_MOSI in accordance with the output SPI_CLK of the master chip 220 and simultaneously receives the data in the SPI_MISO. At this time, the SPI bus always carries out bidirectional communication. Data is received with SPI_MISO while outputting data with SPI_MPSI according to SPI_CLK. Similarly, in order to read data of the slave group 210, data is output to SPI_MOSI while information is input to SPI_MISO in accordance with SPI_CLK.

FIG. 3 shows an example of a 3-wire SPI bus configuration that is a half-duplex transaction by sharing SPI_MOSI and SPI_MISO lines. In this case, there is one data bit. Figure 4 is an example of a four-wire SPI bus configuration, which is a half-duplex transaction, with two data bits. Figure 5 is an exemplary diagram of a six-wire SPI bus configuration, which is a half-duplex transaction, with four data bits.

6A and 6B are block diagrams schematically showing a multi-chip system having a plurality of interface ports according to the present embodiment.

The multi-chip system 600 having a plurality of interface ports according to the present embodiment includes a slave group 610 and a master chip 620. Slave group 610 includes slave chip 0 612, slave chip 1 614, slave chip 2 616 and slave chip 3 618. The components included in the multi-chip system 600 according to the present embodiment are not limited thereto. 6A and 6B, it is assumed that the multi-chip system 600 according to the present embodiment is a 4-diversity environment.

Hereinafter, the slave chip 0 (612) is referred to as a 'first slave', the slave chip 1 (614) as a 'second slave', the slave chip 2 (616) as a 'third slave' The slave chip 3 618 will be referred to as a 'fourth slave' and the master chip 620 will be referred to as a 'master'.

The slave group 610 and the master 620 each include an RF processing unit for receiving analog data (bit stream) from a transmitter (transmitting apparatus) by using a receiving antenna for each channel, a fast Fourier transform (FFT) An orthogonal frequency division multiplexing (OFDM) signal processing unit for generating processed data by performing channel estimation and channel compensation on the processed data, a channel compensation unit for generating compensation data on channel estimation and channel compensation of the processed data, A deinterleaver for generating deinterleaving data rearranged into a plurality of blocks (e.g., rows and columns of blocks), a diversity processor for performing communication with different diversity processors, a demodulator for deinterleaving data, A demapper for outputting the demodulated data, and decoded data obtained by decoding the data string of the demodulated data Board may include a decoding unit. In addition, the multi-chip system 600 may be implemented as a receiver for ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) mobile broadcasting, but is not limited thereto.

In the slave group 610 according to the present embodiment, two or more slaves 612 to 618 for transmitting and receiving a diversity signal are serially connected and a plurality of interface ports Port) for diversity.

The master 620 according to this embodiment controls the input / output (I / O) states of the slaves 612 to 618 in the slave group 610 to vary by using a diversity interface.

The diversity interface will be described below. The diversity interface includes an A interface port (INT_A) including an A master interface and an A slave interface. In addition, the diversity interface includes a B interface port (INT_B) including a B master interface and a B slave interface. The A interface port switches to the A master interface or the A slave interface in accordance with the control command of the master 620. The B interface port switches to the B master interface or the B slave interface according to the control command of the master 620.

The A interface port INT_A and the B interface port INT_B support at least one interface among SPI (Serial Peripheral Interface), I2C (Inter-Integrated Circuit) and SDIO (Secure Digital I / O). For example, the A interface port INT_A may include an A master interface and an A slave interface supporting SPI, and may include an A master interface and an A slave interface supporting I2C. An A master interface And an A-slave interface. In addition, the B interface port (INT_B) may include a B master interface and a B slave interface that support SPI, and may include a B master interface and a B slave interface that support I2C, and a B master interface And a B-slave interface. Of course, the interfaces supported by the A interface port (INT_A) and the B interface port (INT_B) are not limited to at least one of SPI, I2C and SDIO, and various modifications and changes may be made without departing from the technical scope of the present invention. It will be possible to apply it by modification.

Hereinafter, the interface ports included in the slave group 610 will be described with reference to FIGS. 6A and 6B. Here, it is assumed that the multi-chip system 600 operates in a 4-diversity environment.

The first slave 612 includes a first A interface port INT_A and a first B interface port INT_B. The first A interface port INT_A includes a 'first A master interface' and a 'first A slave interface'. The first B interface port INT_B includes a 'first B master interface' and a 'first B slave interface'.

The second slave 614 includes a second A interface port INT_A and a second B interface port INT_B. The second A interface port INT_A includes a 'second A master interface' and a 'second A slave interface'. The second B interface port INT_B includes a 'second B master interface' and a 'second B slave interface'.

The third slave 616 includes a third A interface port INT_A and a third B interface port INT_B. The third A interface port INT_A includes a 'third A master interface' and a 'third A slave interface'. The third B interface port INT_B includes a 'third B master interface' and a 'third B slave interface'.

The fourth slave 618 includes a fourth A interface port INT_A and a fourth B interface port INT_B. The fourth A interface port INT_A includes a 'fourth A master interface' and a 'fourth A slave interface'. The fourth B interface port INT_B includes a 'fourth B master interface' and a 'fourth B slave interface'.

The master 620 allows either the master interface (A master interface and B master interface) included in the diversity interface or the slave interface (A slave interface and B slave interface) to be selected. The master 620 allows switching between master interfaces (A master interface and B master interface) or slave interfaces (A slave interface and B slave interface) in the diversity interface. The master 620 communicates with the slave group 610 using the diversity interface so that the number of input / output pins of the slave group 610 is minimized.

6A is a multi-chip system having two peripherals such as an SPI and an I2C (Inter-Integrated Circuit) for the slave group 610 interface. The SPI peripherals between the slaves 612 to 618 in the slave group 610 are operated as the SPI master interface or SPI slave interface according to the operation mode and the data according to the maximum data transfer rate (Max Data Rate) And has an SPI bus structure capable of variably selecting a bit width (Data Bit Width).

In other words, as shown in FIG. 6A, the master 620 uses the diversity interface to communicate with the A interface port in one of the A master interface or the A slave interface according to the operation mode of each of the slaves 612 through 618 And allows the B interface port to communicate with either the B master interface or the B slave interface. The master 620 allows the data bit width to be variably selected according to the maximum data transmission rate for diversity communication.

6B shows the state of the A interface port INT_A and the state of the B interface port INT_B of each slave chip after a hardware reset. A interface port (INT_A) can be set to a slave interface (SPI or I2C), a B interface port (INT_B) can be either a master interface or a slave interface, (INT_B) state can be set to the slave interface or the master interface.

In other words, as shown in FIG. 6B, the master 620 sets the A interface port (INT_A) and the B interface port (INT_B) included in the interface for diversity after the reset command. The master 620 sets the A interface port INT_A to the A slave interface and then sets the B interface port INT_B to the B master interface or the B slave interface. The master 620 uses the A interface port INT_A to set the port status of the B interface port INT_B to the B slave interface or the B master interface.

7A to 7E are diagrams showing interface ports at the time of 2-diversity operation according to the present embodiment.

7A shows an initial state for a configuration register of RF and baseband. Thereafter, the state of FIG. 7B is obtained by changing the SPI interface type (master interface or slave interface) between the slave chips 612 to 614 after the initial state is set. In other words, as shown in FIG. 7A, the master 620 indicates an initial state for the RF or baseband configuration register as an interface for diversity when the slave group 610 is operated in 2-diversity.

7B shows a two-diversity operation state in which diversity combining is performed. Since the master 620 can not access the second slave 614 using the first A interface port INT_A of the first slave 612 in the 2-diversity operating state, To the first slave 612, a status register (including an interrupt) preset in an idle period in which the path is time-division-divided. However, the BER (Bit Error Rate) update in the second slave 614 is not supported in the manual mode by the master 620 and can be provided only in the automatic mode. In other words, as shown in FIG. 7B, when the interface type between the slaves operating in 2-diversity is changed after the setting of the initial state is completed, the master 620 selects the first slave The access to the first slave 612 is disabled using the first A interface port INT_A of the first slave 612 and therefore the predetermined state register is transmitted to the first slave 612 in the idle period in which the diversity path is time- .

FIG. 7C shows an access method in a case where an attempt is made to access an internal register of the second slave (in some cases, to the first slave 612) in the 2-diversity operation state. And can access the slaves 612-614 using the second B interface port (INT_B) of the second slave 614. The second B interface port INT_B of the second slave 614 may also be used to access the slaves 612-614 to change the SPI interface type between the slaves 612-614 to the initial state. 7C, when the slave group 610 is to be operated in 2-diversity, when the master 620 desires to access the internal register of the second slave 614, the second slave 614 The second slave 614 of the 2-diversity slave is accessed using the second B interface port (INT_B) The master 620 is connected to each of the B interface ports of the slaves (first slave 612 and second slave 614) operated in two-diversity when the slave group 610 is operated in two- INT_B) to change the interface type of the slaves operating in each 2-diversity to the initial state.

7D illustrates a method of implementing a dual receiver function in a two-diversity operating state. That is, the two slaves 612 to 614 operate in a single mode, respectively. For example, when the master 620 receives TS (Transport Stream) data of the dual receiver only from the first slave 612, the transmission data between the second slave 614 and the first slave 612 is TS data The TS data transmitted by the second slave 614 is stored in the TS buffer of the first slave 612 using the internal bus. In other words, as shown in FIG. 7D, when the slave group 610 is operated in two-diversity mode, the master 620 transmits two slave (two-slave) 1 slave 612 and second slave 614) to operate in a single mode.

7D, the master 620 is connected to the second A interface port INT_A of the second slave 614 in the direction of the first B interface port INT_B of the first slave 612, So that the TS data of the slave 614 is transmitted to the first slave 612. The master 620 then receives the TS data of each slave (the first slave 612 and the second slave 614).

7E shows a case in which the master 620 is connected to the second B interface port (not shown) of the second slave 614 when there is a problem of throughput of the interface with the master 620 in the dual receiver function implementation of the 2- INT_B) and receives the TS data using the first A interface port (INT_A) of the first slave 612. In other words, as shown in FIG. 7E, when the slave group 610 is operated in 2-diversity, the master 620 transmits, in the dual receiver state, the first A interface port INT_A of the first slave 612 The TS data of the slave chip in which the problem has occurred is received at the second B interface port INT_B of the second slave 614 and the TS data of the slave chip of the first slave 612 Data is received using the first A interface port (INT_A).

8A to 8E are views showing interface ports at the time of 4-diversity operation according to the present embodiment.

8A shows an initial state for the RF and baseband configuration registers. After the setting of the initial state is completed, the state of FIG. 8B is obtained by changing the SPI interface type (master interface or slave interface) between the slave chips 612 to 618. In other words, as shown in FIG. 8A, the master 620 represents an initial state for the RF or baseband configuration register when the slave group 610 is operated in 4-diversity.

8B shows a 4-diversity operation state in which diversity combining is performed. The master 620 can not access the remaining slaves 614 to 618_ by using the first A interface port INT_A of the first slave 612 in the 4-diversity operation state, The BER update of the second slave 614, the third slave 616 and the fourth slave 618 may be performed by a master (not shown) The master 620 can not support the manual mode and only the automatic mode can be provided. In other words, as shown in FIG. 8B, when the interface type between the slaves is changed after the initial state is set, Since the access to the remaining slave chips becomes impossible using the first A interface port INT_A of the first slave 612 among the diversity slaves 612, To the first slave (612).

8C shows an example of how to access the internal registers of the fourth slave 618, the third slave 616, or the second slave 614 (and possibly the first slave 612) in a four- In the case of access. And the fourth B interface port (INT_B) of the fourth slave 618 can be used to access the slaves 612 through 616. In addition, the SPI interface type between the slaves 612 to 618 can be changed to the initial state by using the fourth B interface port (INT_B) of the fourth slave 618. As shown in FIG. 8C, when the slave group 610 is operated in 4-diversity mode and the slave group 610 is accessed in an internal register of any one of 4-slave operated slaves, 4 slave 618 accesses any slave of the 4-diversity slave using the fourth B interface port INT_B of the slave 618. [ When the slave group 610 is operated in the 4-diversity mode, the master 620 uses the first to fourth B interface ports (INT_B) of the slaves operating in 4-diversity, To the initial state.

8D illustrates a method for implementing a dual receiver function in a 4-Diversity operating state. That is, the three slaves operate in the diversity mode and the remaining one slave operates in the single mode. For example, when the master 620 receives the TS data of the dual receiver only in the first slave 612, the transmission data between the second slave 614 and the first slave 612 is set to be the TS data And the TS data transmitted by the second slave 614 are stored in the TS buffer of the first slave 612 using the internal bus. In other words, as shown in FIG. 8D, when the slave group 610 is operated in the 4-diversity mode, the master 620 transmits three slaves of 4-diversity to implement the dual receiver function, To operate in the diversity mode and the remaining one slave to operate in the single mode.

FIG. 8E illustrates a case where there is an interface throughput problem with the master 620 in the dual receiver function implementation of the 4-diversity operation, the master 620 operates only the fourth slave 618 in the single mode only, B interface port (INT_B). The master 620 operates the first slave 612, the second slave 614 and the third slave 616 in the diversity mode and uses the first A interface port INT_A of the first slave 612 TS data is received. In other words, as shown in FIG. 8E, when the slave group 610 is operated in the 4-diversity mode, the master 620 is in the dual receiver state

When a problem arises in the interface throughput between the first A interface port INT_A of the first slave 612 and the master 620, only the fourth slave 618 of the 4-diversity slave operates in the single mode . The master 620 receives the TS data at the fourth B interface port (INT_B) of the fourth slave 618. The master 620 operates the first slave 612 to the third slave 616 among the 4-diversity slaves in the diversity mode and transmits the first A interface port INT_A of the first slave 612 To receive the TS data.

8E, the first slave 612 operates in the single mode and the second slave 614 to the fourth slave 618 operate in the diversity mode. The master 620 is connected to the second slave 614 operating in the diversity mode from the second A interface port INT_A of the second slave 614 toward the first B interface port INT_B of the first slave 612, To be transmitted to the first slave 612. Then, the master 620 receives the TS data of each slave (the first slave 612 to the second slave 614).

FIG. 9 is a diagram showing the inversion of the interface ports at the time of 2-diversity operation according to the present embodiment.

9 shows the state of the interface port for diversity between the first slave 612 and the second slave 614 in the 2-diversity operation state in the time period during which the second slave 614 does not transmit data 1 is inverted by inverting the interface port of the slave 612, thereby enabling reverse access. For example, since the diversity data to be transmitted from the second slave 614 to the first slave 612 is made by a predetermined timing pattern (Timing Pattern), the first slave 612 and the second slave 614 The interface port control can be performed since the section in which the state of the interface bus is idle can be known.

Only when the interface between the first slave 612 and the second slaves 614 is idle the master 620 is connected to the second slave 614 using the first A interface port INT_A of the first slave 612, It is necessary to store the commands of the master 620 and to perform the stored instructions in the idle time period. In other words, as shown in FIG. 9, when the slave group 610 is operated in 2-diversity, the master 620 determines whether the first slave 612 and the second slave The interface port for diversity between the first slave 612 and the second slave 614 is accessed in the reverse direction by inverting the interface port of the first slave 612 during a time period during which data is not transmitted to the second slave 614.

10 is a diagram illustrating a 2-diversity and 4-diversity pin map supporting SPI and TSIF according to the present embodiment.

10 is a 2-Diversity or 4-Diversity pin map supporting SPI and Transport Stream Interface (TSIF), which is a quad I / O SPI bus with 4-bit data bits between slave chips . ≪ / RTI > 10, the input / output (I / O) pins are mapped in the same manner regardless of the interface mode and the position of the slave chip in the interfaces of the first slave 612 to the fourth slave 618 .

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

600: Multi-chip system 610: Slave group
612: Slave chip 0 614: Slave chip 1
616: Slave chip 2 618: Slave chip 3
620: Master chip

Claims (17)

delete A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and having a plurality of interface ports for each of the slaves via a diversity interface; And
(I / O) state of each of the slaves in the slave group by using the diversity interface,
Wherein the diversity interface comprises:
A interface port (INT_A) including A master interface and A slave interface; And
B interface port (INT_B) including B master interface and B slave interface
Master interface or the A-slave interface according to a control command of the master, and the B-interface port is connected to the B-master interface or the B-slave interface To the multi-chip system. 3. The method of claim 2,
The A interface port INT_A and the B interface port INT_B support at least one of a serial peripheral interface (SPI), an inter-integrated circuit (I2C), and a secure digital I / O (SDIO) Chip system. 3. The method of claim 2,
Wherein the master selects one of a master interface and a slave interface included in the diversity interface so that the master interface or the slave interface is switched, and the input / output (I / O) pin of the slave ) Is minimized. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master communicates with one of a master interface and a slave interface according to an operation mode of each of the slaves using the diversity interface, And the data bit width (Variable Bit Width) is variably selected. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master sets the A interface port INT_A and the B interface port INT_B included in the diversity interface after a reset command,
After setting the A interface port INT_A as a slave interface, the B interface port INT_B is set as a master interface or a slave interface,
Wherein the port state of the B interface port (INT_B) is set to a slave interface or a master interface by using the A interface port (INT_A). A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master indicates an initial state for RF or a baseband configuration register as the diversity interface when the slave group operates in two-diversity mode, When the interface type between the slaves operating in the 2-diversity is changed after the setting is completed,
Since access to the second slave (slave chip 1) becomes impossible using the A interface port INT_A of the first slave (slave chip 0) of the 2-diversity slave, the diversity path (Slave chip 0) to the first slave (the slave chip 0) in a time division idle period. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
(Slave chip 1) to access the internal register of the second slave (slave chip 1) when the slave group is operated in 2-diversity, (INT_B) is used to access the second slave among the slave operated in the 2-diversity. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master uses the B interface port (INT_B) of the slaves operating in the 2-diversity mode when the slave group operates in 2-diversity, The interface type of the multi-chip system is changed to the initial state. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein, when the slave group is operated in a 2-diversity mode, the 2 slaves operating in the 2-diversity mode are respectively in a single mode in order to implement a dual receiver function, Chip system. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein when the slave group is operated in a two-diversity mode, the master is configured to transmit, in a dual receiver state, an A interface port (INT_A) of the first slave (slave chip 0) (Transport Stream) data of a slave in which trouble has occurred to the B interface port (INT_B) of the second slave (slave chip 1), and the first TS of the first slave (slave chip 0) A interface port (INT_A) is used to receive the TS data. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master indicates an initial state for an RF or baseband configuration register when the slave group is operated in 4-diversity mode, and the interface type between the slaves is changed after the setting of the initial state is completed Occation,
Since the access to the remaining slaves becomes impossible using the first interface port INT_A of the first slave (slave chip 0) of the 4-diversity slave, the diversity path is set in the time- State register to the first slave (slave chip 0). A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein, when the slave group is operated in 4-diversity, when the master desires to access the internal register of one of the 4-diversity slaves, the 4th slave (slave chip 3 ) Accesses any one of the four-slave operated slaves using the B interface port (INT_B) of the multi-chip system. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Wherein the master uses the B interface port (INT_B) of the slaves operating in the 4-diversity when the slave group operates in 4-diversity, The interface type of the multi-chip system is changed to the initial state. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
Diversity mode, the master may allow the three slaves operating in the 4-diversity mode to operate in the diversity mode to implement the dual receiver function, and when the slave group operates in the 4-diversity mode, Chip slaves are operated in a single mode. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
When the slave group is operated in the 4-diversity mode, there is a problem in the interface throughput between the A interface port INT_A of the first slave (slave chip 0) and the master in the dual receiver state If so,
Only the fourth slave (slave chip 3) of the slave operated in the 4-diversity operates in the single mode and receives TS data to the B interface port (INT_B) of the fourth slave (slave chip 3) (Slave chip 0) to the third slave (slave chip 2) among the slaves operated in the city in the diversity mode and using the A interface port INT_A of the first slave (slave chip 0) And the TS data is received. A slave group communicating with two or more slaves transmitting and receiving a diversity signal in series and a diversity interface having a plurality of interface ports for each of the slaves; And
(I / O) state of each of the slaves in the slave group using the diversity interface
(Slave chip 0) and the second slave (slave chip 1) among the slave operated in the 2-diversity when the slave group is operated in 2-diversity. (Slave chip 0) is reversed in a time period during which data is not transmitted to the second slave (slave chip 1) through the interface port for diversity, thereby reversing the interface port of the first slave .

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