KR101815961B1 - SPI(Serial Peripheral Interface) interface device and communication method using thereof - Google Patents

SPI(Serial Peripheral Interface) interface device and communication method using thereof Download PDF

Info

Publication number
KR101815961B1
KR101815961B1 KR1020150179103A KR20150179103A KR101815961B1 KR 101815961 B1 KR101815961 B1 KR 101815961B1 KR 1020150179103 A KR1020150179103 A KR 1020150179103A KR 20150179103 A KR20150179103 A KR 20150179103A KR 101815961 B1 KR101815961 B1 KR 101815961B1
Authority
KR
South Korea
Prior art keywords
slave
transition point
time difference
selection signal
difference value
Prior art date
Application number
KR1020150179103A
Other languages
Korean (ko)
Other versions
KR20170071127A (en
Inventor
박재민
Original Assignee
현대오트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 현대오트론 주식회사 filed Critical 현대오트론 주식회사
Priority to KR1020150179103A priority Critical patent/KR101815961B1/en
Publication of KR20170071127A publication Critical patent/KR20170071127A/en
Application granted granted Critical
Publication of KR101815961B1 publication Critical patent/KR101815961B1/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

An SPI interface device and a communication method using the SPI interface device are provided. The SPI interface device includes a master control unit, a first slave driving unit connected to the master control unit through a SPI (Serial Peripheral Interface) method, and a second slave driving unit connected to the master control unit through an SPI method, Wherein the first slave driving unit and the second slave driving unit are connected to the master control unit by using a common slave selecting line, and the first slave driving unit is connected to the first slave driving unit and the second slave driving unit, And calculates a first time difference between a transition point of the first clock transmission signal applied to the driving unit and a transition point of the first slave selection signal applied to the first slave driving unit.

Description

SPI interface device and communication method using the same [0002] SPI (Serial Peripheral Interface) interface device and communication method using thereof [

The present invention relates to an SPI interface device and a communication method using the same. More specifically, the present invention relates to an SPI interface device that can reduce the complexity of a structure by including one slave select line instead of N slave select lines to configure N slave ICs, and a communication method using the SPI interface device .

SPI (Serial Peripheral Interface) is a kind of communication protocol that transmits data specific to an IC by performing data communication in a serial manner, and allows information of the IC to be known.

When a large number of slaves are used by using the SPI, a port of the main processor is used to control each of the slaves. In some cases, the main processor needs to be used more.

Also, the cost of the product may increase due to an increase in the number of ports or an increase in the number of processors.

Therefore, a more efficient SPI interface method and apparatus are required when a plurality of slave devices are used.

Korean Patent Publication No. 2010-0077708 (Published on July 8, 2010)

SUMMARY OF THE INVENTION An object of the present invention is to provide an SPI interface device in which the restriction of the number of slave IC supportable numbers according to the number of slave selection lines of a master IC is reduced and the structure of a communication circuit can be simplified.

Another object of the present invention is to provide a communication method using an SIP interface including an algorithm for performing SPI communication using the SPI interface device.

The technical problems to be solved by the present invention are not limited to the technical problems mentioned above, and other technical problems which are not mentioned can be clearly understood by the ordinary skilled in the art from the following description.

According to an aspect of the present invention, there is provided an SPI interface apparatus including a master controller, a first slave driver connected to the master controller through a serial peripheral interface (SPI) And a second slave driving unit connected to the master control unit through an SPI scheme and different from the first slave driving unit, wherein the first slave driving unit and the second slave driving unit are connected to the master control unit And the first slave driving unit calculates a first time difference between a transition point of a first clock transmission signal applied to the first slave driving unit and a transition point of a first slave selection signal applied to the first slave driving unit do.

In some embodiments of the present invention, the second slave driving unit may include a second slave driving unit configured to switch between a transition point of a second clock transmission signal applied to the second slave driving unit and a transition point of a second slave selecting signal applied to the second slave driving unit The second time difference can be calculated.

In some embodiments of the present invention, a predetermined time difference value may be stored in each of the first slave driver and the second slave driver.

In some embodiments of the present invention, the first time difference value stored in advance in the first slave drive unit and the second time difference value stored in advance in the second slave drive unit may be different from each other.

In some embodiments of the present invention, the master control unit may provide the first slave selection signal to the first slave driving unit and the second slave selection signal to the second slave driving unit.

In some embodiments of the present invention, the transition point of the first slave selection signal and the transition point of the second slave selection signal may be different from each other.

In some embodiments of the invention, the transition point of the first clock transmission signal and the transition point of the second clock transmission signal may be equal to each other.

According to another aspect of the present invention, there is provided an SPI interface apparatus including a master controller, a first slave driver connected to the master controller through an SPI scheme, a first slave driver coupled to the first slave driver, A first operation unit for calculating a first time difference value between a transition point of a clock transmission signal applied to a slave drive unit and a transition point of a slave selection signal, a second operation unit connected to the master control unit through an SPI scheme, And a second operation unit connected to the second slave driving unit and calculating a second time difference value between a transition point of a clock transmission signal applied to the second slave driving unit and a transition point of the slave selection signal .

In some embodiments of the present invention, the first slave driver and the second slave driver may be connected to the master controller using a common slave selection line.

In some embodiments of the present invention, the first calculation unit may determine whether the first slave drive unit is selected by comparing the previously stored time difference value with the first time difference value.

In some embodiments of the present invention, the second operation unit may determine whether to select the second slave drive unit by comparing the previously stored time difference value with the second time difference value.

In some embodiments of the present invention, the master control unit may provide a first slave selection signal to the first slave driving unit and a second slave selection signal to the second slave driving unit.

In some embodiments of the present invention, the transition point of the first slave selection signal and the transition point of the second slave selection signal may be different from each other.

According to an aspect of the present invention, there is provided a communication method using an SPI interface, the method including: providing a clock transmission signal and a slave selection signal from a master controller; receiving, by a plurality of slave drivers, Calculating a time difference value between a transition point of the slave selection signal and a transition point of the slave selection signal, the plurality of slave drivers comparing the time difference value stored in advance and the calculated time difference value, And performing an operation.

In some embodiments of the present invention, the master control unit and the plurality of slave driving units may be connected through an SPI scheme, and the master control unit and the plurality of slave driving units may be connected using a common slave selection line.

In some embodiments of the present invention, the time difference values stored in advance in each of the plurality of slave driving units may be different from each other.

According to the present invention as described above, a communication circuit using one slave selection line can be implemented regardless of the number of slave ICs using the SPI interface device. Thus, the restriction of the number of slave IC supportable numbers according to the number of slave selection lines of the master IC is reduced, the configuration of the communication circuit can be simplified, and the product cost can be reduced.

1 is a block diagram showing a connection between a master control unit and a slave driving unit using existing SPI communication.
2 is a block diagram illustrating a connection between a master control unit and a slave driving unit of the SPI interface apparatus according to an embodiment of the present invention.
3 is a timing diagram showing the transition point of the clock transmission signal and the transition point of the slave selection signal.
4 is a block diagram illustrating a connection between a master control unit and a slave drive unit of an SPI interface apparatus according to another embodiment of the present invention.
5 is a flowchart sequentially illustrating a communication method using an SPI interface according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms "comprises" and / or "made of" means that a component, step, operation, and / or element may be embodied in one or more other components, steps, operations, and / And does not exclude the presence or addition thereof.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a connection between a master control unit and a slave driving unit using existing SPI communication.

Referring to FIG. 1, when the number of slave drivers is N, a serial peripheral interface (SPI) structure including N slave select lines is shown. The SPI interface is a high-speed synchronous serial communication system with four communication lines, which is faster and simpler than an I2C that supports the same multi-slave communication.

Referring to FIG. 1, the SPI interface device includes a master controller 10 and a plurality of slave drivers 20, 30, and 40 connected through a SPI (Serial Peripheral Interface).

The master control unit 10 and the plurality of slave driving units 20, 30 and 40 each comprise four communication ports. The four communication ports include a clock transmission line SCK (SPI Clock) Slave select lines SS1 to SSn, a master in slave out (MISO) line for data transmission, and a master out slave in line (MOSI).

The slave selecting lines SS1 to SSn are connected to the lines of the slave driving units 20 to 30 in a one-to-one correspondence manner and the slave selecting lines SS1 to SSn are connected to the slave driving units 20, And activates each of the slave driving units 20, 30, and 40.

The conventional SPI structure is configured such that when there are N slave driving units 20, 30 and 40, N master slave selecting lines (or 30, 40) are selected for communication selection to the slave driving units 20, 30 and 40 in the master control unit 10 SS1 to SSn) are required, the number of slave selection ports of the master control unit increases as the number of slave driving units increases.

That is, if the number of the slave driving units is increased, the number of the slave selecting lines SS1 to SSn must be increased proportionally, and the manufacturing cost is increased.

In the general SPI interface configuration, the number of slave selection ports and signal lines is increased by N because the number ratio of the master control section and the slave driving section is 1: 1 or 1: N, but the number of the master control section and the slave driving sections Even if the ratio is 1: N, only four communication lines can be constructed.

2 is a block diagram illustrating a connection between a master control unit and a slave driving unit of the SPI interface apparatus according to an embodiment of the present invention. 3 is a timing diagram showing the transition point of the clock transmission signal and the transition point of the slave selection signal.

Referring to FIG. 2, the interface apparatus according to an embodiment of the present invention includes a plurality of slave drivers 200, 300, and 400 connected to the master controller 100 through a serial peripheral interface (SPI) scheme.

The master control unit 100 and the plurality of slave driving units 200, 300 and 400 each have four communication ports. The four communication ports include a clock transmission line SCK Clock, a slave select line (SS), a master in slave out line (MIS0) for data transmission, and a master out slave in line (MOSI). Here, the plurality of slave driving units 200, 300, and 400 are connected to the master control unit 100 using a common slave selecting line SS.

2, only one slave selection line SS is formed in the slave selection line SS regardless of the number of slaves, and the master control unit 100 and the plurality of slave driving units 200, 300, And a slave selection line SS are also connected in common.

Specifically, in the conventional SPI interface structure, if it is determined whether or not the individual slave selection lines connected to the respective slave driving units are activated to determine whether or not the communication bus is occupied, in the SPI interface structure according to the present invention, To the slave driving units 200, 300, and 400, respectively.

Referring to FIG. 3, each of the slave drivers 200, 300, and 400 uses predetermined timing information to determine a transition point of a clock transmission signal transmitted through a clock transmission line SCK, (SS-SCK) between transition points of the slave selection signal transmitted through the slave SS to determine whether the slave driver selected by the master control unit 100 is the slave.

Each of the slave driving units 200, 300, and 400 may calculate a time difference between the transition point of the clock transmission signal and the transition point of the slave selection signal to determine whether the slave driving unit 200 is the selected slave driving unit, And performs an operation in accordance with an operation signal of the control unit 100.

Specifically, for example, when using an SPI interface device at a 10 MHz rate, the maximum value of the time difference value T (SS-SCK) is 100 ns. When 10 slave driving units are used, the range of the time difference value T (SS-SCK) assigned to each slave driving unit is a value obtained by dividing the maximum value (100 ns) by 10, which is 10 ns. According to this, if the range of the calculated time difference value T (SS-SCK) is 0 to 10 ns, the first slave driver is selected. If the range of the time difference value T (SS-SCK) is 10 ns to 20 ns, The slave drive unit can be selected.

According to this method, if the range of the time difference value T (SS-SCK) is 20 ns to 30 ns, the third slave driver is selected and the range of the time difference value T (SS-SCK) , The tenth slave driver can be selected.

That is, the SPI interface device according to the present invention is connected to a master control unit 100 and a plurality of slave driving units 200, 300, and 400 via a common slave selection line SS, And may appear differently in the slave drivers 200, 300, and 400. The master control unit 100 provides a clock transmission signal to the plurality of slave driving units 200, 300 and 400 and provides a slave selecting signal whose transition point is changed to output a slave selecting signal to the slave driving units 200, (T (SS-SCK)) between the transition point and the transition point of the slave selection signal.

The SPI interface apparatus according to the present invention calculates the time difference value (T (SS-SCK)) between the transition point of the clock transmission signal and the transition point of the slave selection signal in each of the slave drivers 200, 300 and 400, (200, 300, 400).

Different time difference values T (SS-SCK) may be stored in advance in each of the plurality of slave drivers 200, 300 and 400, and a time difference value T (SS-SCK) It can be determined whether or not the selected slave drive unit is the selected slave drive unit.

4 is a block diagram illustrating a connection between a master control unit and a slave drive unit of an SPI interface apparatus according to another embodiment of the present invention. For the sake of convenience of description, description of portions substantially the same as those of the SPI interface apparatus according to the embodiment of the present invention will be omitted.

Referring to FIG. 4, the SPI interface apparatus according to another embodiment of the present invention includes a plurality of slave drivers 200, 300, and 400 connected to the master controller 100 through an SPI scheme, And a plurality of operation units 250, 350, and 450 connected to the plurality of operation units.

The master control unit 100 and the plurality of slave driving units 200, 300, and 400 are configured substantially the same as those described above.

Each of the plurality of operation units 250 350 and 450 receives a time difference value T (SS-T) between the transition point of the clock transmission signal transmitted to the corresponding slave drive unit 200, 300 or 400 and the transition point of the slave selection signal, SCK) can be calculated.

That is, the configuration of the module for calculating the time difference value T (SS-SCK) may be added in a separate configuration. At this time, different time difference values T (SS-SCK) may be stored in advance in the respective operation units 250, 350, and 450, and the time difference values T (SS-SCK) It is possible to determine the selected slave drive unit among the slave drive units 200, 300, and 400 connected to the respective operation units 250, 350, and 450.

5 is a flowchart sequentially illustrating a communication method using an SPI interface according to an embodiment of the present invention.

Referring to FIG. 5, a plurality of slave drivers 200, 300, and 400 are provided with a clock transmission signal and a slave selection signal from the master controller 100 (S101).

Subsequently, each of the slave driving units 200, 300, and 400 calculates a time difference value T (SS-SCK) between the transition point of the clock transmission signal and the transition point of the slave selection signal (S102).

Subsequently, it is determined whether the time difference value T (SS-SCK) calculated within the range of the time difference value T (SS-SCK) preset for each of the slave drivers 200, 300 and 400 is included (S103). Accordingly, the selected slave driving unit performs an appropriate operation according to the operation signal provided from the master control unit 100 (S104).

Since the ranges of the time difference values T (SS-SCK) previously set for the slave drivers 200, 300 and 400 are set to be different from each other, the slave driver can be selected according to the calculated time difference value T (SS-SCK) .

According to the present invention, the time difference value between the clock transmission signal transmitted through the clock transmission line (SCK) and the transition point of each slave selection signal transmitted through the slave selection line (SS) is calculated, It is possible to reduce the number of slave selection lines SS connecting the master control unit 100 and the plurality of slave driving units 200, 300 and 400 to one.

Thus, there is no restriction on the number of slave driving units that can be supported according to the number of slave selecting lines, and a single communication line related to the slave selecting line is used, so that the complexity in the circuit configuration can be reduced.

In addition, SPI communication can be efficiently performed while reducing manufacturing cost by reducing the number of ports and communication lines.

The steps of a method or algorithm described in connection with the embodiments of the invention may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of recording medium known in the art. An exemplary recording medium is coupled to a processor, which is capable of reading information from, and writing information to, the storage medium. Alternatively, the recording medium may be integral with the processor. The processor and the recording medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside within the user terminal. Alternatively, the processor and the recording medium may reside as discrete components in a user terminal.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

Claims (16)

A master control unit;
A first slave driver connected to the master controller through an SPI (Serial Peripheral Interface); And
And a second slave driver connected to the master controller through an SPI scheme and different from the first slave driver,
Wherein the first slave drive unit and the second slave drive unit are connected to the master control unit using a common slave select line,
The first slave driver calculates a first time difference between a transition point of a first clock transmission signal applied to the first slave driving unit and a transition point of a first slave selection signal applied to the first slave driving unit,
Wherein the second slave driving unit is configured to calculate a second time difference between a transition point of a second clock transmission signal applied to the second slave driving unit and a transition point of a second slave selection signal applied to the second slave driving unit, Interface device. delete The method according to claim 1,
Wherein the first slave driver and the second slave driver each store a preset time difference value. The method of claim 3,
Wherein the first time difference value stored in advance in the first slave drive unit and the second time difference value stored in advance in the second slave drive unit are different from each other. The method according to claim 1,
Wherein the master control section provides the first slave selection signal to the first slave drive section and provides the second slave selection signal to the second slave drive section. 6. The method of claim 5,
Wherein the transition point of the first slave selection signal and the transition point of the second slave selection signal are different from each other. The method according to claim 6,
Wherein the transition point of the first clock transmission signal and the transition point of the second clock transmission signal are identical to each other. A master control unit;
A first slave driver connected to the master controller through an SPI scheme;
A first operation unit connected to the first slave driving unit for calculating a first time difference value between a transition point of a clock transmission signal applied to the first slave driving unit and a transition point of a slave selection signal;
A second slave driver connected to the master controller through an SPI scheme and different from the first slave driver; And
And a second operation unit connected to the second slave driving unit and calculating a second time difference value between a transition point of the clock transmission signal applied to the second slave driving unit and a transition point of the slave selection signal. 9. The method of claim 8,
Wherein the first slave driver and the second slave driver are connected to the master controller using a common slave select line. 9. The method of claim 8,
Wherein the first operation unit determines whether the first slave drive unit is selected by comparing a time difference value stored in advance with the first time difference value. 11. The method of claim 10,
Wherein the second operation unit compares the previously stored time difference value with the second time difference value to determine whether to select the second slave drive unit. 9. The method of claim 8,
Wherein the master control section provides a first slave selection signal to the first slave drive section and provides a second slave selection signal to the second slave drive section. 13. The method of claim 12,
Wherein the transition point of the first slave selection signal and the transition point of the second slave selection signal are different from each other. Providing a clock transmission signal and a slave selection signal from the master control unit;
Calculating a time difference value between a transition point of the clock transmission signal and a transition point of the slave selection signal in a plurality of slave driving units;
Wherein the plurality of slave driving units compare the previously stored time difference value and the calculated time difference value, respectively; And
And performing an operation in a selected one of the plurality of slave driving units. 15. The method of claim 14,
Wherein the master control unit and the plurality of slave driving units are connected through an SPI scheme,
Wherein the master control unit and the plurality of slave driving units are connected using a common slave selection line. 15. The method of claim 14,
Wherein the time difference values stored in advance in the plurality of slave driving units are different from each other.
KR1020150179103A 2015-12-15 2015-12-15 SPI(Serial Peripheral Interface) interface device and communication method using thereof KR101815961B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150179103A KR101815961B1 (en) 2015-12-15 2015-12-15 SPI(Serial Peripheral Interface) interface device and communication method using thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150179103A KR101815961B1 (en) 2015-12-15 2015-12-15 SPI(Serial Peripheral Interface) interface device and communication method using thereof

Publications (2)

Publication Number Publication Date
KR20170071127A KR20170071127A (en) 2017-06-23
KR101815961B1 true KR101815961B1 (en) 2018-01-08

Family

ID=59283431

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150179103A KR101815961B1 (en) 2015-12-15 2015-12-15 SPI(Serial Peripheral Interface) interface device and communication method using thereof

Country Status (1)

Country Link
KR (1) KR101815961B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101967466B1 (en) * 2017-07-04 2019-04-09 현대오트론 주식회사 Spi monitoring device and method for determining mode operation of spi monitoring device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005141412A (en) 2003-11-05 2005-06-02 Hitachi Ltd Communication system, real time controller and information processing system
JP2005196486A (en) * 2004-01-07 2005-07-21 Hitachi Ltd Data communication device and controller using the same
KR101509423B1 (en) 2013-10-23 2015-04-07 (주)에프씨아이 Multi Chip System with Plurality of Interfaces Port
JP2015064853A (en) 2013-09-24 2015-04-09 エフシーアイ インク Multi-chip system and register setting method of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005141412A (en) 2003-11-05 2005-06-02 Hitachi Ltd Communication system, real time controller and information processing system
JP2005196486A (en) * 2004-01-07 2005-07-21 Hitachi Ltd Data communication device and controller using the same
JP2015064853A (en) 2013-09-24 2015-04-09 エフシーアイ インク Multi-chip system and register setting method of the same
KR101509423B1 (en) 2013-10-23 2015-04-07 (주)에프씨아이 Multi Chip System with Plurality of Interfaces Port

Also Published As

Publication number Publication date
KR20170071127A (en) 2017-06-23

Similar Documents

Publication Publication Date Title
US10642769B2 (en) Serial peripheral interface daisy chain mode system and apparatus
KR102365520B1 (en) Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
US8631179B1 (en) System and method for automatically assigning bus addresses to slave devices
US8433838B2 (en) Remote multiplexing devices on a serial peripheral interface bus
US9824055B2 (en) Control method applied to operating-mode finite-state-machine and computer readable media
CN108920173B (en) Method, chip and communication system for configuring equalization time
KR100696111B1 (en) Communication system
TWI671638B (en) Bus system
CN109376103B (en) Method, chip and communication system for rapid equalization
KR20230144996A (en) Semiconductor apparatus and system perfoming calibration operation
KR102007368B1 (en) PCI express switch and computer system using the same
US20080270654A1 (en) Bus System for Selectively Controlling a Plurality of Identical Slave Circuits Connected to the Bus and Method Therefore
EP3859542A1 (en) Spi broadcast mode
WO2016095435A1 (en) Multi-chip cascading method, chip and device, and storage medium
JP4662723B2 (en) Method and system for assigning multiple sources to multiple channels
US10884956B2 (en) I/O bus shared memory system
US20160224488A1 (en) Bidirectional communication method between a master terminal and a slave terminal on a single transmission line
US9411771B2 (en) Server system for switching master and slave devices
KR101815961B1 (en) SPI(Serial Peripheral Interface) interface device and communication method using thereof
US20150161075A1 (en) I2c router system
US20210141755A1 (en) Bridge chip with function of expanding external devices and associated expansion method
CN111352879A (en) Same-address slave machine expansion circuit and method based on multi-path gating
US8319538B2 (en) Semiconductor device
WO2017112225A1 (en) Soc fabric extensions for configurable memory maps through memory range screens and selectable address flattening
JP4193746B2 (en) Matrix bus connection system

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant