KR101503070B1 - Organic Light Emitting Diode Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light emitting diode (OLED) display device for preventing local heat generation due to panel breakage.

The organic light emitting diode display device includes a display panel having a plurality of gate signal lines and a plurality of data signal lines intersected and having a plurality of pixels formed in each of the intersection regions; A first signal applying unit for generating a first power control signal; A power supply unit supplying a high potential driving voltage and a low potential driving voltage to the pixels in response to the first power control signal; A gate driver for supplying a gate drive pulse to the gate signal lines; And a second signal application unit for monitoring the gate drive pulse and generating a second power supply control signal based on the monitoring result; If the gate driving pulse is not monitored in a state where the driving voltages are supplied to the pixels, the second signal application unit controls the power supply unit using the second power supply control signal, And blocks any one of the driving voltage and the low-potential driving voltage.

Description

[0001] The present invention relates to an organic light emitting diode (OLED) display,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display device, and more particularly, to an organic light emitting diode display device that prevents local heat generation due to panel damage.

2. Description of the Related Art In recent years, various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such a flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (hereinafter referred to as "PTd"), And a light emitting device (Electroluminescence Device).

Since PTD is simple in structure and manufacturing process, it is attracting attention as a display device that is most advantageous for large screen size but large screen size, but it has a disadvantage of low luminous efficiency, low luminance and high power consumption. Though TFT LCD, to which a thin film transistor (hereinafter referred to as "TFT") is applied as a switching device, is the most widely used flat panel display device, it is a non-luminous device and thus has a narrow viewing angle and low response speed. On the other hand, the electroluminescent device is divided into an inorganic light emitting diode display device and an organic light emitting diode display device according to the material of the light emitting layer. In particular, the organic light emitting diode display device uses self light emitting devices that emit self- Brightness and viewing angle are large.

The organic light emitting diode display device has an organic light emitting diode as shown in FIG. The organic light emitting diode has organic compound layers (HIL, HTL, EML, ETL, EIL) formed between the anode electrode and the cathode electrode.

The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL).

When a driving voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons, Thereby generating visible light.

The organic light emitting diode display device arranges the pixels including the organic light emitting diode in a matrix form and controls the brightness of the pixels selected by the scan pulse according to the gray level of the video data. To this end, the organic light emitting diode display selectively turns on the TFT, which is an active element, to select a pixel, and maintains the light emission of the pixel with the voltage held in the storage capacitor.

In such an organic light emitting diode display device, driving voltages (high potential driving voltage, low potential driving voltage) applied to the pixels are generated in a power IC (Integrated Circuit), and the power IC is controlled by a power control signal from the driver IC Its operation is controlled. However, even if a defect such as a panel breakage occurs in the organic light emitting diode display device, the display device may partially emit light due to normal operation of the driver IC. In other words, even if the panel breakage occurs, if the operation state of the driver IC is normal, the driver IC operates the power IC to apply the driving voltages to the pixels in the panel, do. Thus, in the abnormal driving state due to panel breakage or the like, if only the portion of the panel without any breakage is continuously emitted, there is a high possibility that a safety accident due to local burning will occur.

However, the conventional organic light emitting diode display device is not equipped with means for monitoring panel breakage or the like and for blocking local light emission in an abnormal state, so that the safety accident can not be prevented in advance.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an organic light emitting diode display device capable of blocking local light emission of a display panel in a non-steady state by monitoring panel breakage or the like.

According to an aspect of the present invention, there is provided an organic light emitting diode display device including: a display panel having a plurality of gate signal lines and a plurality of data signal lines intersecting each other and having a plurality of pixels formed in each of the intersection regions; A first signal applying unit for generating a first power control signal; A power supply unit supplying a high potential driving voltage and a low potential driving voltage to the pixels in response to the first power control signal; A gate driver for supplying a gate drive pulse to the gate signal lines; And a second signal application unit for monitoring the gate drive pulse and generating a second power supply control signal based on the monitoring result; If the gate driving pulse is not monitored in a state where the driving voltages are supplied to the pixels, the second signal application unit controls the power supply unit using the second power supply control signal, And blocks any one of the driving voltage and the low-potential driving voltage.

And a step-down level shifter for lowering the level of the gate driving pulse supplied from the gate driver and supplying the level to the second signal applying unit.

A source driver for driving the data signal lines; a driver IC integrated with a timing controller for controlling an operation timing of the gate driver and the source driver; And a system for supplying a timing signal to the timing controller together with digital video data; The step-down level shifter is mounted on a flexible printed circuit for signal transmission between the system and the driver IC, or on a system board on which the system is mounted.

The first signal applying unit is embedded in the timing controller, and the second signal applying unit is embedded in the system.

A source driver for driving the data signal lines; a driver IC integrated with a timing controller for controlling an operation timing of the gate driver and the source driver; And a system for supplying a timing signal to the timing controller together with digital video data; The step-down level shifter is included in the timing controller.

The first signal applying unit and the second signal applying unit are embedded in the timing controller.

Wherein the gate driver includes a scan driver and an emission driver; The gate driving pulse includes a scan pulse generated from the scan driver and an emission pulse generated from the emission driver.

The scan driver and the emission driver each comprising a plurality of stages; The monitored scan pulse and the emission pulse are respectively generated from the last stage of the stages.

INDUSTRIAL APPLICABILITY The organic light emitting diode display according to the present invention can easily detect whether a defect such as breakage of a display panel occurs by continuously monitoring the scan pulse from the scan driver or the emission pulse from the emission driver. According to the detection result, the power IC is controlled to block any one of the high-potential driving voltage and the low-potential driving voltage supplied to the pixels, thereby preventing the partial light emission of the display panel in the non- The accident can be prevented in advance.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 2 to 5. FIG.

[First Embodiment]

2 is a block diagram illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

Referring to FIG. 2, the organic light emitting diode display device according to the first embodiment of the present invention includes a display panel 10, a step-down level shifter 20, a system 25, and a power IC 30. The driver IC 14 is mounted on the non-display area of the display panel 10 by a COG (Chip On Glass) method and the scan driver 16a and the emission driver 16b are formed by a GIP (Gate In Panel) method .

A plurality of data lines DL, a plurality of scan lines GL and a plurality of emission lines EL are intersected with each other in the effective display region of the display panel 10, Are arranged in a matrix form. Each of the pixels 12 typically comprises an organic light emitting diode, a driving TFF, a plurality of switch TFTs, and a storage capacitor.

For example, as shown in FIG. 2, each of the pixels 12 emits light by a current flowing between one side supplied with the high potential driving voltage Vdd and the other side supplied with the low potential driving voltage Vss In order to sense the threshold voltages of the driving TFT DT and the driving TFT DT that control the amount of current flowing in the organic light emitting diode OLED according to the organic light emitting diode OLED and its own gate-source voltage difference Vgs, A first switch TFT SW1 connected between the first node n1 and the third node n3 for diode connection of the drive TFT DT and a second switch TFT SW2 connected between the data line DL and the second node n2 A third switch TFT SW3 for switching the current path between the reference voltage source Vref and the second node n2, a third node n3 and a third switch TFT SW3 for switching the current path between the reference voltage source Vref and the second node n2, A fourth switch TFT SW4 for switching the current path between the organic light emitting diodes (OLED), and a fourth switch TFT SW4 for switching between the first node n1 and the second node n2 Includes a storage capacitor (Cst). The driving TFT DT and the switch TFTs SW1 to SW4 are implemented by a P-type metal-oxide semiconductor field effect transistor (MOSFET). The semiconductor layer of the driver TFT (DT) includes a polysilicon layer (Poli Silicon). The operation of the pixel 12 will now be described with reference to FIG. During the data writing period Td, the scan pulse SP is generated at a low logic level to turn on the first and second switch TFTs SW1 and SW2, and the emission pulse Te is generated at the high logic level 3 and the fourth switch TFTs (SW3, SW4) are turned off. Accordingly, the first node n1 is maintained at the first voltage level at which the threshold voltage of the driving TFT DT is subtracted from the high potential driving voltage, and the second node n2 is maintained at the data voltage Vdata (Vdata) level Lt; / RTI > Subsequently, during the light emission period Te, the scan pulse SP is inverted to a high logic level to turn off the first and second switch TFTs SW1 and SW2, and the emission pulse Te is generated at a low logic level The third and fourth switch TFTs SW3 and SW4 are turned on. Thus, the potential of the second node n2 is lowered from the data voltage Vdata (Vdata) to the reference voltage level, and the potential of the first node n1 is also lowered by the first voltage level To a second voltage level. Since the second voltage level includes a threshold voltage variation of the driving TFT DT, the driving TFT DT applies a driving current to the organic light emitting diode OLED regardless of the threshold voltage variation, . Since the structure and operation of the pixel 12 described above are merely examples, it is needless to say that the pixel 12 of the present invention can be replaced with another pixel structure known in the art.

The driver IC 14 is mounted on the display panel 10 in a COG (Chip On Glass) manner. The driver IC 14 is integrated including a source driver 14b for driving the data lines DL and a timing controller 14a for controlling the operation timing of the drivers 14b, 16a and 16b . The driver IC 14 may further include a level shifter (not shown) for generating the gate high voltage VGH and the gate positive voltage VGL and supplying the same to the scan driver 16a and the emission driver 16b . The gate high voltage VGH and the gate low voltage VGL generated through the level shifter have a voltage level suitable for driving the TFTs in the pixel 11. [

The timing controller 14a controls the timing of operation of the source driver 14b based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK and a data enable signal DE A control signal GDC for controlling the operation timing of the scan driver 16a and a control signal EDC for controlling the operation timing of the emission driver 16b are generated . The control signal DDC for controlling the operation timing of the source driver 14b is supplied to the source driver 14b based on the rising or falling edge of the source sampling clock SSC A source output enable signal SOE indicating the output of the source driver 14b, and the like. The control signal GDC for controlling the operation timing of the scan driver 16a includes a gate start pulse GSP indicating a start horizontal line at which the scan starts in one vertical period in which one screen is displayed, A gate shift clock signal GSC generated with a pulse width corresponding to the ON period of the TFT as a timing control signal for sequentially shifting the gate start pulse GSP inputted to the shift register, And a gate output enable signal GOE for indicating the output of the gate driver. The control signal EDC for controlling the operation timing of the emission driver 16b includes an emission start pulse ESP, an emission-shift clock signal ESC, an emission output enable signal EOE, and the like . The timing controller 14a converts the digital video data RGB from the system 25 to the resolution of the display panel 10 and supplies it to the source driver 14b. The timing controller 14a also generates a first power control signal PCS1 to control the output of the power IC 30. [ The first power control signal PCS1 is generated at the first logic level when there is no operation by the user for a predetermined time and blocks the driving voltage applied to the pixels 12 in the display panel 10, (Power save Mode), and when a user operates the display device 10 within a predetermined time, the second logic level is generated and displayed by continuously applying the driving voltage to the pixels 12 in the display panel 10 Thereby causing the panel 10 to be driven in the normal mode.

The source driver 14b converts the digital video data RGB into a data voltage Vdata in synchronization with the control signal DDC of the timing controller 14a and supplies the digital video data RGB to the data lines DL.

The scan driver 16a is composed of a shift register array formed on a non-display region of the display panel 10 through the same process as the TFTs in the pixel 12 in a GIP (Gate In Panel) manner. The scan driver 16a sequentially shifts the gate high voltage VGH and the gate low voltage VGL from the level shifter in synchronization with the control signal GDC of the timing controller 14a to generate the scan pulse SP . Then, by sequentially supplying the scan pulse (SP) to the scan lines (GL), a horizontal line to which the data voltage (Vdata) is supplied is selected. To this end, the shift register array constituting the scan driver 16a has a plurality of stages connected in a dependent manner. The last stage of the scan driver 16a supplies the scan pulse SP to the scan line GL corresponding to the scan driver 16a and the scan pulse SP as the monitoring scan pulse MSP, (20).

The emission driver 16b is composed of a shift register array formed on the non-display area of the display panel 10 through the same process as the TFTs in the pixel 12 in the GIP (Gate In Panel) method. The emission driver 16b sequentially shifts the gate high voltage VGH and the gate low voltage VGL from the level shifter in synchronization with the control signal EDC of the timing controller 14a to generate the emission pulse EP Occurs. Then, by sequentially supplying the emission pulse EP to the emission lines EL, the horizontal line to which the emission pulse EP is supplied is selected. To this end, the shift register array constituting the emission driver 16b has a plurality of stages which are connected in a dependent manner. The last stage of the emission driver 16b supplies the emission pulse EP to the emission line EL corresponding to the emission pulse and the emission pulse EP for monitoring, To the step-down level shifter 20 as shown in FIG.

The step-down level shifter 20 receives the monitoring scan pulse MSP from the scan driver 16a or the monitoring pulse MEP for monitoring from the emission driver 16b and outputs the signals MSP / Down to a TTL (Transistor-Transisotr Logic) level that can be processed by digital logic to generate a level-down scan pulse (LSP) and a level-down emission pulse (LEP). This step-down level shifter 20 may be mounted on a flexible printed circuit (FPC) for signal transmission between the system 25 and the driver IC 14, (Not shown) on which the semiconductor chip 25 is mounted.

The system 25 supplies digital video data RGB and timing signals H.Vsync, DE, DCLK to the timing controller 14a. The system 25 also monitors the level down scan pulse LSP or the level down emission pulse LEP from the step down level shifter 20 and supplies it to the power IC 30 And generates the second power control request (PCS2) at different logic levels. The second power control request PCS2 is generated at the first logic level when the level down scan pulse LSP or the level down emission pulse LEP is monitored as shown in FIG. 4, while the level down scan pulse LSP or the level If the down-pulse (LEP) is not monitored, it is generated at the second logic level. Here, the fact that the level down scan pulse LSP or the level down emission pulse LEP is not monitored means that a defect such as breakage has occurred in the display panel.

The power IC 30 generates a high potential driving voltage Vdd and a low potential driving voltage Vss suitable for driving the pixels 12 using an operation power supplied from the outside. To this end, the power IC 30 includes a DC-DC converter for converting a low level DC input voltage to a high level DC output voltage. The supply of the high potential driving voltage Vdd and the low potential driving voltage Vss to the pixels 12 is cut off under the power save mode while the supply to the pixels 12 is allowed under the normal mode. However, even when the display panel 10 is operating in the normal mode, depending on the logic level of the second power supply control signal PCS2 supplied from the system 25, the high level drive voltage Vdd and the low level drive voltage Vss Is blocked from being supplied to the pixels 12. In other words, under the normal mode in which the high-potential driving voltage Vdd and the low-potential driving voltage Vss are normally supplied as shown in FIG. 4, the power IC 30 outputs the second logic Level driving voltage Vdd or the low-potential driving voltage Vss is prevented from being supplied to the pixels 12 when the second power control signal PCS2 of the level is inputted. As a result, the local light emission of the display panel 10 is blocked in the non-steady state.

[Second Embodiment]

5 is a block diagram illustrating an organic light emitting diode display device according to a second embodiment of the present invention.

5, an organic light emitting diode display device according to a second embodiment of the present invention includes a display panel 110, a step-down level shifter 120, a system 125, and a power IC 130. A driver IC 114 is mounted on a non-display area of the display panel 10 by a COG (Chip On Glass) method and a scan driver 116a and an emission driver 116b are formed on a GIP (Gate In Panel) .

In the organic light emitting diode display device according to the second embodiment of the present invention, the mounting position of the step-down level shifter 120, the level-down scan pulse LSP or the level down emission pulse LEP are monitored, Only the main body generating the second power control signal PCS2 is different from the organic light emitting diode display device according to the first embodiment. That is, in the organic light emitting diode display device according to the second embodiment, the step-down level shifter 120 is included in the driver IC 114 and the main power generation source of the monitoring and second power control signal PCS2 is included in the timing controller 114a. to be. Other than this, the organic light emitting diode display device is substantially the same as the organic light emitting diode display device according to the first embodiment, and a detailed description thereof will be omitted.

As described above, the organic light emitting diode display according to the present invention continuously monitors the emission pulse from the scan driver or the emission driver from the scan driver to easily detect whether a defect such as breakage of the display panel occurs or not. have. According to the detection result, the power IC is controlled to block any one of the high-potential driving voltage and the low-potential driving voltage supplied to the pixels, thereby preventing the partial light emission of the display panel in the non- The accident can be prevented in advance.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining the principle of light emission of a general organic light emitting diode display device. FIG.

2 is a block diagram illustrating an organic light emitting diode display device according to a first embodiment of the present invention.

3 is a timing diagram of a scan pulse and an emission pulse applied to the pixel of FIG.

4 is a timing diagram showing whether the supply of driving voltage is controlled by the second power control signal.

5 is a block diagram showing an organic light emitting diode display device according to a second embodiment of the present invention.

Description of the Related Art

10, 110: display panel 12, 112: pixel

14,114: Driver IC 14a, 114a: Timing controller

14b, 114b: source driver 16a, 116a: scan driver

16b, 116b: Emission driver 20, 120: Step down level shifter

25,125: System 30,130: Power IC

Claims (8)

A display panel having a plurality of gate signal lines and a plurality of data signal lines intersected and having a plurality of pixels formed in each of the crossing areas; A first signal applying unit for generating a first power control signal; A power supply unit supplying a high potential driving voltage and a low potential driving voltage to the pixels in response to the first power control signal; A gate driver for supplying a gate drive pulse to the gate signal lines; A step-down level shifter for lowering a level of the gate drive pulse supplied from the gate driver to a transistor-transistor level (TTL) level; And And a second signal application unit for monitoring a gate drive pulse level-down in the step-down level shifter and generating a second power supply control signal based on the monitoring result; If the gate driving pulse is not monitored in a state where the driving voltages are supplied to the pixels, the second signal application unit controls the power supply unit through the second power supply control signal, Wherein the organic light emitting diode display device comprises: delete The method according to claim 1, A source driver for driving the data signal lines; a driver IC integrated with a timing controller for controlling an operation timing of the gate driver and the source driver; And Further comprising: a system for supplying a timing signal to the timing controller together with digital video data; Wherein the step-down level shifter is mounted on a flexible printed circuit for signal transmission between the system and the driver IC, or on a system board on which the system is mounted. The method of claim 3, Wherein the first signal applying unit is embedded in the timing controller and the second signal applying unit is embedded in the system. The method according to claim 1, A source driver for driving the data signal lines; a driver IC integrated with a timing controller for controlling an operation timing of the gate driver and the source driver; And Further comprising: a system for supplying a timing signal to the timing controller together with digital video data; And the step-down level shifter is included in the timing controller. 6. The method of claim 5, Wherein the first signal applying unit and the second signal applying unit are incorporated in the timing controller. The method according to claim 1, Wherein the gate driver includes a scan driver and an emission driver; Wherein the gate drive pulse includes a scan pulse generated from the scan driver and an emission pulse generated from the emission driver. 8. The method of claim 7, The scan driver and the emission driver each comprising a plurality of stages; Wherein the monitored scan pulse and the emission pulse are generated from a last one of the stages, respectively.

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