KR101485908B1 - Structure and Device fabrication method of high temperature Epitaxial layer growth on hetero substrate - Google Patents

Abstract

The method of manufacturing a heterogeneous substrate of the present invention includes the steps of growing an interlayer on top of a base substrate, forming a top layer on the interlayer, growing a low-temperature buffer layer on the top layer, (III-Nitride) epitaxial layer of the base layer and a portion of the interlayer where the interlayer is in fluid contact with the base substrate during epitaxial growth, reacts with the base substrate to form an interlayer between the base substrate and the interlayer Lt; RTI ID = 0.0 > intermixing < / RTI > According to the present invention, when the temperature is raised to grow the epitaxial layer at a high temperature, the interlayer becomes fluid and the epitaxial layer, which is finally grown by intermixing this portion with the base substrate, It has a high-quality characteristic that is advantageous for a large area which is not influenced by a constant.

Description

Technical Field [0001] The present invention relates to a structure for growing a high-temperature epitaxial layer on a hetero-

The present invention relates to a structure and a method for forming a III-nitride epitaxial layer on a semiconductor substrate by using the mobility characteristic of an interlayer, and more particularly, to a structure and a method for forming a III- Interlayer is formed by diffusion reaction between the interlayer and the semiconductor substrate during the epitaxial process of the epitaxial layer, thereby forming a high-quality defect-free thin film regardless of the lattice mismatch and the thermal expansion coefficient of the semiconductor substrate and the epi- And on the other hand by interposing a top layer between the interlayers and the epi-layer, the epitaxial layer and the interlayer can be mixed and diffused during the epitaxial process of the epi-layer And a method of manufacturing the same.

Recently, the fabrication of power semiconductor optical devices, RF devices and sensors using III-nitride epitaxial layers has been expanded. However, attempts to improve performance and increase productivity are becoming a major concern. The reason for this is that when III-nitride is grown on a substrate such as sapphire, silicon, or silicon carbide (SiC), there is a problem of dependency on electric conductivity or a problem caused by a high density of crystal defects Or the diameter is so small that productivity is so low that it lacks economic value.

For example, applications for manufacturing Red-Green-Blue, UV, and White light emitting devices using GaN-based III nitride epitaxial layers have been greatly expanded. A GaN-based light emitting diode with a textured indium tin oxide transparent layer (hereinafter referred to as " GaN-based light emitting diode " (III-Nitride (Al2O3) powder) is added to the sapphire, as in the case of Al2O3-coated Al2O3 powder, Appl. Phys. Lett. Vol. 94, No. 16, pp. 161107-1 ) Are mainly grown and used. Here, in order to increase the luminous efficiency, various techniques using a nanoparticle or a substrate to be patterned are used.

In recent years, devices such as Schottky barrier diodes, HEMTs and metal oxide semiconductor field effect transistors (MOSFETs) have been researched and developed as electronic devices, and some technologies have been commercialized . Recently, the current control slope of switching is rapidly controlled from dI / dt to 100 A / us as the operating speed of the power control becomes higher as well as the voltage and power of the power control. Thus, overvoltage and power loss And the problem of ensuring reliability at high voltage is serious. Particularly, the leakage current flowing at the interfaces or surfaces of the III-nitride layer (SKH, KH Shim, JW Yang, "Reduced gate leakage current in AlGaN / GaN HEMT by oxygen passivation of AlGaN surface, The leakage current flow or the change in the threshold voltage due to the serious surface and interface defects is a serious problem (see, for example, Wang et al., Vol. 44, No. 18, Aug., 2008 , As well as ensuring the immunity and stability to EOS / ESD is a very important issue.

In modern times, there is a great need for countermeasures to simultaneously expand the limitations of high-speed operation and withstand voltage characteristics provided by silicon semiconductors in power semiconductor devices. In spite of the fact that product development for FET devices has become easier in recent years, device performance still needs to be improved in terms of operation speed, power consumption, over-voltage, reliability, and power driving.

Therefore, a technology for a high-power high-voltage device using a III-nitride semiconductor such as GaN having a high heat-resistant high withstand voltage characteristic is attracting attention. However, in terms of long-term reliability of devices, the role of power semiconductors mainly focusing on silicon is required. In other words, silicon-based advantages can be exploited to overcome static and thermal-electrical instabilities in GaN-based FETs with high-speed and high-voltage characteristics.

As described above, a GaN-based device is mounted on a silicon substrate and integrated with a silicon device, thereby achieving a great improvement in performance, productivity, and reliability. To do this, however, a good crystalline III-nitride epilayer must be formed on the silicon substrate.

However, existing techniques do not solve problems such as defects, cracks, and physical bending of the substrate caused by the lattice mismatch and the thermal expansion coefficient discrepancies in the III-nitride epitaxial layer.

FIGS. 1A to 1F show the state of related arts related to the formation of a conventional III-nitride epitaxial layer in patents and papers.

1A is a schematic cross-sectional view of a nitrided thin film containing Al (US Pat. No. 7,023,025 B2, Apr. 4, 2006, "Crystal Growth Method of Nitride Semiconductor," Johngeon Shin, LG Electronics Inc.) Al as a buffer layer 22 To improve the electrical characteristics and crystallinity by a method of forming a nitrided semiconductor epitaxial layer 23 by using a silicon nitride film. A nitride oxide buffer layer 22 is formed on the metal oxide film 31, and then a nitride semiconductor epitaxial layer 23 is grown thereon. Sapphire and GaInN are used for the substrate 20 and the buffer layer 21, respectively. A method using a sapphire substrate 20 or a method using a GaInN buffer layer 21 has been tried by other researchers in the past.

FIG. 1B is a graph showing the results of the measurement of the temperature of a sample (Korean Patent No. 10-046505, December 2, 2004, Baek Moon Cheol, Kyu Hwan Kim, Han Kyung Pyung, Kim Jung Yoon, Son Young Joon Kim Tae Yeop, Jo Kyung Ik, Hong Sung Un, Yun Sun Kil et. And a group III nitride semiconductor epitaxial layer which is a light emitting material of blue and ultraviolet rays is formed on the silicon substrate 10. AlN is deposited on the silicon substrate 10 and the surface is computed. Then, the GaN epitaxial layer 12 is grown on the AlN thin film 11 protected by the oxide film 11a by HVPE (Hydride Vapor Pressure Epitaxy). (SU Hong, MC Paek, GP Han, YJ Sohn, TY Kim, KI Cho, KH Shim and SG Yoon, "Characterization of Aluminum Nitride Thin Films on Silicon Substrates Grown by Plasma Assisted Molecular Beam Epitaxy, Jpn. (2002)), a buffer layer of AlN is grown on a silicon substrate at a low temperature using a PAMBE method. High quality AlN can be formed on silicon with PAMBE, but it is inconvenient because PAMBE and MOCVD or HVPE are repeatedly used.

(US Pat. No. 7,825,006 B2, Nov. 2, 2010, "Lift-off Process for GaN Films Formed on SiC Substrates and Devices Fabricated Using the Method," by Shuji Nakamura, Steven DenBarrs, Cree, Inc.). A lift-off layer 46 is formed between the SiC substrate 42 and the element 48 of the III-nitride system by using the SiC substrate 42 and the flip chip flip-chip structure is applied to fabricate optical devices with high light emission efficiency. InGaN, AlInGaN and AlInGaAs are used as the lift-off layer 46 and photochemical etching or laser lift-off is performed for the purpose of removing the lift-off layer 46. In this case, Laser lift-off (LLO).

(R. Korbutowicz, E. Dumiszewska, J. Prazmowska, "Thick GaN Layers on Sapphire with Various Buffer Layers," Cryst. Res. Technol. 42, No. 12, pp. 1297-1301 (2007)). A composite substrate is formed on a sapphire substrate by MOVPE (Metal-Oxide Vapor Phase Epitaxy) method, and then a GaN layer is formed thereon by the HVPE method. Three kinds of AlN, GaN / AlN and GaN are grown on sapphire substrate by MOVPE method and used as a composite substrate. Then, GaN is grown on the composite substrate to a thickness of 22-66 μm, which is the most crystalline in the GaN-on-Sapphire composite substrate. It is a study on the effect of different materials on the crystallinity as a result of studies on structures that have been widely known and used in the past.

Fig. 1e is a cross-sectional view of a GaN on Si-on-porous-Silicon Substrates, " Status Solidi C " , No. 7-8, pp. 2049-2051 (2010)). Growth of GaN on porous silicon results in a poor GaN film because migration is severe and pits are generated significantly. Therefore, a GaN epitaxial layer having excellent crystallinity can be grown by using a silicon epitaxial (Si-epi) layer grown on porous silicon. No new voids are formed between AlN and porous silicon. However, there remains a technical problem that it is difficult to completely remove the voids in the original porous silicon (Si) and the minute pinholes on the surface.

1F is a schematic diagram of a method of manufacturing a semiconductor device according to the present invention (SA Kukushikin, AV Osipov, VN Bessolov, BK Medvedev, VK Nevolin, KA Tcarik, "Substrates for Epitaxy of Gallium Nitride: New Materials and Techniques," Rev. Adv. 1-32 (2008)). This is a review paper on the technology for growing GaN on a semiconductor substrate. Ultrathin films of SiC are formed on the silicon substrate to minimize the elastic deformation and the dislocation of GaN. Gas-source molecular beam epitaxy (GSMBE), radio-frequency MBE (RF-MBE), metal-oxide chemical vapor deposition (MOCVD), and HVPE are used for epitaxial growth. GaN / AlN / Si (111), GaN / SiC / Si (100), GaN / ZnO / Si (001), GaN / InGaN / Si (111) The results of the structure of AlN / GaN / Si3N4 / Si (111) are reviewed.

As described above, the prior arts are papers and patents on the known III-nitride epitaxial structure. Si, sapphire, ZnO, and SiC are the most used substrates in the prior art, and the problems of the GaN-based III-nitride semiconductor devices are inherent, The development of new device structures and fabrication techniques that improve thermal and electrical performance is an important technical issue.

Accordingly, the present invention provides a new epitaxial structure and a fabrication method for solving the above problems by inserting a heavily doped SiGe-based semiconductor layer into an interlayer.

In addition, the present invention relates to a SiGe-based epitaxial layer grown at a low temperature, wherein a crystal defect is concentrated to a SiGe-based epitaxial layer while severely relaxing stress at a high temperature for growing a III- To provide an epitaxial structure and a manufacturing method thereof.

Typically, silicon semiconductor devices operate with the limitation of figure-of-merit (FOM) that the (breakdown voltage x operating speed) maintains a generally constant value. Therefore, when the breakdown voltage is increased to increase the breakdown voltage, the breakdown voltage decreases and the breakdown voltage is used to trade-off the breakdown voltage and the breakdown voltage. In order to overcome the physical limitations of such silicon semiconductors, it is necessary to change the structure of the device or to employ a GaN-based material having different characteristics as a material.

Therefore, GaN-based FET devices are being proposed to replace silicon semiconductor power devices or to apply them to higher specifications. However, crystal defects are usually left in the active layer in a GaN-based semiconductor device, which is a difficulty in securing thermal-electrical reliability. As a countermeasure against such a problem, a method of attaching and assembling an element for protecting the FET to the outside is used, but a further improved technology is required because of its large size and complicated shape.

In FIG. 2, the lattice mismatch applied to the III-nitride epitaxial layer in the III-nitride-on-Si structure is -17%, the thermal expansion coefficient is 57%. Therefore, in epitaxial growth, crystal defects such as dislocations occur at a high rate of 108-1010 cm-2 in the GaN epitaxial layer, and tensile stress is induced to deform the wafer in a concave shape. Also, after the epitaxial growth is completed, a crack is generated due to a difference in thermal expansion coefficient (TEC) during the process of lowering the temperature to room temperature.

This physically modified III-nitride epilayer is a key issue that provides a critical impossibility to fabricate a precise semiconductor device thereon. In addition, some III-nitride epilayers and silicon substrates are also rapidly destroyed by some external physical impact.

Therefore, the relaxation of the strain due to the lattice mismatch between the silicon substrate and the III-nitride epitaxial layer by ~ 17% and the strain due to the mismatch of the thermal expansion coefficient, A technology that can accommodate the physical transformation of the In order to compensate for these weaknesses, a thick silicon substrate is specially manufactured and used in a thickness of 1 to 3 mm. This is deviating from a general semiconductor standard, which makes it difficult to use semiconductor processing equipment and consumes a large amount of material.

Accordingly, it is an object of the present invention to provide a semiconductor device having a III-nitride epitaxial layer and a lift-off technique for separating each chip into an ultra-thin film, To provide an epitaxial structure and a manufacturing method thereof.

As a means for solving the above problems, the dissimilar substrate of the present invention comprises a base substrate, an intermixing layer formed on the base substrate, an interlayer formed on the intermixing layer, a buffer layer And an epi layer formed on the buffer layer.

According to another aspect of the present invention, a heterogeneous substrate manufacturing method of the present invention includes the steps of growing an interlayer on a base substrate, forming a top layer on the interlayer, forming a buffer layer Forming a high-temperature III-nitride epitaxial layer on the buffer layer, growing the epitaxial layer on the buffer layer, forming a III-nitride epitaxial layer on the buffer layer, And a part of the layer reacts with the base substrate to form an intermixing layer between the base substrate and the interlayer.

In the present invention, the following effects are expected through a structure for forming a III-nitride semiconductor epitaxial layer on a silicon substrate and a manufacturing method using the same.

First, a III-nitride semiconductor ultra thin film can be obtained through a low-cost process, and its quality is excellent without defects, so that it can have superior characteristics in manufacturing a semiconductor device through the III-nitride semiconductor ultra thin film.

Second, the present invention using an interlayer having a fluidity is effective for effectively suppressing stress generated regardless of lattice mismatch of a III-nitride semiconductor epitaxial layer grown on a semiconductor substrate Device characteristics.

Third, when the Ge material is used as an interlayer, the thermal expansion coefficient is similar to that of the GaN epitaxial layer, thereby preventing wafer warping.

Fourth, the selective etching solution provides an advantage of easily obtaining a III-nitride semiconductor thin film.

1A to 1F are cross-sectional views showing characteristics of a circuit and an element structure of a conventional FET.
2 is a description of a technical problem of GaN-on-Si.
3A to 3F are cross-sectional views illustrating a manufacturing process of a hetero-substrate using the concept of an inter-mixing layer according to the present invention.
Figure 4 is a comparison of the physical constants of the materials.
5A and 5B are cross-sectional views of the interlayer according to the present invention in a single layer and a multi-layer structure.
6A to 6D are cross-sectional views illustrating an intermixing layer epitaxy for growing a three-group nitride based epitaxial layer on a silicon base substrate according to the present invention.
7A to 7D are cross-sectional views illustrating a method of manufacturing a semiconductor device using a hetero-substrate according to the present invention.
FIG. 8 is a table summarizing the advantages and disadvantages of the prior art and the technique of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the detailed description of known functions and configurations incorporated herein will be omitted when it may unnecessarily obscure the subject matter of the present invention.

The same reference numerals are used for portions having similar functions and functions throughout the drawings.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to include an element does not exclude other elements unless specifically stated otherwise, but may also include other elements.

Hereinafter, preferred embodiments of the hetero-substrate including the intermixing layer between the semiconductor substrate and the high-temperature epitaxial layer according to the present invention having the above-described structure will be described in detail with reference to the accompanying drawings.

3F, the dissimilar substrate 100 of the present invention includes a base substrate 110, an intermixing layer 120a formed on the base substrate 110, an interlayer 120a formed on the intermixing layer 120a, A top layer 120b formed on the interlayer 120, a buffer layer 130 formed on the top layer 120b and an epi layer 140 formed on the buffer layer 130 .

The interlayer 120 functions to dissipate the residual stress by forming the intermix layer 120a through a diffusion reaction with the base substrate 110 during the epitaxial layer epitaxy process. In addition, the degree of occurrence of crystal defects due to stress due to lattice mismatch in the epitaxial layer 140 is minimized.

In particular, the interlayer 120 has properties substantially similar to those of the epitaxial layer in which the thermal expansion coefficient is finally grown, thereby preventing the wafer bending due to the difference in thermal expansion coefficient.

The base substrate 110 refers to various material layers having high melting temperatures such as silicon and sapphire.

The interlayer 120 may be formed of a semiconductor material having a lower melting point than the buffer layer 130 and the epi-layer 140. The interlayer 120 may include a sandwich-shaped composite layer composed of a single layer or a multi-layered epilayer depending on the composition ratio and composition of the material. Interlayer 120 includes Si1-xGex, Ge1-xSnx epi layers.

The interlayer 120 may be formed by growing a buffer layer 130 at a low temperature and growing an epitaxial layer 140 at a high temperature in the growth of a III-nitride epitaxial layer 140 This layer is intermixed with the base substrate 110 so that the epitaxial layer 140 to be finally grown is not affected by the lattice constant of the semiconductor base substrate 110 .

The top layer 120b is a material having a lattice constant characteristic that is higher than that of the interlayer 120 and is thermally and physically stable and helps grow a buffer layer 130 grown thereon. The interlayer 120 and the buffer layer 130 are not affected when the Epi layer 140 is grown.

To this end, the top layer 120b is a physically stable layer that prevents the interlayer 120 and the buffer layer 130 from reacting, and has a sharp interface characteristic.

The epitaxial layer 140 includes a III-nitride epitaxial layer. The three-element nitride based epitaxial layer may comprise a composite layer in which single or multiple layers of GaN, InN, AlN and their ternary, quaternary compound semiconductor epitaxial layers are formed in sandwich form. In the present invention, the epitaxial layer 140 is related to a III-nitride epitaxial layer and SiGe and GeSn epitaxial layers, and a substantial epitaxial layer having a complicated structure is simplified and named collectively.

Such an epi-layer 140 can be usefully used for manufacturing a light emitting element, a light receiving element, a high-voltage high-voltage FET or a high-power diode. Particularly, the epitaxial layer 140 of the present invention has few crystal defects, and is suitable for the production of semiconductor devices and high-density digital-analog circuits, and is easy to fabricate in a large area.

As described above, the SiGe-based epitaxial layer 120 grown at a low temperature relaxes the stress severely at a high temperature of 1,000 to 1,300 DEG C, which grows a III-nitride layer, while crystal defects are grown in the SiGe-based epitaxial layer And generates an intermix layer 120a.

The intermixing layer 120a is formed of a material having a high quality such that the epitaxial layer 140 to be finally grown is not affected by the lattice constant of the semiconductor base substrate 110 and is free from defects and cracks, It has the role of having characteristics. This can solve the wafer bending phenomenon due to the difference of the thermal expansion coefficient and the defect caused by the lattice constant mismatch, which is the greatest problem in the growth of the conventional III-nitride epitaxial layer, and it can show excellent quality characteristics.

Particularly, the inter mixing layer 120a is formed by etching the base substrate 110 and the elements formed in the grown III-nitride epitaxial layer 140 and a solution having a high selectivity ratio It has a great advantage that the device can be easily separated and used for integration. For example, due to the intermixing layer 120a, a defect-free high-quality thin film can be grown and separated regardless of the lattice mismatch and thermal expansion coefficient between the semiconductor base substrate 110 and the epi-layer 140.

Therefore, the strain due to the lattice mismatch between the silicon base substrate 110 and the III nitride epitaxial layer 140 and the strain due to the mismatch between the thermal expansion coefficient and the 17% 57% can accommodate the physical transformation of relaxation.

On the other hand, when a semiconductor device is fabricated in the III-nitride epitaxial layer 140 and an intermixing layer 120a is formed therebetween, a lift-off (lift) process for separating each chip into an ultra- -off) technology can be stably secured. In this case, the heat generated from the high-power device is sufficiently discharged to the outside with high thermal conductivity, which is advantageous for manufacturing a highly reliable III-nitride power device. Likewise, a light emitting device or a light receiving device is fabricated with an ultra-thin film of III-nitride, and the photoelectric conversion efficiency can be obtained by operating vertically.

Hereinafter, a hetero-substrate according to the present invention and a method of manufacturing a semiconductor device using the same will be described in detail with reference to the drawings.

3A to 3F, an interlayer 120 is grown on a base substrate 110, a top layer 120b is formed on an interlayer 120, and a top layer 120b Temperature buffer layer 130 is grown on the buffer layer 130 to form a high temperature III-nitride semiconductor epitaxial layer 140 on the buffer layer 130.

At this time, when the epitaxial layer 140 is grown, a part of the interlayer 120, which is in contact with the base substrate 110 while having the fluidity of the interlayer 120, reacts with the base substrate 110, The intermixing layer 120a is formed between the first interlayer 120 and the second interlayer 120a.

Therefore, the fusion temperature of the interlayer 120 should be higher than the growth temperature of the buffer layer 130 and lower than the growth temperature of the epitaxial layer 140. For example, the interlayer 120 is stress relaxed at a high temperature of 1,000 to 1,300 DEG C to grow the epitaxial layer 140, and crystal defects are focused on the SiGe-based epitaxial layer.

On the other hand, the top layer 120b prevents reactivity between the buffer layer 130 and the interlayer 120 during growth of the epitaxial layer 140 of the high-temperature III nitride semiconductor (III-nitride). If the interlayer 120 reacts with the buffer layer 130, an intermix layer may be formed in the interlayer 120 in contact with the buffer layer 130.

≪ Embodiment 1 >

3A to 3F are cross-sectional views illustrating an inter layer epitaxy process according to an embodiment of the present invention.

3A is a cross-sectional view showing a configuration of a base substrate 110 for epitaxial growth.

3B is a cross-sectional view illustrating a structure of an inter layer 120 and a top layer 120b formed on a base substrate 110. FIG.

3C is a cross-sectional view illustrating the structure of a buffer layer 130 formed on a top layer 120b. The buffer layer 130 is grown at a lower temperature than the interlayer 120.

FIG. 3D is a plan view of an atomic layer structure of an interlayer 120 when a temperature is raised for growth of an Epi layer (140 in FIG. 3F) after growth of a buffer layer 130 110). ≪ / RTI >

3E illustrates an interlayer 120 epitaxy process in which an interlayer 120 reacts with a base substrate 110 to form an inter mixing layer 120a. Fig. Defects due to the lattice mismatch between the semiconductor base substrate 110 and the Epi layer (140 in FIG. 3F) are all relaxed in the interlayer 120, ) 140, a defect-free high-quality layer having an original lattice constant can be grown regardless of the difference in lattice constant with respect to the semiconductor base substrate 110.

3F is a cross-sectional view of an embodiment of a cross-sectional structure in which an Epi layer 140 is grown on a buffer layer 130 through the above-described process.

5A and 5B are cross-sectional views of another embodiment of the present invention for growing an Epi layer 140 using a single layer and multi-layer interlayer 120. FIG.

5A and 5B, in a heterogeneous substrate 100 including a base substrate 110, an interlayer 120, a top layer 120b, a buffer layer 130, and an epitaxial layer 140, In the case where the interlayer 120 is formed of a single material or a composite layer according to two or three materials and compositions, the techniques of the present invention can be used in various ways. Accordingly, it is possible to control the conditions suitable for the fusion temperature and lift-off of the semiconductor base substrate 110 and the epi layer 140 to be grown.

≪ Embodiment 2 >

6A to 6D illustrate a structure in which a Ge epi layer is interposed between a silicon (Si) base substrate 210 and a III-nitride Epi layer 240 Lt; RTI ID = 0.0 > interlayer < / RTI > epitaxy. A Si1-xGex or Ge1-xSnx epitaxial layer 220 having a minimized defect is grown on a silicon (Si) base substrate 210 using a two-step growth method, a buffer layer method or the like.

Then, a III-nitride buffer layer 240 is formed at a low temperature. The Si1-xGex, Ge1-xSnx epilayer, which is the interlayer 220, becomes fluid when the chamber temperature is raised for the subsequent high-temperature growth. As a result, the atoms of the interlayer 220 are diffused into the base substrate 210 to form an intermixed layer 220a. The III-nitride Epi layer 240 grown thereafter grows into a defect-free high-quality thin film regardless of the lattice constant of the silicon (Si) base substrate 210. Also, in the case of the Ge interlayer 220, the thermal expansion coefficient of the GaN epitaxial layer 240 is similar to that of the GaN epitaxial layer 240, thereby preventing wafer warping due to the thermal expansion coefficient mismatch.

≪ Third Embodiment >

FIGS. 7A through 7D illustrate an epitaxial layer 340 through selective solution etching after growth of an epitaxial layer 340 through an interlayer 320 of the present invention, and features of a device isolation method and a defect reduction method Sectional views.

7A is a cross-sectional view illustrating a process of dry etch a III-Nitride Epi layer grown on an interlayer 320 on a silicon (Si) base substrate 310, And a hole is formed up to a mixing layer (inter mixing layer) 320a. For example, the epilayer 340, the buffer layer 330, the top layer 320b, the interlayer 320, and a part of the intermixing layer 320a may be removed through the dry etching process in the vertical direction.

7B shows a III-Nitride Epi layer 340 (FIG. 7B) in which a solution containing selective etching between the silicon (Si) base substrate 310 and the intermixing layer (SiGe layer) Sectional view showing a process of selectively inserting the epi-layer 340 by inserting the base substrate 310 on which the base substrate 310 is grown. For example, the interlayer 320 and the intermixing layer 320a may be removed through a wet etching process in a horizontal direction.

At this time, when the interlayer 320 and the intermixing layer 320a are removed, a part of the top layer 320b may be removed together. Further, when the interlayer 320 and the intermixing layer 320a are removed, a part of the intermixing layer 320a may remain.

FIG. 7C is a cross-sectional view showing a process of easily separating elements by selectively etching between elements when the III-nitride-based element 342 is manufactured.

7D shows that a defect that may be induced between the base substrate 310 and the epi-layer 340 in the multi-layered epitaxial layer 340 manufactured by the present invention is confined in the inter layer 320, To the epi-layer 340 located at the bottom of the substrate.

<Comparative Example>

Referring to the table of FIG. 8, the advantages and disadvantages of various substrate-related technologies of GaN-on-sapphire, GaN-on-Si, GaN-on-SiC and GaN-on-SiGe can be seen. In case of GaN-on-sapphire substrate, it is easy to secure GaN epitaxial growth technology, can use an insulating substrate, and is stable at high temperature. However, it is disadvantageous to a vertical type device and has a low thermal conductivity, which is disadvantageous to a power device.

In the case of GaN-on-Si, the epitaxial process is simple, manufacturing cost is low, and silicon doping and device integration are easy. However, the occurrence of cracks due to lattice mismatch or thermal expansion gaps is serious and is susceptible to thermal and mechanical shock.

In the case of GaN-on-SiC, it is easy to secure GaN epitaxial growth technology, can use an insulating substrate, has high thermal conductivity, and is stable at high temperature. However, the substrate is expensive, the reliability is low, the substrate size is limited, and productivity is low.

In the case of GaN-on-SiGe, it is possible to control the stress, adjust the relaxation process, easily integrate with the silicon semiconductor, facilitate the lift-off using the wet etching, Is reusable. Here, compared to a very simple structure such as GaN-on-Si in which a GaN epitaxial layer is directly grown on a silicon substrate, the III-nitride epitaxial layer has excellent crystallinity and electrical properties, while substrate manufacturing cost is slightly increased .

As described above, a high-quality III-nitride semiconductor epitaxial layer is grown using the interlayer of the present invention and a high-performance device using the epitaxial layer can be fabricated. The process steps for manufacturing the device according to the present invention are very simple. Process step and process control are simple and accurate, and the product is excellent in mass productivity and reliability.

In this technology, GaN-on-Ge-on Si technology significantly reduces wafer deflection due to thermal expansion coefficient as well as efficient defect reduction. These materials have a thermal expansion coefficient of 5.6 (GaN), Ge (5.8) and Si (2.6), respectively. Therefore, conventional GaN-on- The thermal expansion coefficient is similar and it is a solution to solve the problem when it is used as an interlayer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. To those skilled in the art.

100: heterogeneous substrate 110: base substrate
120: Interlayer 120a: Intermixing layer
120b: top layer 130: buffer layer
140: Epilayer

Claims (12)

A base substrate;
An intermixing layer formed on the base substrate;
An interlayer formed on the intermixing layer;
A top layer formed on the interlayer;
A buffer layer formed on the top layer; And
An epi layer formed on the buffer layer; And,
Wherein the top layer has a stable material characteristic and a sharp interface property so as to block mixing and diffusion reaction between the epi layer and the interlayer in an epitaxial process of the epi layer. Structure to grow on heterogeneous substrates. The method according to claim 1,
The interlayer serves to dissipate the residual stress by forming the intermixing layer through a diffusion reaction with the base substrate during the epitaxial layer epitaxy, and a crystal defect due to stress due to lattice mismatch is formed in the epitaxial layer Wherein the high temperature epi layer is grown on a heterogeneous substrate. The method according to claim 1,
Wherein the interlayer has a property substantially similar to that of the epitaxial layer in which the thermal expansion coefficient is finally grown, thereby preventing wafer warping caused by a difference in thermal expansion coefficient. . The method according to claim 1,
The interlayer is composed of Si1-xGex and Ge1-xSnx, and has a fluidity by changing the composition ratio of the grown III-nitride to the type of the epi layer and the type of the base substrate Wherein the high temperature epi layer is grown on a heterogeneous substrate. delete Growing an interlayer on top of the base substrate;
Forming a top layer on the interlayer;
Growing a low-temperature buffer layer on the top layer;
Forming a high-temperature boron-phosphide-based epitaxial layer on the buffer layer; And
Forming an intermix layer between the base substrate and the interlayer by reacting a portion of the interlayer, which is in contact with the base substrate, with the interlayer when the epitaxial layer grows, Wherein the high temperature epi layer is grown on a heterogeneous substrate. The method according to claim 6,
Wherein the melting temperature of the interlayer is higher than the buffer layer growth temperature and lower than the epilayer growth temperature. The method according to claim 6,
Wherein the interlayer is stress relaxed at a high temperature of 1,000 to 1,300 DEG C for growing the epitaxial layer, and crystal defects are focused on a SiGe-based epitaxial layer. The method according to claim 6,
Wherein the top layer prevents reactivity between the buffer layer and the interlayer when growing the epitaxial layer at a high temperature. The method according to claim 6,
Lifting off the epilayer from the base substrate; Wherein the step of lifting off comprises:
A dry etching step of removing the epilayer, the buffer layer, the top layer, the interlayer, and a part of the intermixing layer in a vertical direction;
A wet etching step of removing the interlayer and the intermixing layer in a horizontal direction; And
Fabricating and separating a semiconductor device in the epilayer; Wherein the first and second substrates are formed on the first substrate and the second substrate, respectively. 11. The method of claim 10,
Wherein when the interlayer and the intermix layer are removed, a part of the top layer is removed together. 11. The method of claim 10,
Wherein a part of the intermixing layer remains on the base substrate when removing the interlayer and the intermixing layer.

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