KR101443922B1 - A metallic bump structure without under bump metallurgy and a manufacturing method thereof - Google Patents

Abstract

The metal bumps are formed directly on the I / O pads of the semiconductor wafer without the UBM. First, a zinc layer is formed on the I / O pad and the anti-oxidation layer of the I / O pad is selectively etched. The isolation layer and the copper foil are then successively disposed in this order above the I / O pad. The isolation layer is originally in a liquid or transient solid state and then solidifies permanently. Vias over the I / O pads are then formed by removing the isolation layer and portions of the copper foil. A thin metal layer joining the copper foil and the I / O pad is then formed in the via and a plating resist is formed on the copper foil. A metal bump is then formed from the via, and the height of the via is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a metal bump structure without a metal bump and a manufacturing method thereof,

The present invention relates generally to flip chip packaging, and more particularly to a method of forming metallic bumps on I / O pads of a semiconductor device without under bump metallurgy, Metal bump structure.

Flip chip packaging utilizes bumps to form electrical contacts between the I / O pads of a semiconductor die (e.g., a chip) and the leadframe of the substrate or package. Conventionally, there is a so-called under bump metallurgy (UBM) located between the bumps and the I / O pads of the semiconductor die.

The UBM typically includes an adhesive layer, a barrier layer, and a wetting layer that are sequentially arranged on top of the I / O pad. The bumps themselves can be classified into bumps with solder bumps, gold bumps, copper pillar bumps and mixed metals based on the materials used.

Techniques such as electroplating, printing or stud bonding are typically used to form bumps on UBMs. For electroplating, patterned plating resists are first formed on the UBMs and then the metals are plated. For printing, the solders are first printed on the UBMs and the solder is heat cured to the bumps. For stud bonding, only limited gold bumping is used. The semiconductor die with bumps is then individually singulated from the semiconductor wafer and soldered onto a substrate or leadframe.

The UBM not only prevents copper traces on the semiconductor die from melting into the solder, but also acts as a conducting plate if the electroplating is a means of forming metal bumps. In addition, if aluminum is used in the I / O pads, the wet layer of UBM provides reliable solderability to form solder bumps.

It is therefore a primary object of the present invention to provide a method of forming metal bumps directly on I / O pads of a semiconductor wafer without costly UBM processes. The I / O pads can be made of copper or aluminum, and if the I / O pads are made of copper, they can have an anti-oxidation layer made of aluminum or other antioxidant material.

According to one embodiment of the present invention, the method includes the following main steps. First, a zinc layer is formed on the upper surface of the aluminum I / O pad or the oxidation resistant layer of the I / O pad is selectively etched. The isolation layer and the copper foil are then successively arranged in this order above the I / O pad. The isolation layer is originally in a liquid or temporarily cured state and is then permanently cured to firmly attach to the semiconductor die. I / O, a via over the pad, is then formed by removing the isolation layer and a portion of the copper foil. A thin metal layer joining the copper foil and the I / O pads is then deposited on the via and the plating resist on the copper foil is laminated. The metal bumps are then plated from vias to conduct current by utilizing a copper foil and a thin metal layer, the height of which is controlled by the plating resist. Finally, the plating resist and the copper foil are removed.

SUMMARY OF THE INVENTION The present invention provides a method of forming metallic bumps on I / O pads of a semiconductor device without under bump metallurgy and a metal bump structure thus formed.

The above objects, features, aspects and advantages of the present invention will be better understood by reading the accompanying detailed description provided below with appropriate reference to the accompanying drawings.

The following description is merely illustrative embodiments and is not intended to limit the scope, applicability or configuration of the invention in any way. Rather, the following description provides a convenient example for implementing exemplary embodiments of the invention. Many modifications to the described embodiments may be made in the functionality and arrangement of the elements described without departing from the scope of the invention as set forth in the appended claims.

Figures 1A-1H illustrate the results of the steps of forming metal bumps on I / O pads of a semiconductor wafer in accordance with an embodiment of the invention. As shown in FIG. 1A, the I / O pads 12 are located on one side of a semiconductor die, which may be an integrated circuit (IC), transistor, diode, or thyristor. This face is referred to as the active face of the semiconductor die 10 for ease of reference. Note that the semiconductor die 10 is actually a part of a semiconductor wafer (not shown) and has not yet been individually separated. Semiconductor wafers may have many dice 10, and each semiconductor die 10 may have many I / O pads 12. For ease of understanding, only one semiconductor die 10 and one I / O pad are shown in the accompanying drawings. On the active surface of the semiconductor die 10 is a passivation layer 14 that exposes a portion of the top surface of the I / O pad 12. The term "semiconductor device" as used herein may also refer to a semiconductor die as shown or a semiconductor wafer comprising many semiconductor dies.

The I / O pads 12 may be made of aluminum or copper. If the I / O pad 12 is made of copper, the I / O pad 12 is typically made of aluminum or other antioxidant material to cover the exposed upper surface of the I / 16). If the I / O pads 12 are made of aluminum, there is typically no oxidation resistant layer. If the I / O pads 12 are made of aluminum or the I / O pads 12 are made of copper with an aluminum antioxidant layer 16, the zinc layer can be a zinc bath commonly known as zincation Lt; RTI ID = 0.0 > I / O < / RTI > In an alternative embodiment in which instead of coating the zinc layer, the I / O pad 12 is comprised of copper having an antioxidant layer 16 of aluminum or other antioxidant material, Lt; RTI ID = 0.0 > I / O < / RTI > The result will be similar to the view of FIG. 1A without the antioxidant layer 16.

Briefly summarized, there are three possible combinations: (1) a zinc layer coated on the aluminum I / O pad 12; (2) a zinc layer coated on the aluminum anti-oxidation layer 16 of the copper I / O pad 12; Or (3) the copper I / O pad 12 is selectively etched by an antioxidant layer 16 made of aluminum or other antioxidant material. The zinc layer is typically very thin. Therefore, for the sake of simplicity, the following combinations (2) (i.e., the antioxidant layer 16 and the zinc layer are coated on the antioxidant layer 16) are mainly used by way of example and the zinc layer is too thin to be seen. The following description of combinations (1) and (3) can be easily extended by expressing that the antioxidant layer 16 is absent in the accompanying drawings.

An isolative layer 18 and a copper foil 20 are then provided as shown in FIG. 1B. The isolation layer 18 and the copper foil 20 are successively arranged in this order on the upper surface of the Fig. 1A structure and the results are shown in Fig. 1C. The material of the isolation layer 18 is that the isolation layer 18 is in a liquid state (step A) or in a transiently cured state (step B) so that the isolation layer 18 can firmly attach to the structure of FIG. Various types of polymers, such as epoxy resins, are ideal materials for the isolation layer 18. The isolation layer 18 is then permanently solidified (step C) by applying appropriate heat and pressure to the liquid or temporarily cured isolation layer 18, thereby adhering firmly to the structure of FIG. 1A. If a temporary cured quarantined material is selected, the quarantined material should be able to return to the liquid state again within the specified temperature range during curing. In one embodiment, the copper foil 20 is first coated with an isolation layer 18, and the combination is then deposited on the upper surface of the structure of FIG. 1A. And then is permanently solidified by applying appropriate heat and pressure to the quaternary layer 18, thereby adhering firmly to the structure of FIG. In one alternative embodiment, the isolation layer 18 is in a transiently cured or liquid state and is first deposited on the top surface of the FIG. 1A structure. A copper foil 20 is then deposited on the upper surface of the isolated layer 18. Thereafter, by applying appropriate heat and pressure, the quenchant layer 18 is permanently solidified and thereby adheres firmly to the structure of FIG. 1A. Alternatively, the isolation layer 18 may be reinforced with glass fibers. The copper foil 20 may also optionally be thinner if a fine pitch bump or a tiny bump is to be formed.

A portion of the copper foil 20 above the I / O pad 12 is then first removed by laser ablation or chemical etching and then a portion of the isolation layer 18 over the I / Is removed by laser ablation or lithographic means. So that the via 22 exposing the top surface of the zinc layer of the I / O pad 12 (or the copper I / O pad 12 if the antioxidant layer 16 is first etched by selective etching) As shown in FIG. The semiconductor device during the lamination of the copper foil 20 and the isolation layer 18 on the semiconductor device may be a whole semiconductor wafer without separation or a part of the semiconductor wafer after cutting and separating.

As mentioned earlier, if the I / O pad 12 is made of aluminum or if the I / O pad 12 has an antioxidant layer 16 made of aluminum, then the zinc layer will have an isolation layer 18 and copper foil O pad 12 or the aluminum antioxidation layer 16 of the I / O pad 12 by a zinc bath process prior to lamination of the I / O pad 20. In an alternate embodiment, the zinc layer is formed by the zinc bath process after the via 22 of FIG. 1D is formed in the same manner as described above, to form the aluminum oxidation resistant layer 12 of the I / O pad 12 or I / (16). ≪ / RTI > The selective etching of the antioxidant layer to expose the copper I / O pads 12 may also be accomplished using the vias of FIG. ≪ RTI ID = 0.0 > 1d, < / RTI & (22) may be formed.

A thin metal layer 24 is then formed in at least the via 22 using electroless deposition of copper or nickel so that a thin metal layer 24 is deposited on the zinc layer The copper foil 20 is bonded to the upper surface of the copper I / O pad 2 if the copper foil 20 is selectively etched. An optional additional metal layer may be further formed by electroplating (or electroless electrodeposition) on the outer surface of the thin metal layer 24 to enhance reliability. Plated metal layers are not shown for simplicity. A plating resist 26 is then coated using a photoimageable film lamination and a plating opening (numbering) is performed to expose the via 22 coated with the thin metal layer 24, By selectively applying a light exposure on the upper surface of the copper foil 20 having the desired thickness (not shown). The copper foil 20 and the thin metal layer 24 can together conduct the current to plate the metal bumps 28 in the vias 22 above the I / O pads 12, as shown in FIG. have. The material of the metal bump 28 may be selected from the group consisting of gold, copper, tin, nickel, solder, and combinations thereof, which has good adhesion to the thin metal layer 24 and good weldability during assembly.

Finally, the plating resist 26 is stripped as shown in FIG. 1h and a portion of the copper foil 20 under the plating resist 26 is also removed using laser or chemical etching. The metal bump 28 is then coated with a coating 30 on top of the top surface of the metal bump 28 (metal bump 28 is completely covered in the figure) to prevent the metal bump 28 from being oxidized prior to assembly It can be covered more selectively. Various materials may be used as the coating layer 30 depending on the material of the metal bumps 28. [ For example, in the case of nickel bumps 28, a gold coating layer 30 may be used, and in the case of copper bumps 28, the coating layer 30 may include, but not limited to, Organic Solubility Preservative (OSP), electroless nickel / An electroless nickel immersion gold, an immersion silver, or an immersion tin. In an alternative embodiment, the coating layer 30 is formed on the upper surface of the structure of FIG. 1G by electroplating before the plating resist 26 is stripped.

Thereafter, the plating resist 26 and a portion of the copper foil 20 under the plating resist 26 are removed. The result produced would be similar to the result of Figure 1 h, except that there is no coating 30 on the sides of the metal bump 28. Therefore, the formation of the metal bump 28 is completed. The height of the metal bump 28 can be adjusted by making the plating resist 26 an appropriate height and the width of the metal bump 28 is determined by adjusting the opening of the plating opening on the plating resist 26.

In an alternative embodiment, the liquid quench layer 18 is applied to the structure of Fig. 1A alone, without the copper foil 20. The isolation layer 18 is then first solidified to a temporary cured state and the via layer 12 is removed to expose the zinc layer of the I / O pad 12 (or the copper I / O pad 12 if the oxidation protection layer 16 is selectively etched) 22 are formed. The copper foil 20 is then deposited on the temporarily cured isolating layer 18. The isolation layer 18 then coagulates permanently with the copper foil 20. After that, a portion of the copper foil 20 over the via 22 is removed by chemical etching or laser ablation, and the result is the same as that shown in Fig. Subsequent steps similar to those described above may be performed to form the metal bump 28. While coating the isolation layer 18 on a semiconductor device, the semiconductor device may be an entire semiconductor wafer without isolation or a part of a semiconductor wafer after cutting and separating.

In another alternative embodiment in which copper foil 20 is not used at all, a liquid or temporarily cured separating layer 18 is deposited on the structure of FIG. 1A and permanently coagulated alone. Vias 22 are then formed to expose the zinc layer of the I / O pad 12 (or the copper I / O pads 12 if the antioxidant layer 16 is selectively etched). A thin metal layer 24 is subsequently formed in the via 22 on the upper surface of the isolating layer 18 and by sputtering or electroless electrodeposition. The thin metal layer 24 is then selectively thickened to achieve better conductivity by electroplating (or electroless electrodeposition) and the result will be similar to that shown in FIG. 1e. The thickened metal layer 24 above the isolation layer 18 will perform the function of the copper foil 20 in the previous embodiments. Subsequent steps similar to those described above may be performed to form the metal bump 28. In such an embodiment, an isolation layer such as ABIN (Ajinomoto Build-ip Film) with good adhesion to electroless electrodeposition is desirable, especially for better reliability, while rerouting is required for the bumping process. During the coating of the isolation layer 18 on the semiconductor device, the semiconductor device may be an entire semiconductor wafer without isolation or a part of a semiconductor wafer after cutting and separating.

In another alternate embodiment where the isolation layer 18 is also deposited on the structure of FIG. 1A without the copper foil 20 and permanently solidified by itself, the thin metal layer 24 is deposited by sputtering or electroless deposition, (18). Vias 22 are formed to expose the zinc layer of the I / O pad 12 (or the copper I / O pad 12 if the antioxidant layer 16 is selectively etched). The thin metal layer 24 is then again formed by electroless deposition or sputtering to cover at least the via 22. The thin metal layer 24 is selectively thickened to achieve better conductivity by electroplating (or electroless electrodeposition) and the result will be similar to that shown in FIG. The thickened metal layer 24 above the isolation layer 18 will perform the function of the copper foil 20 in the previous embodiments. Subsequent steps similar to those described above may be performed to form the metal bump 28. During the coating of the isolation layer 18 on the semiconductor device, the semiconductor device may be an entire semiconductor wafer without isolation or a part of the semiconductor wafer after cutting and separating.

O pad 12 (not shown) to form a via 22 to accurately expose the zinc layer of the I / O pad 12 (or the copper I / O pad 12 if the antioxidant layer 16 is selectively etched) ) Must be determined first. To achieve this, fiducial marks may be prepared on the bottom surface of the semiconductor device in advance. The exact positional coordinates of the I / O pads 12 can then be determined by examining the coordinates of the reference marks and their positional relation to the I / O pads 12. An alternative approach is to use an X-ray device through the copper foil 20 of Figure 1C to directly determine the exact positional coordinates of the I / O pads 12. [ Another alternative approach is to use the camera to detect fiducial marks on the semiconductor device after removing a portion of the copper foil 20 and then to calculate the positional coordinates of the I / O pad 12.

Bump rerouting is sometimes not desirable because metal bumps on the original locations of the I / O pads are not suitable for soldering in the next assembly process and conventional UBM processes can reorder the bumps to the proper location for subsequent soldering do. The present invention omits the expensive UBM process to achieve the bump rerouting shown in Figure 2 so that the rerouted bumps 28A and the routing traces 42 on the side of the vias 22 are suitable Lt; / RTI > Figures 3a-3d illustrate additional steps for extending the method of the present invention to achieve bumpless routing.

Figure 3A shows a structure formed according to the steps shown by Figures 1A-1F. 3A is similar to the structure of FIG. 3A except that the plating resist 26 is formed on the side of the via 22 as well as the specified location of the metal bump 28A and the designated location of the rerouted metal bump 28A, 1f in that it has a plating opening 40 for exposing the exposed surface 42 of the substrate. It is recommended to ablate the blind hole 60 following the via 22 below the designated position of the rerouted metal bump 28A to enhance the mechanical strength of the rerouted metal bump 28A. The thin metal layer 24 is also deposited with the blind holes 60 below the rerouted metal bumps 28A as well as before the plating resist 26 is laminated. Alternatively, a conductive paste may fill the blind holes 60 and solidify to replace the deposition of the thin metal layer 24.

And then plated until copper or other suitable metal reaches a thickness designed to form the routing trace 42, as shown in Figure 3B. 3C, a second plating resist 26A is applied to the upper surface of the plating resist 26 and the designated position of the rerouted metal bump 28A (i.e., the upper part of the blind hole 60) Until a metal bump 28A rerouted with a suitable metal such as copper, nickel, solder, tin, gold, or a combination thereof, is formed at a designated location with a specified thickness Plated. Finally, as shown in FIG. 3D, the plating resist 26, 26A is removed and a portion of the copper foil 20 under the plating resist 26 is etched by chemical etching or laser ablation to form a rerouted metal bump The coupling trace 28A and the coupling trace 42 are completed. Optionally, a solder mask may then be applied to cover the via 22 and the routing trace 42 for protection.

In an alternative embodiment, the plating resist 26 includes a via 22, a routing trace 42 that joins the designated location of the rerouted metal bump 28A, the via 22 and the designated location, One or more plated bars 52 that connect the plated electrode 50 of the semiconductor wafer shown in Fig. 2 to the plated electrode 50 of the semiconductor wafer shown in Fig. 2), the plated metal bump 28A, the via 22 and the routing trace 42, And has a plating opening for exposure. Copper or other suitable metal is then plated to a thickness designed to form the routing trace 42 and the plated bar 52. The plating resist 26 is first peeled off and a portion of the copper foil 20 under the plating resist 26 is etched by laser ablation or chemical etching. An optional solder mask is then applied on the semiconductor die 10 with an opening on the designated location of the rerouted metal bump 28A. next. The second plating resist 26A is laminated on the solder mask with an opening on the designated position of the rerouted metal bump 28A. A metal bump 28A rerouted with a suitable metal, such as copper, nickel, solder, tin, gold, or a combination thereof, is used to conduct the current using a plating bar 52 Plated. Finally, the second plating resist 26A is peeled off and the plating bar 52 is etched. Thereafter, the rerouted metal bump 28A is completed. Note that these steps are very similar to the previous embodiments and therefore no additional drawings are provided.

Sometimes, if rerouting is difficult to achieve with a single layer of the above traces, a plurality of trace layers may be used with the routing trace (s) on the lower layer (s) terminating at any midpoint (s). One embodiment is described as follows and is shown in Figures 4A-4D. According to steps 1A-1F, a plating resist 26 is applied to the via 22, the intermediate location, the side (s) to which the intermediate location combines the via 22, as shown in FIG. 4A after the thin metal layer 24 is coated in the via. And is laminated on the copper foil 20 with an opening to expose the routing trace 42. Copper or other suitable metal is plated to achieve the designed thickness to form the routing trace 42 as shown in Figure 4B. The plating resist 26 is then stripped and a portion of the copper foil 20 under the plating resist 26 is etched by laser ablation or chemical etching. The second isolation layer 68 and the second copper foil 70 are then laminated and permanently solidified on the semiconductor die 10 as shown in Figure 4C. It should be noted that various approaches for laminating the second isolation layer 68 and the second copper foil 70 may also be applied here and the detailed description thereof is omitted here for the sake of simplicity. A portion of the second copper foil 70 and the second isolation layer 68 above the intermediate location may be removed by similar methods as described above to form a second via 72 exposing an intermediate location as shown in Figure 4D. . It is recommended to ablate the blind hole 74 following the second via 72 beneath the designated location of the rerouted metal bump 28A to increase the mechanical strength of the again rutted metal bump 28A do. The thin metal layer 76 is then deposited with the rerouted metal bump 28A and the blind holes 74 below the second vias 72. Alternatively, a conductive paste may be plugged into the blind holes 74 to solidify to replace the deposition of the thin metal layer 74.

The similarity between the structure shown in FIG. 4D and the structure shown in FIG. 3A is very straight forward. The same steps described in Figures 3A-3D thus form a rerouted metal bump 28A joined to the second via 72 at an intermediate location by the second trace layer 78 and the second trace layer 78 . The result is shown in Figure 4e. The above-described processes may actually be repeated to reroute more intermediate locations and more routing trace layers.

The most important advantages of the present invention are as follows. Elements selected from a large set of highly conductive metal materials such as gold, silver, palladium, copper, tin, solder, nickel, or a combination of these highly conductive metal materials are first deposited on the metal bumps 28 ). ≪ / RTI > Secondly, the bonding of the metal bumps 28 to the semiconductor die 10 is enhanced by the additional bonding provided by the insulating layer 18, so that an excellent bond between the metal bumps 28 and the semiconductor die 10 Bonding. Third, if the expensive UBM process is to replace the UBM with copper foil 20, which serves as an electroplating bond during the formation of metal bumps and a selected barrier layer coated on metal bump 28, Can be omitted because the trace can be prevented from dissolving, thereby significantly reducing the production cost.

While the invention has been described with reference to preferred embodiments, it is not intended to be limited to the embodiments shown. Various substitutions and modifications have been suggested above and others will occur to those skilled in the art. Therefore, all such substitutions and modifications are intended to be included within the scope of the invention as defined in the appended claims.

Figures 1 AH show the results of steps of forming metal bumps on I / O pads in accordance with one embodiment of the present invention.

2 is a schematic top view showing a semiconductor die of a semiconductor wafer having rerouted metal bumps and a plated net.

Figures 3a-3d illustrate additional steps to extend the method of Figures la-lh to achieve bumpless routing.

Figures 4A-4E illustrate steps for achieving bump re-routing through two trace layers.

Claims (84)

Disposing an isolation layer and a copper foil on the active surface of the semiconductor device in this order; Forming vias in the isolation layer over the I / O pad and the copper foil; Forming a thin metal layer at least in the via coupled to the copper foil and the I / O pad; Forming a first plating resist having a first opening on said upper surface of said copper foil to at least expose said via coated with said thin metal layer; And Forming a metal bump on the I / O pad on the active surface of the semiconductor device, comprising plating a metal material within the first opening. 3. The method of claim 1, wherein if the I / O pad is made of aluminum or if the I / O pad has an aluminum oxidation layer, the aluminum I / O pad or the aluminum I / Further comprising the step of forming a zinc layer on the upper surface of the aluminum antioxidant layer. 2. The method of claim 1, wherein if the I / O pad is made of aluminum or if the I / O pad has the aluminum anti-oxidation layer, then the upper surface of the aluminum I / O pad or aluminum anti- ≪ / RTI > further comprising the step of forming a zinc layer on the metal layer. The method of claim 1, further comprising removing the anti-oxidation layer prior to disposing the isolation layer and the copper foil if the I / O pad is made of copper and the I / O pad has an anti- A method of forming a bump. The method of claim 1, further comprising removing the anti-oxidation layer after the via is formed if the I / O pad is made of copper and the I / O pad has an anti-oxidation layer. The method of claim 1, wherein the isolation layer is one of a temporary cured state and a liquid state; The copper foil is first coated with the isolation layer; The copper foil and the isolation layer are stacked together on the active surface; The quench layer is permanently solidified; And the via is formed by removing the isolation layer and a portion of the copper foil above the I / O pad. The method of claim 1, wherein the isolation layer is one of a temporary cured state and a liquid state; The isolation layer is first deposited on the active surface; The copper foil is then deposited on the upper surface of the isolation layer; The separating layer is then permanently solidified; And the via is then formed by removing the isolation layer and a portion of the copper foil above the I / O pad. The method of claim 1, wherein the isolation layer is in a liquid state and is first applied to the active surface; The quenching layer solidifies in a temporary cured state; The via is formed by removing a portion of the isolation layer over the I / O pad; The copper foil is then deposited on the upper surface of the isolation layer; The quench layer is permanently solidified; And a portion of the copper foil on the via top is removed. The method of claim 1, further comprising thinning the copper foil if fine pitch metal bumps are desired. The method of claim 1, wherein the thin metal layer is formed of one of copper and nickel. The method of claim 1, further comprising forming an additional metal layer on the outer surface of the thin metal layer prior to forming the first plating resist. The method of claim 1, wherein the metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. The method according to claim 1, Removing the first plating resist and a portion of the copper foil under the first plating resist; And Further comprising forming a coating layer on the upper surface of the metal material to prevent oxidation. The method according to claim 1, Forming a coating layer for preventing oxidation on the upper surface of the metal material; And Further comprising: removing the first plating resist and a portion of the copper foil under the first plating resist. The method of claim 1, wherein the first opening is a method of forming a metal bump further exposing one of a rerouted and intermediate position of the metal bump and a routing trace joining the rerouted or intermediate position to the via . 16. The method of claim 15, Further comprising forming a blind hole in the isolation layer at the rerouted position prior to forming the thin metal layer, Wherein the thin metal layer further forms a metal bump that covers the blind hole. 16. The method of claim 15, further comprising: forming a blind hole in the isolation layer at the rerouted position prior to forming the thin metal layer; And Further comprising filling the blind hole with a conductive paste prior to forming the first plating resist. 16. The method of claim 15, Forming a second plating resist having a second opening exposing the rerouted position on the upper surface of the first plating resist and the routing trace; Plating the second metal material in the second opening; And Further comprising forming the metal bumps by removing the first and second plating resist and a portion of the copper foil under the first plating resist. 19. The method of claim 18, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 19. The method of claim 18, further comprising applying a solder mask to cover the routing trace and the via after removing the first and second plating resist and the copper foil. 5. The method of claim 1, wherein the first opening comprises a rutting location for joining the rerouted position of the metal bump, the rerouted location and the via, and at least the via, the routing trace, and the rerouted metal bump. Further exposing a plating bar for bonding a plating electrode of the semiconductor device to a plating net; Wherein plating of the metallic material forms a metal bump forming the routing trace and the plating bar. 23. The method of claim 21, Removing the first plating resist and a portion of the copper foil under the first plating resist; Applying a solder mask to expose the rerouted position, a portion of the plating bar, and the plating electrode; Forming a second plating resist on the solder mask having a rerouted position and a second opening to expose the plating electrode; Forming the metal bump by plating a second metal material in the second opening; And And removing the second plating resist and the plating bar. 23. The method of claim 22, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 16. The method of claim 15, Removing the first plating resist and a portion of the copper foil under the first plating resist; Disposing a second isolation layer having a second via at the intermediate location and a second copper foil on the active surface of the semiconductor device in this order; Forming a second thin metal layer in at least the second via; A second via pattern formed on the upper surface of the second copper foil, the second via coated with the second thin metal layer, the rerouted position of the metal bump and the second routing trace coupling the rerouted location to the second via, Forming a second plating resist having a second opening to expose the second plating resist; Forming the second routing trace by plating a second metallic material in the second opening; Forming a third plating resist having a third opening to expose the rerouted location on the upper surface of the second plating resist and the second routing trace; Plating a third metal material in the third opening; And And forming the metal bump by removing a portion of the second and third plating resist and the second copper foil under the second plating resist. 27. The method of claim 24 further comprising forming a blind hole in the second isolation layer and the second copper foil at the rerouted position prior to forming the second thin metal layer, Wherein the second thin metal layer further forms a metal bump that covers the blind hole. 25. The method of claim 24, further comprising: forming a blind hole in the isolation layer and the second copper foil at the rerouted position prior to forming the second thin metal layer; And Further comprising the step of filling the blind holes with a conductive paste prior to forming the second plating resist. 27. The method of claim 24, wherein the second and third metallic materials are one of gold, copper, tin, nickel, solder, and combinations thereof. The method of claim 1, wherein the semiconductor device is one of a semiconductor wafer and a portion of a semiconductor wafer after separation. Disposing an isolation layer on the active surface of the semiconductor device; Forming a via in the isolation layer over the I / O pad; Forming a thin metal layer on the upper surface of the isolation layer and in the via coupling the I / O pad; Forming a first plating resist on the upper surface of the thin metal layer above the isolation layer, the first plating resist having a first opening to expose at least the via coated with the thin metal layer; And Forming a metal bump on the I / O pad on the active surface of the semiconductor device, comprising plating a metal material on the first opening. 29. The method of claim 29, wherein if the I / O pad has aluminum or an anti-oxidation layer of aluminum, the aluminum I / O pad or the aluminum anti- ≪ / RTI > further comprising the step of forming a zinc layer on the metal layer. 29. The method of claim 29, wherein if the I / O pad is made of aluminum, or if the I / O pad has an aluminum antioxidant layer, the upper surface of the aluminum I / O pad or aluminum anti- ≪ / RTI > further comprising forming a zinc layer on the substrate. 29. The method of claim 29, further comprising removing the anti-oxidation layer prior to disposing the isolation layer, if the I / O pad is made of copper and the I / O pad has an anti-oxidation layer Way. 32. The method of claim 29, further comprising removing the anti-oxidation layer after the via is formed if the I / O pad is made of copper and the I / O pad has an anti-oxidation layer. 32. The method of claim 29, wherein the isolation layer is one of a transient cured state and a liquid state and is first deposited on the active surface; The quench layer is permanently solidified; The via is then formed by removing a portion of the isolation layer over the I / O pad; And the thin metal layer forms on the upper surface of the isolation layer and within the via. 30. The method of claim 29, wherein the isolation layer is in a liquid or transiently cured state and is first deposited on the active surface; The quench layer is permanently solidified; The thin metal layer is then formed on the upper surface of the isolation layer; The via is then formed by removing a portion of the isolation layer and the thin metal layer over the I / O pad; And the thin metal layer forms a metal bump that is again formed in the via. 30. The method of claim 29, further comprising thickening the thin metal layer prior to forming the first plating resist. 32. The method of claim 29, wherein the thin metal layer comprises one of copper and nickel. 31. The method of claim 29, wherein the metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 29. The method of claim 29, Removing the first plating resist and a portion of the thin metal layer under the first plating resist; And And forming a coating layer for preventing oxidation at least on the upper surface of the metal bump. 29. The method of claim 29, Forming a coating layer for preventing oxidation on the upper surface of the metal bump; And Further comprising removing the first plating resist and a portion of the thin metal layer under the first plating resist. 32. The method of claim 29, wherein the first opening further exposes one of a rerouted and intermediate position of the metal bump, a routing trace coupling the rerouted or intermediate position to the via; Wherein plating of the metallic material forms a metal bump forming the routing trace. 45. The method of claim 41, further comprising forming a blind hole in the isolation layer at the rerouted position prior to forming the first plating resist; Wherein the thin metal layer also forms a metal bump that also covers the blind hole. 42. The method of claim 41, Forming a blind hole in the isolation layer at the rerouted position before forming the first plating resist; And Further comprising filling the blind hole with a conductive paste prior to forming the first plating resist. 42. The method of claim 41, Forming a second plating resist having a second opening exposing the rerouted position on the upper surface of the first plating resist and the routing trace; Plating a second metallic material within the second opening; And Further comprising forming the metal bumps by removing the first and second plating resist and a portion of the thin metal layer under the first plating resist. 45. The method of claim 44, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 45. The method of claim 44, further comprising applying a solder mask to cover the routing trace and the via after removing the first and second plating resist. 32. The method of claim 29, wherein the first opening is formed in a rinsing position of the metal bump, a rerouted position, and a routing net that joins the via and a plating net including at least the via, the routing trace, and the metal bump. Further exposing a plating bar for bonding the plating electrode of the semiconductor device; Wherein plating of the metallic material forms a metal bump forming the routing trace and the plating bar. 48. The method of claim 47, further comprising: removing the first plating resist and a portion of the thin metal layer under the first plating resist; Applying a solder mask to expose the rerouted position, a portion of the plating bar, and the plating metal; Forming a second plating resist on the solder mask including the rerouted position and a second opening to expose the plating electrode; Forming the metal bump by plating a second metal material within the second opening; And And removing the second plating resist and the plating bar. 49. The method of claim 48, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 48. The method of claim 47, Disposing a second isolation layer and a second thin metal layer having a second via in an intermediate position on the active surface of the semiconductor device in this order; Forming a second thin metal layer in at least the second via; Exposing a second routing trace on the upper surface of the second thin metal layer, the second via coated with the thin metal layer, the rerouted location of the metal bump and the rerouted location to the second via, Forming a second plating resist having a second opening to form a second plating resist; Forming the second routing trace by plating a metal material within the second opening; Forming a third plating resist having a third opening exposing the rerouted position on the upper surface of the second plating resist and the second routing trace; Plating a third metallic material within the third opening; And Further comprising forming said metal bumps by removing said second and third plating resist and a portion of said second thin metal layer under said second plating resist. 51. The method of claim 50, further comprising forming a blind hole in the second isolation layer and the second thin metal layer at the rerouted position prior to forming the second thin metal layer; Wherein the second thin metal layer further forms a metal bump that covers the blind hole. 51. The method of claim 50, further comprising: forming a blind hole in the second isolation layer and the second thin metal layer at the rerouted position prior to forming the second thin metal layer; And Further comprising the step of filling the blind holes with a conductive paste prior to forming the second plating resist. 51. The method of claim 50, wherein the third metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 30. The method of claim 29, wherein the semiconductor device is one of a semiconductor wafer and a portion of a semiconductor wafer after separation. An insulating layer and a copper foil having vias on top of the I / O pad and sequentially arranged on the active surface of the semiconductor die; A thin metal layer at least coupled to the copper foil and the I / O pad in the via; And And a metal material filled in said vias and extending vertically above said copper foil and said isolation layer, The metal material extending laterally from the copper foil and over the isolation layer to one of the rerouted and intermediate positions of the metal bump from the via, Wherein the copper foil and the isolation layer comprise blind holes covered with the thin metal layer in the rerouted position. 56. The method of claim 55, wherein if the I / O pad is made of aluminum or if the I / O pad has an anti-oxidation layer of aluminum, a zinc layer is deposited on the upper surface of the aluminum I / Including more metal bump structure. 56. The metal bump structure of claim 55, wherein the isolation layer is one of a transiently cured state and a liquid state prior to application to the active surface. 55. The metal bump structure of claim 55, wherein the thin metal layer comprises one of copper and nickel. 56. The metal bump structure of claim 55, wherein the metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 56. The metal bump structure of claim 55, further comprising a coating layer for preventing oxidation at least on the upper surface of the metallic material. delete delete An insulating layer and a copper foil having vias on top of the I / O pad and sequentially arranged on the active surface of the semiconductor die; A thin metal layer at least coupled to the copper foil and the I / O pad in the via; And And a metal material filled in said vias and extending vertically above said copper foil and said isolation layer, The metal material extending laterally from the copper foil and over the isolation layer to one of the rerouted and intermediate positions of the metal bump from the via, Wherein the copper foil and the isolation layer comprise blind holes filled with a conductive paste at the rerouted location. An insulating layer and a copper foil having vias on top of the I / O pad and sequentially arranged on the active surface of the semiconductor die; A thin metal layer at least coupled to the copper foil and the I / O pad in the via; And And a metal material filled in said vias and extending vertically above said copper foil and said isolation layer, The metal material extending laterally from the copper foil and over the isolation layer to one of the rerouted and intermediate positions of the metal bump from the via, And a second metallic material on the upper surface of the metallic material at the rerouted position. 65. The metal bump structure of claim 64, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. An insulating layer and a copper foil having vias on top of the I / O pad and sequentially arranged on the active surface of the semiconductor die; A thin metal layer at least coupled to the copper foil and the I / O pad in the via; And And a metal material filled in said vias and extending vertically above said copper foil and said isolation layer, The metal material extending laterally from the copper over the copper foil and the isolation layer to one of the rerouted and intermediate positions of the metal bump from the via, A second isolation layer and a second copper foil sequentially arranged with a second via at an intermediate location on the active surface of the semiconductor die; At least a second thin metal layer in the second via; A second copper foil extending laterally from the second via to the rerouted position of the metal bump and a second metal material over the second isolation layer; And And a third metallic material on the upper surface of the second metallic material at the rerouted position. 65. The metal bump structure of claim 66, wherein the second isolation layer and the second copper foil are covered with the second thin metal layer and have blind holes filled with the second metal material in the rerouted position. 65. The metal bump structure of claim 66, wherein the second isolation layer and the second copper foil have blind holes filled with a conductive paste at the rerouted position. 65. The metal bump structure of claim 66, wherein the second and third metallic materials are one of gold, copper, tin, nickel, solder, and combinations thereof. An isolation layer having vias over the I / O pads on the active surface of the semiconductor die; A thin metal layer in the via that couples the top surface of the isolation layer and the I / O pad; And And a metal material filled in the vias and extending perpendicularly to the thin metal layer and the isolation layer, Wherein the isolation layer has a blind hole covered with the thin metal layer in a rerouting position. 65. The method of claim 70, wherein if the I / O pad is made of aluminum or if the I / O pad has an anti-oxidation layer of aluminum, a zinc layer is deposited on the top surface of the aluminum I / Including more metal bump construction. 55. The structure of claim 70, wherein the isolation layer is one of a transiently cured state and a liquid state prior to application to the active surface. 54. The metal bump structure of claim 70, wherein the thin metal layer comprises one of copper and nickel. 51. The metal bump structure of claim 70, wherein the metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 58. The metal bump structure of claim 70, further comprising a coating layer on the upper surface of the metallic material for anti-oxidation. 54. The metal bump structure of claim 70, wherein the metal material extends laterally from the thin metal layer and over the isolation layer to one of the rerouted and intermediate locations of the metal bump from the via. delete 75. The metal bump structure of claim 76, wherein the isolation layer comprises a blind hole filled with conductive paste in the rerouted position. 75. The metal bump structure of claim 76, further comprising a second metallic material on the upper surface of the metallic material in the rerouted position. 81. The metal bump structure of claim 79, wherein the second metallic material is one of gold, copper, tin, nickel, solder, and combinations thereof. 78. The method of claim 76, A second isolation layer and a second copper foil having second vias in the intermediate position and sequentially arranged on the active surface of the semiconductor die; At least a second thin metal layer in the second via; A second copper foil extending laterally from the second via to the rerouted position of the metal bump and a second metal material over the second isolation layer; And And a third metallic material on the upper surface of the second metallic material at the rerouted position. 81. The metal bump structure of claim 81, wherein the second isolation layer comprises blind holes in the rerouted position covered by the second thin metal layer and filled with the second metal material. The structure of claim 81, wherein the second isolation layer comprises a blind hole filled with a conductive paste at the rerouted location. The metal bump structure of claim 81, wherein the second and third metallic materials are one of gold, copper, tin, nickel, solder, and combinations thereof.

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