KR101443959B1 - Structure of semiconductor package and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package includes a connection pad, a first metal layer, a circuit layer, a pin base, a guide hole, and a metal bump . Further, the circuit may be formed as a single layer or a multilayer, and the connection pads and the external pins are electrically connected. In addition, in the manufacturing process, the positioning structure is designed to facilitate the positioning, thereby overcoming the positioning error due to heating or cooling, and greatly increasing the accuracy of alignment of the guide holes and the connection pads, Thereby ensuring reliability.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor package structure and a method of manufacturing the same.

The present invention relates to a semiconductor package structure and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor package structure and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor package structure, And a method of manufacturing the semiconductor package.

Prior art flip chip package technology uses metal bumps to electrically connect the connection pads of a semiconductor die and the substrate or leadframe to provide a first connection between the metal bumps and the connection pads of the semiconductor die, (Under Bump Metallurgy).

Generally, the UBM includes an adhesive layer, a barrier layer and a bonding layer, which are laminated on the connecting pad from below to above. Depending on the material used, the bumps can be classified as tin-lead bumps, gold bumps, copper cylinder bumps and metal blending bumps.

The solder bump forming method of the semiconductor device disclosed in U.S. Patent No. 5,508,229 is applied to an entire wafer. In a microlithography manufacturing process, A UBM was formed along the reference point to allow current to flow, thereby forming a metal bump.

In this conventional technique, instead of using an entire wafer, a plated metal bump, or an interconnecting circuit, the entire wafer is divided first to form a semiconductor die, and the semiconductor chip is first positioned on the single crystal circuit surface and fixed on the film . The backside is then fixed through glue or hot pressing. A blind hole is also formed on the film using a laser or other method to expose the connection pads of the semiconductor die. The metal layer can be formed by ion sputtering or chemical vapor deposition methods, as disclosed in U.S. Patent Nos. 5,353,498 and 7,067,356. Or a chemical dip coating method, which is disclosed in U.S. Patent No. 7,067,356. Alternatively, a metal foil may be used to adhere to the film, and a chemical dip coating method may be used to form a metal film in the blind hole, as disclosed in U.S. Patent No. 6,991,966. After that, according to the general printed circuit board manufacturing process, connection pin and external pin are connected and completed.

In the above-described prior art, first, a reference point and a cavity are formed on the core board, and then the semiconductor die is positioned at the reference point and sealed, and a guide hole is formed to expose the connection pad of the die. However, sealing work carried out using glue or hot compression is all done under high temperature and high pressure, where semiconductor die having different thermal expansion coefficients of the die, film and core board material and already positioned prior to glue or thermal compression, Or its position is changed during the cooling process. Thereafter, the position is determined again along the reference point of the core board, and a guide hole for exposing the connection pad is formed. In this process, it is difficult to align the guide holes and the connection pads, which affects the package quality.

Accordingly, a semiconductor die filler chip packaging method that can be applied to a flip chip package of a semiconductor die is newly developed and applied on a wafer and / or a chip and / or a die, without using a UMB and / By improving the quality of the package structure by reducing the positioning error that can be caused by the difference in the thermal expansion coefficient of the die, film, and fixing material, without fixing the die and fixing again by glue or heat compression, There is a desperate need to solve the problem.

US 5,508,229 2. US 5,353,498 3. US 7,067,356 4. US 6,991,966

The main object of the present invention is to provide a semiconductor package structure which comprises a semiconductor die, a connection pad, a passivation layer, a first metal layer, an insulation layer, a circuit layer, a pin base, a metal bump, And a bonding chip. An insulating plate is formed on the bonding chip, and a plurality of cavities are provided. A semiconductor die is formed in the plurality of cavities and a connection pad is formed on the tangential surface of the semiconductor die. The semiconductor die is positioned to correspond to the bottom surface of the tangent plane, and is connected to the bonding chip. The passivation layer covers the tangential surface of the semiconductor die, forming an opening to expose the upper surface of the one or more connection pads.

A first metal layer is formed on the upper surface of the connection pad. An insulating layer is formed on the passivation layer and the first metal layer, and includes a guide hole to expose the first metal layer. The circuit layer is formed on a part of the surface of the insulating layer, and is positioned on the hole wall of the plurality of guide holes and connected to the first metal layer. A pin base is formed on the circuit layer and the metal bumps are connected to the pin base to contact the circuit layer thereby electrically connecting the connection pads on the semiconductor die and the external circuit board.

Further, a second insulating layer having an opening on the circuit layer can be further formed, through which part of the circuit layer is exposed. An external circuit layer is formed on a part of the surface of the second insulating layer and the hole wall of the opening, and the external circuit layer is connected to the circuit layer. After the above-described structures are successively laminated, a pin base is formed on the outermost circuit layer, and the metal bumps are connected to the pin base. The pin base and the outer circuit layer are in contact so that the connection pads of the semiconductor die are electrically connected to the external circuit board.

It is still another object of the present invention to provide a method of fabricating a semiconductor package structure that includes a semiconductor wafer preparation step, a first metal layer formation step, an insulation layer formation step, a guide hole and positioning structure formation step, A second metal layer forming step, a circuit forming step, and a bump connecting step. The semiconductor wafer preparation step mainly comprises preparing a semiconductor wafer, wherein the semiconductor wafer includes one or more semiconductor dies, each semiconductor die having at least one connection pad and a passivation layer. The connection pad is formed on the tangential surface of the semiconductor die and the passivation layer is formed to cover the tangential surface of the semiconductor die but the top surface of the one or more connection pads is exposed through the opening.

In the first metal layer formation step, a first metal layer is formed on the connection pad. In the insulating layer forming step, an insulating layer is formed on the semiconductor wafer. In the step of forming the guide hole and the positioning structure, a guide hole is formed on the insulating layer so that the first metal layer is exposed, and a positioning structure is formed to facilitate positioning in a subsequent step. The dividing step divides the semiconductor die along each semiconductor die. In the aligning and compacting step, a divided semiconductor die is inserted into a spacer, which includes an insulating plate and a bonding chip. The insulating plate is fixed on the bonding chip, and has a plurality of cavities to form a semiconductor die. In both the cavity periphery and the outer rim of the spacer, a positioning mark is formed to correspond to and be positioned with respect to the positioning structure. After positioning, make sure that the surface of the insulating plate and the insulating layer are flush with each other.

In the second metal layer forming step, a second metal layer is formed on the surfaces of the insulating layer and the insulating plate. The second metal layer may also be formed on the hole wall of the insulating layer guide hole and connected to the first metal layer. In the circuit formation step, the second metal layer is patterned. In the bump connecting step, a pin base is formed on the circuit layer, and then a metal bump is formed on the pin base, thereby completing the semiconductor package structure such that the metal bumps correspond to the connection pads on the semiconductor die.

Advantageously, one or more circuit lamination steps can be carried out before the bump connecting step, wherein the circuit lamination step includes an insulating layer forming step, a guide hole forming step and an external circuit forming step. In the insulating layer forming step, a second insulating layer is formed on the circuit layer and the insulating layer. In the guide hole forming step, an opening is formed in the second insulating layer so that a part of the circuit layer is exposed. In the external circuit forming step, an external metal layer is formed on the second insulating layer, the external metal layer is formed on the hole wall of the opening to connect the external metal layer and the circuit layer, and then the external metal layer is rendered by the image transfer method , And an external circuit layer is formed.

A feature of the semiconductor package structure and the method of manufacturing the same according to the present invention is that a connection pad, a first metal layer, and a second metal layer are mounted on a semiconductor die and the connection pad is electrically communicated with the external pin. Therefore, it is possible to overcome the positioning error due to heating or cooling without using the Under Bump Metallurgy (UBM) and / or fixing the die with a film and then fixing the die with glue or thermocompression The accuracy of alignment of the guide holes and the connection pads is greatly increased, and reliability of electrical connection between the connection pads and the external fins can be ensured.

1A is a cross-sectional view showing a first embodiment of a semiconductor package structure according to the present invention.
1B is a cross-sectional view showing a first embodiment of a semiconductor package structure according to the present invention.
2 is a flow chart illustrating a method of fabricating a semiconductor package structure according to the present invention.
Figs. 3A to 3I and Figs. 4A to 4E are structural explanatory diagrams illustrating Fig.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily understand and carry out the present invention.

FIG. 1A is a cross-sectional view illustrating a first embodiment of a semiconductor package structure according to the present invention. 1A, a semiconductor package structure 2 includes a semiconductor die 10, a first metal layer 18, an insulating layer 20, a circuit layer 28, one or more pin bases 40, A metal bump 50, an insulating plate 100, and a bonding chip 200. On the semiconductor die 10, one or more connection pads 12 and a passivation layer 14 are provided. The insulating plate 100 is formed on the bonding chip 200 and is provided with a plurality of cavities and a plurality of positioning marks 104. A semiconductor die 10 is formed in the plurality of cavities, one of which is illustrated in FIG. The one or more connection pads 12 are formed on the tangential surface of the semiconductor die 10, the semiconductor die 10 being positioned to correspond to the bottom surface of the tangential surface and being connected to the bonding chip. The passivation layer 14 covers the tangential surface of the semiconductor die 10 and forms an opening to expose the top surface of the one or more connecting pads 12. The insulating layer 20 has one or more positioning structures 24 that are disposed corresponding to the plurality of positioning marks 104.

The first metal layer 18 is formed on the upper surface of the connection pad 12. The insulating layer 20 is formed on the passivation layer 14 and a portion of the first metal layer 18 and includes at least one guide hole to expose a portion of the first metal layer 18. The circuit layer 28 is formed on a part of the surface of the insulating layer 20 and is connected to the first metal layer 18. The circuit layer 28 may fill one or more guide holes, or may form a cover layer in the hole walls of one or more guide holes. Alternatively, the circuit layer 28 may extend from the insulating layer 20 to the surface of the insulating plate 100. The pin base 40 and the circuit layer 28 may be formed on the guide hole in contact with each other or may be formed in a proper position of the circuit layer 28 away from the guide hole. The metal bumps 50 are connected on the pin base 40 to electrically connect the connection pads of the semiconductor die 10 and an external circuit board (not shown).

The connection pad 12 may be made of copper, aluminum, or an alloy thereof. The material of the first metal layer 18 is copper or nickel. When a material of the connection pad 12 is made of aluminum or an alloy thereof, a zinc layer (not shown in the figure) is formed between the connection pad 12 and the first metal layer 18 to change the properties of the surface, So that the first metal layer 18 in the subsequent step can be easily attached. The material of the circuit layer 28 is at least one of copper, nickel, gold, silver, and tin. The pin base 40 is placed in the proper position in the circuit layer 28 or it is plated with a metal layer thereon to make it easy to bond with the metal bumps. The metal may be at least one of copper, gold, silver, tin, and nickel, and the metal bump 50 may be at least one of copper, gold, silver, tin, and nickel.

FIG. 1B is a cross-sectional view showing a first embodiment of the semiconductor package structure according to the present invention. Referring to FIG. As shown in FIG. 1B, the semiconductor package structure 3 according to the second embodiment and the semiconductor package structure 2 according to the first embodiment are similar to each other, but the main difference lies in the circuit layer 28. The circuit layer 28 is provided with a second insulating layer 30 having one or more openings and an external circuit layer 36 is formed on the second insulating layer 30. The external circuit layer 36 is formed on a part of the surface of the second insulating layer 30 and connected to the circuit layer 28. The external circuit layer 36 may fill the openings, or may form a cover layer in the hole walls of the openings. The pin base 40 and the external circuit layer 36 are brought into contact with each other so that the pin base 40 is positioned on the opening or separated from the opening . The metal bumps 50 are connected on the pin base 40 to electrically connect the connection pads of the semiconductor die 10 and an external circuit board (not shown).

FIG. 2 is a flow chart showing a method for fabricating a semiconductor package structure according to the present invention, and FIGS. 3A to 3I and 4A to 4E are structural explanatory views for explaining FIG. Referring to FIG. 2, a method S1 of fabricating a semiconductor package structure according to the present invention includes a semiconductor wafer preparation step S10, a first metal layer formation step S15, an insulating layer formation step S20, A structure forming step S25, a dividing step S30, an aligning and pressing step S35, a second metal layer forming step S40, a circuit forming step S45 and a bump connecting step S60.

The semiconductor wafer preparation step S10 is mainly for preparing a semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor dies 10 shown in FIG. 3A. Each semiconductor die 10 is provided with one or more connection pads 12 A passivation layer 14 is provided. The connection pad 12 is formed on the tangential surface of the semiconductor die 10 and the passivation layer 14 is formed to cover the tangential surface of the semiconductor die 10, The upper surface is exposed.

3B, the first metal layer 18 is formed on the connection pad 12 by dip coating in the first metal layer forming step S15. 3C, the insulating layer 20 is formed on the first metal layer 18 and the passivation layer 14 in the insulating layer forming step S20. 3D, the guide hole and positioning structure forming step S25 allows one or more guide holes 22 to be formed on the insulating layer 20 so that the first metal layer 18 is exposed and the positioning structure 24) so as to facilitate positioning in a subsequent step.

The dividing step S30 divides the semiconductor die 10 along the semiconductor wafer. In the aligning and pressing step S35, the divided semiconductor die 10 is inserted into the spacers shown in Figs. 3E and 3F, which include the insulating plate 100 and the bonding chip 200. Fig. The insulating plate 100 is fixed on the bonding chip 200 and includes a plurality of cavities 102. The semiconductor die 10 is formed in the plurality of cavities 102 so that the bottom surface of the semiconductor die 10 is connected to the bottom surface of the tangent surface to be connected to the bonding chip 200. As shown in FIG. 3E, a positioning mark 104 is formed in the periphery of the cavity 102 so as to be positioned and associated with the positioning structure 24. After positioning, the surfaces of the insulating plate 100 and the insulating layer 20 are kept in the same plane, and heat and pressure are applied to push the bonding chip 200 so that the bonding die 200 is bonded to the semiconductor die 10 and the insulating plate 100 So that the colloid is simultaneously poured into the positioning structure 24 and the positioning mark 104 to form the same horizontal plane as the insulating layer 20. [ In addition, a front plate positioning mark 106 is formed at the edge of the insulating plate 100 to facilitate positioning of the entire insulating plate 100 and elements during the manufacturing process.

As shown in FIG. 3G, in the second metal layer forming step S40, the insulating layer 20 and the second insulating layer 100 are formed on the surface of the insulating layer 100 by at least one of sputtering, electroplating, and chemical dip coating. A metal layer 26 is formed. The second metal layer 26 is also formed in the hole wall of the guide hole 22 of the insulating layer 20 or it fills the guide hole 22 to be in contact with the first metal layer 18. As shown in Fig. 3H, in the circuit forming step S45, the second metal layer 26 is patterned by the image transfer method to form the circuit layer 28. [ 3I, in the bump connecting step S60, the pin base 40 is inserted into the guide hole 22 covered by the second metal layer 26, or the pin base 40 is inserted in a position away from the guide hole 22 The metal bumps 50 are formed on the pin base 40 after the pin base 40 is formed so that the one or more connection pads 12 are connected to the corresponding one or more metal bumps 50, Thereby completing the package structure (2). In addition, when the pin base 40 is not formed above the guide hole 22, a concave portion (not shown in the figure) can be formed below the pin base 40 to secure the strength of the metal bump 50 do.

Advantageously, the method S1 of fabricating the semiconductor package structure can perform the circuit stacking step S50 one or more times before the bump connecting step S60, wherein the circuit stacking step S50 includes an insulating layer forming step S51 ), A guide hole forming step (S53), and an external circuit forming step (S55). In the insulating layer forming step S51, a second insulating layer 30 is formed on the circuit layer 28 and the insulating layer 20, as shown in FIG. 4A. In the guide hole forming step S53, as shown in FIG. 4B, at least one opening 32 is formed in the second insulating layer 30 so that a part of the circuit layer is exposed. 4C, the external metal layer 34 is formed on the second insulating layer 30, and the external metal layer 34 is formed on the hole wall of the opening 32. In the external circuit forming step S55, Or the openings 32 are filled so that the outer metal layer 34 and the circuit layer 28 are connected to each other so that the circuit is made conductive. Thereafter, as shown in Fig. 4D, the outer metal layer is patterned by the image transfer method to form the outer circuit layer 36. Fig.

In the drawings of the present invention, it is shown that the circuit stacking step (S50) is performed once, but in practice, it is possible to form a multilayer circuit layer by performing it several times according to the required circuit stacking density. Finally, after completing the circuit stacking step S50, the pin base 40 is formed in the concave portion of the opening 32 covered with the external circuit layer 36, or the pin base 40 is formed in the opening 32 And the metal bump 50 is formed on the pin base 40, thereby completing the semiconductor package structure 3.

Here, the first metal layer 18 is formed by a chemical dip coating method, and the second metal layer 26 is formed by sputtering, electroplating, or chemical dip coating. As the chemical dip coating solution, electroless nickel or electroless copper is most preferable. When the surface of the connection pad 12 is made of aluminum or aluminum alloy, a coating layer (not shown) is formed between the connection pad 12 and the first metal layer 18 in an electroless manner to change the surface properties , So that the first metal layer 18 of the subsequent step is easily attached. The coating layer is formed of zinc and the zinc is replaced by a chemical dip coating method. In addition, a metal particle layer (not shown) may be formed on the surface of the insulating layer 20, the surface of the insulating plate 100, and the surface of the second insulating layer 30 to form the circuit layer 28 and / Or the insulating layer 100 and / or the second insulating layer 30 so that the insulating layer 36 is easily adhered to the insulating layer 20 and / Herein, the metal particle layer includes metal particles such as copper or nickel in the polymer layer. In addition, when the pin base 40 is not located in the guide hole 22 and / or the opening 32, a concave portion (not shown in the drawing) may be formed below the pin base 40 so that the metal bump 50 ).

A feature of the semiconductor package structure and the method of manufacturing the same according to the present invention is that a connection pad, a first metal layer, and a second metal layer are mounted on a semiconductor die and the connection pad is electrically communicated with the external pin. Therefore, the connection pad and the external pin can be connected without using the under bump metallurgy (UBM). In addition, by forming the guide hole with the positioning structure of the semiconductor wafer itself as a cover, it is possible to prevent misalignment due to glue and / or post-caulking heating or cooling, and to greatly increase the accuracy of alignment of the guide holes and connection pads, And the reliability of electrical connection between the external pin and the external pin can be ensured.

The above-described embodiments are merely examples for explaining the technical features of the present invention and are not used to limit the protection scope of the present invention described in the claims. It is therefore to be understood that various modifications and equivalents may be resorted to without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the scope of protection of the present invention should be determined by the technical idea of the appended claims.

2: Semiconductor package structure 3: Semiconductor package structure
10: semiconductor die 12: connection pad
14: passivation layer 18: first metal layer
20: Insulating layer 22: Guide hole
24: positioning structure 26: second metal layer
28: circuit layer 30: second insulating layer
32: opening 34: outer metal layer
36: external circuit layer 40: pin base
50: metal bump 100: insulating plate
102: joint 104: positioning mark
106: front plate positioning mark 200: bonding chip
S1: Manufacturing method of semiconductor package structure
S10: semiconductor wafer preparation step
S15: First metal layer forming step
S20: Insulating layer forming step
S25: Guide hole and positioning structure formation step
S30: Split step
S35: Alignment and Compression Steps
S40: second metal layer formation step
S45: Circuit formation step
S50: Circuit stacking step
S51: Insulating layer forming step
S53: Guide hole forming step
S55: External circuit formation step
S60: Bump concatenation step

Claims (11)

Bonding chip;
An insulating plate fixed on the bonding chip, the insulating plate having a plurality of cavities and a plurality of positioning marks;
One or more semiconductor dies formed in any one of said plurality of cavities, each of said semiconductor dies including at least one connection pad and a passivation layer, wherein a bottom surface of said semiconductor die and said bonding chip are connected The semiconductor die;
A first metal layer formed on an upper surface of the at least one connection pad;
An insulating layer formed on the passivation layer and the first metal layer and having at least one guide hole to expose the first metal layer;
A circuit layer formed on a part of the surface of the insulating layer and in the at least one guide hole, the circuit layer being connected to the first metal layer;
At least one pin base formed on the circuit layer; And
Wherein the at least one connection pad is formed on the at least one semiconductor die, the at least one connection pad electrically connected to the at least one connection pad and the external circuit board formed on the at least one pin base, The passivation layer covering the tangential surface of the semiconductor die and forming a plurality of openings to expose an upper surface of the at least one connection pad and having at least one positioning structure, Wherein the at least one positioning structure comprises at least one metal bump disposed corresponding to the plurality of positioning marks. The method of claim 1, wherein the circuit layer fills the at least one guide hole or forms a cover layer in the hole wall of the at least one guide hole, and wherein the at least one pin base is positioned in the at least one guide hole, And the recess is formed below the pin base to increase the strength of the metal bump. [2] The method of claim 1,
A second insulating layer having at least one opening to expose a portion of the circuit layer;
An external circuit layer formed on a part of the surface of the second insulating layer and in the one or more openings and in contact with the circuit layer,
The outer circuit layer filling the at least one opening or forming a cover layer in the hole wall of the at least one opening such that the at least one pin base is formed on the outer circuit layer, The at least one opening being not filled by the layer or filling the one or more openings. The semiconductor package structure according to claim 1, wherein the circuit layer extends to a surface of the insulating plate. The method according to claim 1 or 3, wherein a metal particle layer is formed between the surface of the insulating layer and the circuit layer, or between the second insulating layer and the outer circuit layer, wherein the metal particle layer has a plurality of metal particles The semiconductor package structure comprising: The method of claim 1, wherein the first metal layer is formed by a chemical dip coating method, wherein the chemical dip coating solution is an electroless nickel or an electroless copper, Or an aluminum alloy, a zinc layer is formed between the connection pad and the first metal layer in an electroless manner to change the properties of the surface, and the material of the at least one pin base and the at least one metal bump Is at least one of copper, gold, silver, tin, and nickel. A semiconductor wafer includes at least one semiconductor die, each semiconductor die having at least one connection pad and a passivation layer, wherein the at least one connection pad is formed on a tangential surface of the semiconductor die, A semiconductor wafer preparation step formed to cover the tangential surface of the semiconductor die, wherein the upper surface of the at least one connection pad is exposed through at least one opening;
Forming a first metal layer on the at least one connection pad by a chemical dip coating method;
Forming an insulating layer on the first metal layer and the passivation layer;
Forming at least one guide hole on the insulating layer of each semiconductor die to expose a portion of the first metal layer and form a positioning structure;
Dividing each semiconductor die along the semiconductor wafer;
Inserting each of the semiconductor die divided into spacers, wherein the spacer comprises an insulating plate and a bonding chip, the insulating plate being fixed on the bonding chip and having a plurality of cavities and a plurality of positioning marks, Wherein the semiconductor die is positioned to correspond to a bottom surface of the tangent plane and is connected to the bonding chip, the plurality of positioning marks corresponding to the positioning structure, The semiconductor die being bonded to the insulating plate and the bonding chip so that the insulating plate and the insulating layer are flush with each other and the semiconductor die is integrally formed and the colloid is simultaneously poured into the positioning structure and the positioning mark, Wherein the positioning mark has the same horizontal plane as the insulating layer , Which to align and aphap step;
A second metal layer forming step of forming a second metal layer on the surface of the insulating layer and the insulating plate, the second metal layer being in contact with the first metal layer;
Forming a circuit layer by patterning the second metal layer in an image transfer method; And
And forming a metal bump on the pin base after one or more pin bases are formed on the circuit layer and electrically connecting the connection pads on the semiconductor die to the external circuit Of the semiconductor package. 8. The method of claim 7, wherein the circuit layer fills the at least one guide hole or forms a cover layer in the hole wall of the at least one guide hole, and wherein the at least one pin base is positioned in the at least one guide hole, And the recess is formed below the pin base to increase the strength of the metal bump. 9. The method of claim 7, further comprising performing a circuit stacking step after the circuit forming step,
An insulating layer forming step of forming a second insulating layer on the circuit layer and the insulating layer;
Forming at least one opening in the second insulating layer so that a part of the circuit layer is exposed; And
Forming an outer metal layer on the second insulating layer, forming an outer metal layer by an image transfer method, and forming an outer circuit layer, and connecting the outer metal layer and the circuit layer together However,
The outer circuit layer filling the at least one opening or forming a cover layer in the hole wall of the at least one opening such that the at least one pin base is formed on the outer circuit layer, Wherein the one or more connection pads are connected to the corresponding one or more metal bumps. 2. The method of claim 1, wherein the one or more connection pads are connected to the one or more metal bumps. [7] The method of claim 7, wherein the first metal layer is formed by a chemical dip coating method, and the second metal layer is formed by at least one of sputtering, chemical dip coating and electroplating, Is an electroless nickel or electroless copper and when the surface of the one or more connection pads is made of aluminum or an aluminum alloy, the connection pad and the first metal layer are coated with zinc Wherein the at least one pin base and the at least one metal bump material are at least one of copper, nickel, gold, silver, and tin. The method according to claim 7 or 9, wherein a metal particle layer is formed between the surface of the insulating layer and the circuit layer, or between the second insulating layer and the outer circuit layer, wherein the metal particle layer has a plurality of metal particles Wherein the semiconductor package structure comprises a plurality of semiconductor packages.

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