KR101443379B1 - Liquid Crystal Pixel and Panel and Display Device including the same - Google Patents

Abstract

A liquid crystal pixel capable of quickly responding to an electrical signal is disclosed.

The liquid crystal pixel includes: a liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel drive signal to be supplied from the data line to the pixel electrode of the liquid crystal cell in response to a scan signal on the gate line; And a second switch element for switching a vertical common voltage to be supplied from a vertical common line to a vertical common electrode of the liquid crystal cell in response to the scan signal on the gate line.

Vertical electric field, horizontal electric field, response speed, liquid crystal, transverse mode common electrode, longitudinal mode common electrode, return time.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal pixel,

This specification relates to a liquid crystal pixel for controlling a light transmittance of a liquid crystal to display a dot. Further, the present specification relates to a liquid crystal panel and a liquid crystal display device including liquid crystal pixels.

A normal liquid crystal pixel controls the amount of light passing through the liquid crystal layer in response to an electrical signal to display a dot corresponding to the pixel data. The liquid crystal molecules included in the liquid crystal layer are rearranged in the direction of forming the electric field (for example, vertical or horizontal direction) in an initial alignment state (e.g., a horizontal or vertical alignment state) to adjust the amount of light transmitted. When the electric field is removed, the liquid crystal molecules of the liquid crystal layer return to the initial alignment state in the rearranged state. This return of the liquid crystal molecules to the initial alignment state proceeds not by the electric field but by the elastic force of the liquid crystal molecules, the rotational viscosity of the liquid crystal molecules, and the anchoring energy between the alignment film and the liquid crystal molecules. The elastic force of the liquid crystal molecules, the rotational viscosity of the liquid crystal molecules, and the anchoring energy between the alignment film and the liquid crystal molecules are remarkably smaller than the electric field energies.

Due to this, the returning speed of the liquid crystal molecules to the initial alignment state is inevitably slower than the rearrangement speed. The slow return rate of the liquid crystal molecules acts as a factor to lower the response speed of the liquid crystal pixel to the electrical signal. Even in a liquid crystal panel in which liquid crystal pixels are arranged in a matrix form, the response speed of an image with respect to video data can not but be limited. In addition, in the image displayed by the liquid crystal display device using the liquid crystal panel, deterioration of the outline and hue and blurring are inevitable. As a result, the liquid crystal display device is inevitably deteriorated in image quality.

Accordingly, the present specification will provide an embodiment of a liquid crystal pixel that is more responsive to electrical signals.

In this specification, embodiments of a liquid crystal panel and a method of manufacturing the liquid crystal panel capable of responding to an electrical signal more quickly will be provided.

Furthermore, the present specification will provide embodiments of a liquid crystal display device and a driving method thereof that can improve image quality.

A liquid crystal pixel according to an embodiment includes: a liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel drive signal to be supplied from the data line to the pixel electrode of the liquid crystal cell in response to a scan signal on the gate line; And a second switch element for switching a vertical common voltage to be supplied from a vertical common line to a vertical common electrode of the liquid crystal cell in response to the scan signal on the gate line.

The vertical common voltage may selectively have a high potential level higher than a maximum voltage level of the pixel driving signal and a low potential level corresponding to a voltage on the horizontal common voltage line according to a voltage of the pixel driving signal. The vertical common voltage maintains the high potential level when the pixel driving signal has the black level voltage, and has the low potential level when the pixel driving signal is higher than the black level voltage.

The gate line may include main and sub gate lines. In this case, the first switch element will respond to the main scan signal on the main gate line, and the second switch element will respond to the subscan signal on the subgate line.

A liquid crystal panel according to an embodiment includes a plurality of main gate lines intersecting with each other, and unit regions divided by a plurality of data lines, wherein a horizontal common electrode common-connected to a horizontal common voltage line, - arranged pixel electrodes, and corresponding main gate lines, and data lines and A first substrate on which a main thin film transistor connected between pixel electrodes is formed; A plurality of sub-gate lines opposed to the main gate lines and a plurality of vertical common voltage lines opposed to the data lines, A second substrate formed with a vertical common electrode located in each of the regions, and a sub-thin film transistor connected between the corresponding sub gate line, a corresponding vertical common voltage line, and a corresponding horizontal common electrode; And a liquid crystal layer disposed between the pixel and the horizontal common electrode of the first substrate and the vertical common electrode of the second substrate.

A method of manufacturing a liquid crystal panel according to an embodiment of the present invention includes a plurality of main gate lines and a plurality of data lines intersecting with unit areas to divide unit areas, a horizontal common electrode provided in each of the unit areas to be connected to a horizontal common voltage line, Pixel electrodes arranged alternately with the electrodes, and corresponding main gate and data lines and Forming a main thin film transistor connected between pixel electrodes on a first substrate; A plurality of subgate lines opposed to the main gate lines, a plurality of vertical common voltage lines opposed to the data lines, a unit divided by the subgate lines and the vertical common voltage lines Forming a sub-thin film transistor on the second substrate, the sub-thin film transistor being connected between a corresponding one of the sub-gate lines, a corresponding vertical common voltage line and a corresponding horizontal common electrode; Disposing the first and second substrates such that the pixel and the horizontal common electrode face the vertical common electrode; And injecting a liquid crystal material between the first and second substrates.

A liquid crystal display according to an exemplary embodiment of the present invention includes liquid crystal cells arranged in unit areas divided by a plurality of gate lines and a plurality of data lines, vertical common voltage lines respectively corresponding to the data lines, A first switch element for selectively connecting a corresponding data line and a pixel electrode of a corresponding liquid crystal cell in response to a scan signal on the corresponding gate line, A liquid crystal panel having a second switch element for selectively connecting a vertical common electrode of the cell; A data converter for converting the pixel data stream into a black level control data stream; A gate driver sequentially driving the gate lines on the liquid crystal panel; A data driver for driving the data lines in response to a pixel data stream; And a vertical common line driver for selectively driving each of the plurality of vertical common voltage lines in response to the black level control data stream.

A method of driving a liquid crystal display according to an embodiment includes converting a pixel data stream into a black level control data stream; Sequentially driving a plurality of gate lines on a liquid crystal panel; Driving a plurality of data lines on the liquid crystal panel in response to a pixel data stream; And selectively driving each of the plurality of vertical common voltage lines on the liquid crystal panel corresponding to the data lines in response to the black level control data stream.

With such a configuration, the liquid crystal pixel according to the embodiment allows the liquid crystal cell to be driven by the horizontal electric field between the pixel electrode and the horizontal common electrode during the display of the lighter grayscale than the lowest grayscale (i.e., black). The liquid crystal pixel causes the liquid crystal molecules of the liquid crystal cell to be initialized by the vertical electric field between the vertical common electrode and the horizontal common electrode during the display of the lowest gradation. In other words, the liquid crystal cell is controlled by the electric field not only at the gray levels that are brighter (or higher) than the lowest gray level, but also at the time of displaying the lowest gray level. Accordingly, the liquid crystal pixel according to the embodiment can remarkably increase the response speed of light to the pixel driving signal.

The liquid crystal panel according to the embodiment allows the liquid crystal pixels to be arranged in a matrix form to be driven by a horizontal electric field when displaying gradations lighter than the lowest gradation (i.e., black), while at the time of displaying the lowest gradation, . In other words, the liquid crystal panel causes each of the liquid crystal pixels to be driven by an electric field not only at the gray level (or higher) than the lowest gray level, but also at the display of the lowest gray level. Accordingly, the liquid crystal panel according to the embodiment can respond to the pixel driving signal at a high speed.

As described above, in the liquid crystal display device according to the embodiment, the liquid crystal pixels are individually driven by the pixel driving signal at the time of displaying the grayscale lighter than the lowest grayscale (i.e., black), while at the time of displaying the lowest grayscale, And is initialized by the vertical common voltage. In other words, in the liquid crystal display according to the embodiment, the liquid crystal pixels are controlled by the electric field even in the display of the lowest gray level as well as the gray level that is brighter (or higher) than the lowest gray level. Accordingly, the liquid crystal display device according to the embodiment can display an image responding at a high speed corresponding to the video data. As a result, the liquid crystal display device according to the embodiment can minimize image deterioration and blurring phenomenon. Furthermore, the liquid crystal display device according to the embodiment can improve the image quality.

In addition to the above embodiments, other objects, other features, and other features of the present disclosure will become apparent from the detailed description of the embodiments associated with the accompanying drawings.

Hereinafter, embodiments of a liquid crystal pixel, a liquid crystal panel and a liquid crystal display capable of responding to an electrical signal will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram for explaining a liquid crystal pixel of a fast response speed according to an embodiment in detail. The liquid crystal pixel of FIG. 1 includes a liquid crystal cell CLC connected to the horizontal common voltage line HCL, a main thin film transistor MT connected to the main gate line MGL, and a sub thin film connected to the sub gate line SGL. And a transistor SM. The liquid crystal cell CLC includes a horizontal common electrode HCE connected to a horizontal common voltage line HCL, a pixel electrode PXE connected to a source electrode of the main thin film transistor MT, And a vertical common electrode (VCE) connected to the electrode. The same scan signal is supplied to the main and sub gate lines MGL and SGL.

The main thin film transistor MT switches the pixel drive signal Vpds to be supplied from the data line DL to the pixel electrode PXE of the liquid crystal cell CLC in response to the scan signal on the main gate line MGL . The pixel driving signal Vpds has a gradation voltage corresponding to the gradation of the pixel to be displayed in the gradation voltage set. The gradation voltage set includes a black level corresponding to the horizontal common voltage Vhcom, a back level voltage of a positive (or negative) voltage higher (or lower) than the horizontal common voltage Vhcom, And 2 ^k-1 gradation voltages set to have the same level difference or variable level difference between the voltages. When the scan signal Vsn has a high potential (that is, high logic), the main thin film transistor MT is turned on so that the pixel drive signal Vpds on the data line DL is turned on, To be supplied to the pixel electrode PXE of the cell CLC. At this time, a difference voltage between the voltage of the pixel driving signal Vpds and the horizontal common voltage Vhcom is charged between the pixel electrode PXE of the liquid crystal cell CLC and the horizontal common electrode HCE. The voltage charged between the pixel electrode PXE and the horizontal common electrode HCE is maintained until the main thin film transistor MT is turned on again. On the other hand, when the scan signal Vsn has a low potential (that is, low logic), the main thin film transistor MT is turned off to turn on the pixel drive signal Vpds on the data line DL And is not transmitted to the pixel electrode PXE of the liquid crystal cell CLC.

The sub-thin film transistor ST responds to the scan signal on the stand-by gate line SGL and generates a vertical common voltage Vvcom to be supplied from the vertical common voltage line VCL to the vertical common electrode VCE of the liquid crystal cell CLC, . 2, the vertical common voltage line VCL is supplied with a pixel driving signal (Vhcom) or a horizontal common voltage (Vhcom) based on the vertical common voltage Vvcoml or the horizontal common voltage Vhcom having a low potential corresponding to the same level as the horizontal common voltage Vhcom A vertical common voltage Vvcomh having a high potential corresponding to a level much higher than the maximum gradation voltage (i.e., the back level) When the pixel drive signal Vpds on the data line DL has a gradation level voltage higher than the black level as in the period of "T1" in Fig. 2, the low potential vertical common voltage Vvcoml VCL). In contrast, when the pixel drive signal Vpds on the data line DL is a black level voltage in the period of "T2" in FIG. 2, the high-potential vertical common voltage Vvcomh becomes higher than the vertical common voltage VCL . When the scan signal Vsn on the sub gate line SGL has a high potential voltage (i.e., high logic), the sub thin film transistor ST is turned on and a low vertical common voltage (VCL) on the vertical common voltage line VCL Vvcoml or a high vertical common voltage Vvcomh is supplied to the vertical common electrode VCE of the liquid crystal cell CLC. At this time, a difference voltage between the vertical common voltage Vvcoml or Vvcomh and the horizontal common voltage Vhcom is charged between the vertical common electrode VCE and the horizontal common electrode HCE of the liquid crystal cell CLC. The voltage charged between the vertical common electrode (VCE) and the horizontal common electrode (HCE) is maintained until the sub-thin film transistor (ST) is turned on again. On the contrary, when the scan signal Vsn has a low potential (that is, low logic), the sub-thin film transistor ST is turned off so that the vertical common voltage Vcom on the vertical common voltage line VCL ) Is not transmitted to the vertical common electrode (VCE) of the liquid crystal cell (CLC).

When the pixel driving signal Vpds having a voltage higher than the black level is charged between the pixel electrode PXE and the horizontal common electrode HCE while the vertical common electrode VCE is charged with the low potential vertical common voltage Vvcoml The liquid crystal molecules included in the liquid crystal cell CLC are rearranged so as to be distorted by the voltage (i.e., the horizontal electric field) of the pixel driving signal Vpds between the pixel electrode PXE and the horizontal common electrode HCE, And passes the light amount corresponding to the voltage of the signal Vpds. Accordingly, the liquid crystal pixel including the liquid crystal cell CLC displays the gray level corresponding to the voltage of the pixel driving signal Vpds. On the other hand, when the pixel electrode PXE is charged with the black pixel driving signal Vpds while the vertical common electrode VCE is charged with the vertical common voltage Vvcomh of high electric potential, the liquid crystal cell CLC The liquid crystal molecules constituting the liquid crystal molecules quickly return to the initial arrangement state by the vertical common voltage Vvcomh (i.e., the vertical electric field) of the high potential charged between the vertical common electrode VCE and the horizontal common electrode HCE, Do not. At this time, the liquid crystal pixel including the liquid crystal cell CLC displays black.

As described above, the liquid crystal molecules of the liquid crystal cell are rearranged by the horizontal electric field between the pixel electrode (PXE) and the horizontal common electrode (HCE) at the time of display of the gradation that is brighter than the lowest gradation (that is, black). At the time of display of the lowest gradation, the liquid crystal molecules of the liquid crystal cell return to the initial arrangement state by the vertical electric field between the vertical common electrode (VCE) and the horizontal common electrode (HCE). In other words, the arrangement of the liquid crystal molecules is controlled by the electric field even at the display of the lowest gradation as well as the gradations brighter (or higher) than the lowest gradation. Accordingly, the liquid crystal pixel according to the embodiment can remarkably increase the response speed of light to the pixel driving signal.

3 is a circuit diagram illustrating in detail the structure of a liquid crystal panel of a fast response speed according to an embodiment. 3 includes a plurality of data lines DL1 to DLm arranged in parallel in one direction (e.g., a horizontal direction) and a plurality of data lines DL1 to DLm arranged in parallel in another direction (e.g., And main gate lines MGL1 to MGLn. The data lines DL1 to DLm intersect the main gate lines MGL1 to MGLn to divide the liquid crystal panel into a plurality of pixel regions (for example, mxn pixel regions) arranged in a matrix form do.

The liquid crystal panel according to the practical example includes a plurality of vertical common voltage lines VCL1 to VCLm respectively corresponding to the data lines DL1 to DLm and a plurality of sub-pixels corresponding to the main gate lines MGL1 to MGLn, The gate lines SGL1 to SGLn are arranged. The vertical common voltage lines VCL1 to VCLm and the sub gate lines SGL1 to SGLn are also divided into a plurality of pixel regions (for example, mxn pixel regions) in the form of a matrix, Cross each other.

A liquid crystal pixel LPX is formed in each of the plurality of pixel regions. The liquid crystal pixel LPX includes a main thin film transistor MT connected to a corresponding main gate line MGL and a corresponding data line DL, a corresponding sub gate line SGL, A sub thin film transistor ST connected to the corresponding vertical common voltage line VCL and a liquid crystal cell CLC connected to the main and sub thin film transistors MT and ST and the horizontal common voltage line HCL . The horizontal common voltage line HCL is commonly connected to all of the liquid crystal cells CLC. The description of the liquid crystal pixel LPX will be omitted because the configuration, action, effect, and characteristics of each of these liquid crystal pixels LPX are clearly revealed through the description of FIG.

The liquid crystal pixels LPX to be arrayed in the matrix form are individually driven by a horizontal electric field at the time of displaying a gray level that is brighter than the lowest gray level (i.e., black), while they are driven by a vertical electric field do. In other words, each of the liquid crystal pixels LPX is driven by an electric field not only in the gradations that are brighter (or higher) than the lowest gradation but also in the case of displaying the lowest gradation. Accordingly, the liquid crystal panel according to the embodiment can respond to the pixel drive signal at a high speed.

The liquid crystal panel having a fast response speed as shown in FIG. 3 will be composed of first and second array substrates (i.e., lower and upper array substrates) arranged on both sides of the liquid crystal layer. FIGS. 4A and 4B are plan views illustrating in detail the planar structure of the first and second array substrates included in the liquid crystal panel according to one embodiment. Although Figures 4A and 4B show only the planar structure of some liquid crystal pixels (i.e., three liquid crystal pixels), any one of ordinary skill in the art with respect to the liquid crystal panel disclosed herein will recognize that some of the liquid crystal pixels It will be easily understood that liquid crystal pixels arranged in a matrix form by repeating in the vertical and horizontal directions can be realized.

Referring to FIG. 4A, the first array substrate 10 has data lines DL and main gate lines MGL which are arranged to cross each other. The first array substrate 10 is divided into a plurality of pixel regions P in the form of a matrix by these data lines DL and main gate lines MGL. A main thin film transistor MT is disposed in the vicinity of a crossing portion of a corresponding data line DL and a corresponding main gate line MGL. The main thin film transistor MT includes a gate electrode MGE formed on the lower surface of the semiconductor pattern MSP and source and drain electrodes MSE and MDE arranged at a predetermined interval on the surface of the semiconductor pattern MSP. The gate electrode MGE is formed to protrude from the main gate line MGL. The drain electrode MDE is formed so as to protrude from the data line DL. Further, the first array substrate 10 has a horizontal common voltage line HCL arranged in parallel with the main gate line MGL. The data lines DL and the horizontal common electrodes HCE stretched from the horizontal common voltage line HCL are arranged in each of the pixel regions P by a predetermined number. In addition, a predetermined number of pixel electrodes PXE are arranged in each of the pixel regions P. [ The pixel electrodes PXE are formed in parallel with the data lines DL, like the horizontal common electrodes HCE. A predetermined number of pixel electrodes PXE and horizontal common electrodes HCE included in each pixel region P are alternately arranged. In addition, the pixel electrodes PXE and the horizontal common electrodes HCE may be formed in various shapes such as a jig jig shape or a boomerang shape instead of a rod shape. The pixel electrode PXE on each pixel region P is electrically connected to the source electrode MSE of the corresponding main thin film transistor MT via the contact MCT.

The second array substrate 20 shown in FIG. 4B has vertical common voltage lines VCL and subgate lines SGL arranged crossing each other. The vertical common voltage lines VCE are arranged at positions corresponding to the data lines DL on the first array substrate 10 and the subgate lines SGL are also arranged on the main gate lines 10 on the first array substrate 10. [ (MGL). The second array substrate 20 is divided into a plurality of pixel regions P in the form of a matrix by the vertical common voltage lines VCE and the sub gate lines SGL. The sub-thin film transistor ST is disposed in the vicinity of the intersection of the corresponding vertical common voltage line VCE and the corresponding sub-gate line SGL. The sub-film transistor ST includes a gate electrode SGE formed on the lower surface of the semiconductor pattern SSP and source and drain electrodes SSE and SDE arranged on the surface of the semiconductor pattern SSP at a predetermined interval. The gate electrode SGE of the sub-thin film transistor ST is formed so as to protrude from the sub-gate line SGL. The drain electrode SDE of the sub-thin film transistor ST is formed so as to protrude from the vertical common voltage line VCL. Further, the second array substrate 20 has a vertical common electrode (VCE) arranged in each of the pixel regions (P). The vertical common electrode VCE is formed to occupy the remaining pixel region P except for a partial occupied region of the sub-thin film transistor ST. The vertical common electrode VCE is electrically connected to the source electrode SSE of the corresponding sub-thin film transistor ST via the contact SCT.

5 is a view for explaining a cross-sectional structure of a liquid crystal panel of a fast response speed according to an embodiment. 5 is a cross-sectional view showing a cross section taken along the line I-I 'of the first and second array substrates 10 and 20 of FIG. The liquid crystal panel of FIG. 5 has a liquid crystal material layer 30 injected between the first and second array substrates 10 and 20.

The first array substrate 10 has a gate electrode MGE and a horizontal common electrode HCE formed on the first transparent substrate 12. The first transparent substrate 12 may be any one of a plastic film and a glass substrate made of an insulating material having a high light transmittance. The gate electrode MGE is connected to the main gate line MGL (not shown) and formed simultaneously with the main gate line MGL. The horizontal common electrode HCE is connected to the horizontal common voltage line HCL not shown and simultaneously connected to the horizontal common voltage line HCL through the lift-off process and to the main gate line MGL and the gate electrode MGE, Are formed on the same layer. Actually, the gate electrode MGE and the main gate line MGL are formed by depositing a conductive material layer containing any one of Cu, Al, AlNd, Au, Ag and Mo on the first transparent substrate 12, By patterning the resulting conductive material. Next, a photoresist pattern (not shown) is formed on the first transparent substrate 12 on which the gate electrode MGE and the main gate line MGL are formed. The photoresist pattern exposes the surface of the first transparent substrate 12 on which the horizontal common electrode HCE and the horizontal common voltage line HCL are to be formed. A transparent conductive material (not shown) such as indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the exposed surface of the photoresist pattern and the first transparent substrate 12. The transparent conductive material on the photoresist pattern is removed together with the photoresist pattern through the cleaning process. Thus, the horizontal common electrode HCE and the horizontal common voltage line HCL are formed in the same layer as the gate electrode MGE and the main gate line MGL. An insulating film 14 is formed on the entire surface of the first transparent substrate 12 on which the gate electrode MGE, the main gate line MGL, the horizontal common electrode HCE and the horizontal common voltage line HCL are formed do. The insulating film 14 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the first transparent substrate 12.

The first array substrate 10 includes drain and source electrodes MDE and MSD disposed on the insulating film 14 and spaced apart from the semiconductor material pattern MSP and the data line DL and on the semiconductor material pattern MSP, MSE). The drain and source electrodes MDE and MSE constitute the main thin film transistor MT together with the semiconductor material pattern MSP and the gate electrode MGE. A semiconductor material pattern MSP is formed on the insulating film 14 at a position above the gate electrode MGE. The drain electrode MDE is formed simultaneously with the source electrode MSE and the data line DL as well as connected to the data line DL on the insulating film 14. [ The semiconductor material pattern MSP will be formed as the semiconductor material is deposited on the front side of the insulating film 14 and the deposited semiconductor material layer is patterned through the lithographic printing process. A conductive material layer including one of Cu, Al, AlNd, Au, Ag, and Mo is deposited on the front surface of the insulating film 14 having the semiconductor material pattern MSP. The drain and source electrodes MDE and MSE and the drain electrode MDE, which are spaced apart from each other on the semiconductor material pattern MSP by patterning the conductive material layer on the insulating film 14 through the lithographic printing process, A data line DL is formed.

The first array substrate 10 includes a protective layer 16 formed on the entire surface of a first transparent substrate 12 having a main thin film transistor MT and pixel electrodes PXE disposed on the protective layer 16. [ Respectively. The pixel electrodes PXE are electrically connected to each other in each pixel region P while being electrically isolated from the pixel electrodes in the other pixel region. The pixel electrodes PXE in each pixel region P are electrically connected to the source electrode MSE of the main thin film transistor MT by the contact MCT penetrating the protective layer 16. [ The protective layer 16 is formed to have a flat surface through an application process of an insulating material such as silicon nitride or silicon oxide. The protective layer 16 is provided with a contact hole exposing a part of the source electrode MSE of the main thin film transistor MT. The contact hole is formed by partially removing the protective layer 16 through the lithographic printing process. Next, a transparent conductive material such as ITO or IZO is deposited on the entire surface of the protective layer 16 that exposes a part of the source electrode MSE of the main thin film transistor MT. At this time, the transparent conductive material is embedded in the contact hole, and the contact (MCT) is formed. The transparent conductive material layer on the passivation layer 16 is patterned through the lithographic printing process to be electrically connected to the source electrode MSE of the main thin film transistor MT and to the lower horizontal common electrodes HCE, So that the pixel electrodes PXE are formed. The pixel electrodes PXE are spaced apart from the horizontal common electrode HCE by a predetermined distance in order to improve the light transmittance according to the gradation of the image. The distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is determined to be about 3.0 to 5.0 mu m by the experiment of the light transmission characteristic for the pixel driving signal Vpds at the back level . The light transmittance with respect to the pixel driving signal Vpds of the back level has a response characteristic as shown in Fig. 6 according to the separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE. 6, "ED1" indicates the light transmission characteristic with respect to the pixel driving signal Vpds at the back level when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 3.0 mu m . "ED2" represents the light transmission characteristic for the pixel driving signal Vpds of the back level when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 4.0 μm. "ED3" represents the light transmission characteristic for the pixel driving signal Vpds of the back level when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 5.0 μm. 6, when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is about 4.0 m, the light transmission characteristic with respect to the pixel driving signal Vpds of the back level is the best . It is therefore desirable that the protective layer 16 be formed to have a thickness of approximately 4.0 탆 so that the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE can be maintained to approximately 4.0 탆 or so desirable.

The first array substrate 10 may further include a color filter layer (not shown) positioned between the gate electrode MGE and the main gate line MGL and the first transparent substrate 12. The color filter layers include alternating red, green, and blue filters. Each of the red, green, and blue filters is formed to have a size corresponding to the pixel region. Further, the first array substrate 10 is positioned between the gate electrode MGE and the main gate line MGL and the first transparent substrate 12, and a black matrix (not shown) for isolating the color filters is added As shown in FIG. The black matrix prevents color interference that may occur at the edges of the color filters.

The second array substrate 20 has a gate electrode SGE formed on the second transparent substrate 22. As the second transparent substrate 22, any one of a plastic film and a glass substrate made of an insulating material having a high light transmittance may be used, like the first transparent substrate 12. The gate electrode SGE is formed at the same time as the subgate line SGL, not shown, as well as the subgate line SGL. The gate electrode SGE and the subgate line SGL are formed by depositing a conductive material containing any one of Cu, Al, AlNd, Au, Ag and Mo on the second transparent substrate 22, Are formed in an integrated form by patterning. The insulating film 24 is formed to have the same thickness on the entire surface of the second transparent substrate 22 on which the gate electrode SGE and the subgate line SGL are formed. The insulating film 24 is formed to have a uniform thickness by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the second transparent substrate 12.

The second array substrate 20 includes a semiconductor material pattern SSP and a vertical common voltage line VCL disposed on the insulating film 24 and drain and source electrodes (SDE, SSE). These drain and source electrodes SDE and SSE constitute a sub-film transistor ST together with a semiconductor material pattern SSP and a gate electrode SGE. A semiconductor material pattern SSP is formed on the insulating film 24 at a position above the gate electrode SGE. The drain electrode SDE is formed simultaneously with the source electrode SSE and the vertical common voltage line VCL in addition to being connected to the vertical common voltage line VCL on the insulating film 24. [ The semiconductor material pattern (SSP) will be formed by depositing a semiconductor material on the entire surface of the insulating film 24 and patterning the deposited semiconductor material layer through a lithographic printing process. Then, a conductive material layer containing any one of Cu, Al, AlNd, Au, Ag and Mo is deposited on the front surface of the insulating film 24 having the semiconductor material pattern SSP. The drain and source electrodes SDE and SSE and the drain electrode SDE are arranged at a predetermined interval on the semiconductor material pattern MSP by patterning the conductive material layer on the insulating film 24 through the lithographic printing process, An integrated vertical common voltage line VCL is formed.

The second array substrate 20 includes an overcoat layer 26 formed on the entire surface of the second transparent substrate 22 having the sub-thin film transistor ST and a vertical common electrode VCE). The vertical common electrode VCE is formed to occupy the remaining pixel region P except for a part of the occupied region of the sub-thin film transistor ST. The vertical common electrode VCE is formed so as to overlap with a part of the source electrode SSE of the sub-thin film transistor ST. This vertical common electrode VCE is electrically connected to the source electrode SSE of the sub-thin film transistor ST by the contact SCT passing through the overcoat layer 26. [ The overcoat layer 26 is formed so that an insulating material such as silicon nitride or silicon oxide is applied to the entire surface of the insulating film 24 having the sub-thin film transistor ST through a coating process to have a flat surface. In the overcoat layer 26, a contact hole exposing a part of the source electrode SSE of the sub-thin film transistor ST is formed. The contact holes are formed by the partial removal of the overcoat layer 26 through the lithographic process. Next, a transparent conductive material such as ITO or IZO is deposited on the entire surface of the overcoat layer 26 exposing a part of the source electrode SSE of the sub-thin film transistor ST. At this time, the transparent conductive material is embedded in the contact hole, and the contact (SCT) will be formed. A layer of a transparent conductive material on the overcoat layer 26 is patterned through a lithographic process to electrically connect to the source electrode SSE of the sub-thin film transistor ST.

The second array substrate 20 may further include a color filter layer (not shown) positioned between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 22. The color filter layers include alternating red, green, and blue filters. Each of the red, green, and blue filters is formed to have a size corresponding to the pixel region. Further, the second array substrate 20 is positioned between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 22, and a black matrix (not shown) for isolating the color filters is added As shown in FIG. The black matrix prevents color interference that may occur at the edges of the color filters.

The first and second array substrates 10 and 20 are bonded together by a sealing material (not shown) such that the pixel electrode PXE and the vertical common electrode VCE face each other. The sealing material separates the first and second array substrates 10 and 20 from each other to secure a space for injecting the liquid crystal material. The distance between the first and second array substrates 10 and 20 (i.e., the distance between the pixel electrode PXE and the vertical common electrode VCE, EPss) Vpds), so that the liquid crystal pixel can be effectively driven. The spacing distance EGss between the first and second array substrates 10 and 20 for effective driving of the liquid crystal pixel is determined by experimenting the light transmission characteristics of the liquid crystal cell CLC with respect to the pixel driving signal Vpds of the back level It has been found that approximately 3.0 to 5.0 mu m or so can be applied. Actually, when a liquid crystal material having an anisotropy of refractive index of 0.11 is injected between the first and second array substrates 10 and 20 and a back-level pixel driving signal Vpds is supplied to the pixel electrode PXE, The light transmittance of the first array substrate 10 and the second array substrate 20 is shown as shown in FIG. 7 depending on the distance EGss between the first and second array substrates 10 and 20. 7, "SD1" indicates the light transmittance of the liquid crystal pixel with respect to the pixel driving signal Vpds of the back level when the distance EGss between the first and second array substrates 10 and 20 is 3.4 m Lt; / RTI > "SD2" represents the light transmission characteristic of the liquid crystal pixel with respect to the pixel driving signal Vpds of the back level when the separation distance EGss between the first and second array substrates 10, 20 is 4.0 μm. "SD3" represents the light transmission characteristic of the liquid crystal pixel with respect to the pixel driving signal Vpds of the back level when the separation distance EGss between the first and second array substrates 10, 20 is 5.0 μm. 7, when the distance EGss between the first and second array substrates 10 and 20 is approximately 3.4 to 4.0 mu m, the light transmission of the liquid crystal pixel to the pixel driving signal Vpds of the back level The characteristics are changed to a form close to linear. In view of this, the sealing material may have a height (or thickness) of about 3.4 to 4.0 mu m so that the separation distance EGss between the first and second array substrates 10 and 20 can be maintained at about 3.4 to 4.0 mu m or so .

With respect to the maximum transmittance of the liquid crystal pixel, the distance (EGss) between the first and second array substrates 10 and 20 and the refractive index anisotropy value of the liquid crystal material have opposite characteristics. In practice, when the distance EGss between the first and second array substrates 10 and 20 is long, a high transmittance of the liquid crystal pixel is obtained only when the liquid crystal material has a low refractive index anisotropy value. On the contrary, when the spacing distance EGss between the first and second array substrates 10 and 20 is short, a high transmittance of the liquid crystal pixel can be obtained only when the liquid crystal material has a high refractive index anisotropy value. In addition, the spacing distance EGss between the first and second array substrates 10 and 20 and the refractive index anisotropy value of the liquid crystal material should be set as small as possible to allow the optical delay of the liquid crystal pixel to be retarded. The amount of optical delay of the liquid crystal pixel is determined by measuring the maximum transmittance characteristic of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material by appropriately selecting the appropriate amount of liquid crystal material according to the separation distance EGss between the first and second array substrates 10, Can be measured together with the refractive index anisotropy value. By this experiment, the optical delay of the liquid crystal pixel was measured to be 380 nm to 440 nm.

8 illustrates the maximum transmittance characteristics of the liquid crystal pixels by the distance EGss between the first and second array substrates 10 and 20 with respect to the refractive index anisotropy value of the liquid crystal material. 8, "RA1" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the spacing distance EGss between the first and second array substrates 10 and 20 is 3.4 m. "RA2" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10, 20 is 4.0 μm. "RA3" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10, 20 is 4.5 μm. "RA4" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the distance EGss between the first and second array substrates 10, 20 is 5.0 μm. 8, when the distance EGss between the first and second array substrates 10 and 20 is 3.4 μm, the refractive index anisotropy value of the liquid crystal material is 0.12, and the first and second array substrates 10, 20) becomes 4.0 탆, 4.5 탆 and 5.0 탆, the refractive index anisotropy values of a suitable liquid crystal material are lowered to 0.10, 0.05 and 0.08. Next, the amount of optical delay in the liquid crystal pixel including the liquid crystal material having the refractive index anisotropic value appropriate for the separation distance EGss between the first and second array substrates 10 and 20 is 3.4 μm, 40 μm, 400 nm, 405 nm and 400 nm at the distance between the first and second array substrates 10 and 20 of 50 m, respectively.

In addition, in the liquid crystal panel of the fast response speed according to the embodiment, a proper potential difference between the vertical common electrode (VCE) and the horizontal common electrode (HCE) should be set in order to minimize light leakage at the time of black level display. For this purpose, the light transmittance of each of the first and second array substrates 10 and 20 according to the difference in potential between the vertical common electrode VCE and the horizontal common electrode HCE was measured. The voltage to be applied between the vertical common electrode (VCE) and the horizontal common electrode (HCE) can be obtained. Actually, in a state where the distance (EPss) between the first and second array substrates 10 and 20 is 3.4 占 퐉 and the refractive index anisotropy value of the liquid crystal material is set to 0.12, the vertical common electrode VCE and the horizontal common electrode (HCE) is varied in a region higher than the voltage of the back level pixel driving signal (Vpds), the light transmission amount of the liquid crystal pixel is measured. As shown in Fig. 9, the light transmittance of the liquid crystal pixel at the time of black level display becomes minimum when a voltage of 8.5 V is supplied between the vertical common electrode (VCE) and the horizontal common electrode (HCE). In this manner, when the distance (EPss) between the first and second array substrates 10 and 20 is 4.0 占 퐉 and the refractive index anisotropy value of the liquid crystal material is 0.10, the light transmittance of the liquid crystal pixel is 9.0V Is minimized when supplied between the vertical and horizontal common electrodes (VCE, HCE). The light transmission amounts of the liquid crystal pixels in the case where the distance (EPss) between the first and second array substrates 10 and 20 are 4.5 탆 and 5.0 탆 and the refractive index anisotropy values of the liquid crystal material are 0.09 and 0.08, Was found to be the minimum when the voltage between the vertical and horizontal common electrodes (VCE, HCE) was supplied.

The maximum transmittance LTRmax of the liquid crystal pixel according to the separation distance EGss between the first and second array substrates 10 and 20 obtained through the above experiments, the refractive index anisotropy value? N of the liquid crystal material, The delay amount? Nd and the high potential vertical common voltage (Vvcomh) can be summarized as shown in Table 1.

EGss (占 퐉) LTRmax Δn Nd (nm) Vvcomh (V) 3.4 0.352562 0.12 408 8.5 4.0 0.461057 0.10 400 9.0 4.5 0.463481 0.09 405 8.5 5.0 0.475367 0.08 400 8.5

As can be seen from FIG. 7 and Table 1, for an efficient liquid crystal panel in which the light transmission characteristic for the back level pixel driving signal Vpds is changed to a more linear form and the optical delay amount can be minimized, It is most preferable that the spacing distance between the second array substrates 10 and 20 is about 4.0 mu m and the liquid crystal material with a light delay amount of about 0.400 nm is used. For this, the refractive index anisotropy value of the liquid crystal material and the voltage between the vertical and horizontal common electrodes (VCE, HCE) are most preferably about 0.10 and about 9.0V. From this point of view, a liquid crystal material having a refractive index anisotropy value in the range of approximately 0.0950 to 0.1050 is most preferable as the liquid crystal material for a liquid crystal panel of a fast response speed according to the embodiment. Therefore, it is preferable that the liquid crystal layer 30 of the liquid crystal panel of the fast response speed according to the embodiment uses any one of Fluoro substitution liquid crystal materials. For example, any one of the liquid crystal materials such as ML-0323, ML-0424, ML-0249 and ML-0567 may be used as the material of the liquid crystal layer 30 of the liquid crystal panel of the fast response speed according to this embodiment will be.

The liquid crystal pixels to be arranged in the matrix form in this manner are individually driven by the horizontal electric field between the pixel electrode PXE and the horizontal common electrode HCE during the display of the lighter grayscale than the lowest grayscale (i.e., black) Is driven by the vertical electric field between the vertical and horizontal common electrodes VCE and HCE. In other words, each of the liquid crystal pixels is driven by an electric field not only in the gradations that are brighter (or higher) than the lowest gradation but also in the case of displaying the lowest gradation. Accordingly, the liquid crystal panel according to the embodiment can respond to the pixel driving signal at a high speed.

FIGS. 10A and 10B are plan views illustrating details of the planar structure of the first and second array substrates included in the liquid crystal panel of the fast response speed according to another embodiment. Although Figs. 10A and 10B show only the planar structure of some liquid crystal pixels (i.e., three liquid crystal pixels) as in Figs. 4A and 4B, all those skilled in the art with respect to the liquid crystal panel disclosed in this specification , It can be easily understood that a plurality of liquid crystal pixels arranged in a matrix form can be implemented by repeating some of the liquid crystal pixels shown in the vertical and horizontal directions.

The first array substrate 40 of FIG. 10A has the same planar structure as the first array substrate 10 of FIG. 4A except that the contact (MCT) is removed. The elements of FIG. 10A having the same function, structure and arrangement as those shown in FIG. 4A will be referred to by the same reference numerals and names. In addition, since the elements of FIG. 10A, which are the same as those shown in FIG. 4A, have already been revealed through the description of FIG. 4A, a description thereof will be omitted.

In the first array substrate 40 of FIG. 10A, the pixel electrodes PXE on the respective pixel regions P are formed in an integrated form so as to be electrically connected to each other. A part of the pixel electrode PXE overlaps with a part of the source electrode MSE of the main thin film transistor MT. The overlapping portions of the pixel electrode PXE and the source electrode MSE of the main thin film transistor MT are in direct contact with each other. Thus, the pixel electrode PXE is electrically connected to the source electrode MSE of the main thin film transistor MT without depending on the contact.

On the other hand, the second array substrate 50 of FIG. 10B has the same planar structure as the second array substrate 20 of FIG. 4B except that the contact (SCT) is removed. The components of FIG. 10B having the same function, structure and arrangement as those shown in FIG. 4B will be referred to by the same reference numerals and names. Further, since the components of Fig. 10B, which are the same as those shown in Fig. 4B, have already been revealed through the description of Fig. 4B, a description thereof will be omitted.

A part of the vertical common electrode VCE on each pixel region P overlaps with a part of the source electrode SSE of the sub-thin film transistor ST in the second array substrate 50 of Fig. 10B. The overlapping portions of the vertical common electrode (VCE) and the source electrode (SSE) of the sub-thin film transistor (ST) are in direct contact with each other. Thus, the vertical common electrode VCE is electrically connected to the source electrode SSE of the sub-thin film transistor ST without depending on the contact.

11 is a view for explaining a cross-sectional structure of a liquid crystal panel of a fast response speed according to another embodiment. 11 is a cross-sectional view of the first and second array substrates 40 and 50 taken along line II-II 'in FIG. The liquid crystal panel of Fig. 11 has a liquid crystal material layer 60 injected between the first and second array substrates 40 and 50. Fig.

The first array substrate 40 has horizontal common electrodes HCE and an interlayer insulating film 44 sequentially formed on the first transparent substrate 42. The first transparent substrate 42 may be formed of a plastic film or a glass substrate made of an insulating material having a high light transmittance. The horizontal common electrode HCE is connected to the horizontal common voltage line HCL (not shown), and is formed in an integrated form with the horizontal common voltage line HCL. The horizontal common electrode HCE and the horizontal common voltage line HCL are formed by depositing ITO or IZO and a transparent conductive material (not shown) on the first transparent substrate 42, And patterned through the process, they are formed into an integrated form. An interlayer insulating film 44 is formed on the entire surface of the first transparent substrate 42 on which the horizontal common electrode HCE and the horizontal common voltage line HCL are formed to have a planarizing surface. The interlayer insulating film 44 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the first transparent substrate 42.

The first array substrate 40 has a gate electrode MGE formed on the interlayer insulating film 44. [ The gate electrode MGE is connected to the main gate line MGL (not shown) and formed simultaneously with the main gate line MGL. The gate electrode MGE and the main gate line MGL are formed by depositing a conductive material containing any one of Cu, Al, AlNd, Au, Ag and Mo on the interlayer insulating film 44, And is patterned through a printing process. A gate insulating film 46 is formed on the entire surface of the interlayer insulating film 44 on which the gate electrode MGE and the main gate line MGL are formed to have the same thickness. The gate insulating film 46 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the gate electrode MGE, the main gate line MGL, and the interlayer insulating film 44.

The first array substrate 40 includes a semiconductor material pattern MSP and a data line DL disposed on the gate insulating film 46, drain and source electrodes (MDE, MSE), and pixel electrodes PXE electrically connected to the source electrode MSE. These drain and source electrodes MDE and MSE constitute the main thin film transistor MT together with the semiconductor material pattern MSP and the gate electrode MGE. A semiconductor material pattern MSP is formed on the gate insulating film 46 at a position above the gate electrode MGE. The drain electrode MDE is formed simultaneously with the source electrode MSE and the data line DL as well as connected to the data line DL on the gate insulating film 46. [ The pixel electrodes are electrically connected to each other within the pixel region P while being electrically isolated from the pixel electrodes PXE on the other pixel region P. [ A part of the pixel electrode PXE in each pixel region P overlaps with a part of the source electrode MSE of the main thin film transistor MT. The overlapping portions of the pixel electrode PXE and the source electrode MSE of the main thin film transistor MT are in direct contact so that the pixel electrode PXE is electrically connected to the source electrode MSE of the main thin film transistor MT. The pixel electrodes PXE are in direct contact with the gate insulating film 46 and are located on the same layer as the data lines DL. Further, the pixel electrodes PXE are alternately arranged with the horizontal common electrodes HCE under the gate insulating film 46. [

The semiconductor material pattern MSP will be formed by depositing a semiconductor material on the entire surface of the gate insulating film 46 and patterning the deposited semiconductor material layer through a lithographic printing process. Then, a conductive material layer containing any one of Cu, Al, AlNd, Au, Ag and Mo is deposited on the entire surface of the gate insulating film 46 having the semiconductor material pattern MSP. The drain and source electrodes MDE and MSE and the gate insulating film 46 are spaced apart from each other on the semiconductor material pattern MSP by patterning the conductive material layer on the insulating film 14 through the lithographic printing process, And a data line DL integrated with the drain electrode MDE is formed. Next, a semiconductor material pattern (MSP) A photoresist is applied to the entire surface of the gate insulating film 46 on which the data line DL, the drain and the source electrodes MDE and MSE are formed. The photoresist layer is patterned through exposure and development to expose a gate insulating film 46 corresponding to a region where pixel electrodes PXE including a part of the source electrode MSE are to be located. A transparent insulating material such as ITO or IZO is deposited on the photoresist pattern and the gate insulating film 46 exposed by the photoresist pattern to a uniform thickness. Finally, the transparent insulating material on the photoresist pattern is removed together with the photoresist pattern through the cleaning process so that pixel electrodes PXE are formed which are in direct contact with a part of the source electrode MSE and the gate insulating film 46 .

The pixel electrodes PXE are spaced apart from the horizontal common electrode HCE by a predetermined distance in order to improve the light transmittance according to the gradation of the image. The spacing distance EGph between the pixel electrode PXE and the horizontal common electrode HCE may be set to approximately 3.0 to 5.0 mu m. Accordingly, the interlayer insulating film 44 and the gate insulating film 46 can be formed so that their total thickness has a value within a range of approximately 3.0 to 5.0 mu m. The interlayer insulating film 44 and the gate insulating film 46 are formed to have a roughness of about 4.0 占 퐉 so that the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE can be kept about 4.0 占 퐉 in order to maximize the light transmittance. Lt; RTI ID = 0.0 > um. ≪ / RTI >

The first array substrate 40 includes a first array substrate 40 and a second array substrate 40. The first array substrate 40 includes a first substrate 40 and a second substrate 40. The first substrate 40 includes a horizontal common electrode VCE and a horizontal common voltage line VGL, A color filter layer (not shown) positioned between the insulating films 44 may be additionally provided. The color filter layers include alternating red, green, and blue filters. Each of the red, green, and blue filters is formed to have a size corresponding to the pixel region. The first array substrate 40 is connected to the horizontal common electrode VCE and the horizontal common voltage line VGL and the first transparent substrate 42 or between the horizontal common electrode VCE and the horizontal common voltage line VGL, A black matrix (not shown) for isolating the color filters as well as the insulating layer 44 may be additionally provided. The black matrix prevents color interference that may occur at the edges of the color filters.

The second array substrate 50 has a gate electrode SGE formed on the second transparent substrate 52. As the second transparent substrate 52, any one of a plastic film made of an insulating material having good light transmittance and a glass substrate can be used, like the first transparent substrate 42. The gate electrode SGE is formed at the same time as the subgate line SGL, not shown, as well as the subgate line SGL. The gate electrode SGE and the subgate line SGL are formed by depositing a conductive material layer containing any one of Cu, Al, AlNd, Au, Ag and Mo on the second transparent substrate 52, By patterning the material, into an integrated form. An insulating film 54 is formed on the entire surface of the second transparent substrate 52 on which the gate electrode SGE and the subgate line SGL are formed. The insulating film 54 is formed to have a uniform thickness by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the second transparent substrate 52.

The second array substrate 50 includes a semiconductor material pattern SSP and a vertical common line VCL located on the insulating film 54, drain and source electrodes arranged at regular intervals on the semiconductor material pattern SSP SDE, and SSE), and a vertical common electrode (VCE). These drain and source electrodes SDE and SSE constitute a sub-film transistor ST together with a semiconductor material pattern SSP and a gate electrode SGE. A semiconductor material pattern SSP is formed on the insulating film 54 at a position above the gate electrode SGE. The drain electrode SDE is formed simultaneously with the source electrode SSE and the vertical common voltage line VCL in addition to being connected to the vertical common voltage line VCL on the insulating film 24. [ The vertical common electrode VCE occupies the remaining pixel region P except for a part of the occupied region of the sub-thin film transistor ST. The vertical common electrode VCE overlaps with a part of the source electrode SSE of the sub-thin film transistor ST. The overlapping portions of the vertical common electrode VCE and the source electrode SSE of the sub thin film transistor ST are in direct contact with each other so that the vertical common electrode VCE is electrically connected to the source electrode SSE of the sub- . The vertical common electrode VCE is in direct contact with a portion of the source electrode SSE of the sub-thin film transistor ST and the insulating film 54 through a lift-off process, As shown in FIG.

The semiconductor material pattern (SSP) will be formed by depositing a semiconductor material over the entire surface of the insulating film 54 and patterning the deposited semiconductor material layer through a lithographic printing process. Next, a conductive material layer containing any one of Cu, Al, AlNd, Au, Ag and Mo is deposited on the entire surface of the insulating film 54 having the semiconductor material pattern SSP. The drain and source electrodes SDE and SSE and the drain electrode SDE are spaced apart from each other on the semiconductor material pattern MSP by patterning the conductive material layer on the insulating film 54 through the lithographic printing process, An integrated vertical common voltage line VCL is formed. Next, a photoresist is applied to the entire surface of the slimming film 54 on which the semiconductor material pattern SSP, the vertical common voltage line VCL, the drain and the source electrodes SDE and SSE are formed. The photoresist layer is patterned through exposure and development to expose the insulating film 54 corresponding to the region where the vertical common electrode VCE including a part of the source electrode MSE is to be located. A transparent insulating material such as ITO or IZO is deposited to a uniform thickness on the photoresist pattern and the insulating film 54 exposed by the photoresist pattern. Finally, the transparent insulating material on the photoresist pattern is removed together with the photoresist pattern through the cleaning process to form a vertical common electrode (VCE) which is in direct contact with a part of the source electrode MSE and the insulating film 54. [

The second array substrate 50 may further include a color filter layer (not shown) between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 52. The color filter layers include alternating red, green, and blue filters. Each of the red, green, and blue filters is formed to have a size corresponding to the pixel region. Further, the second array substrate 50 is positioned between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 52, and a black matrix (not shown) for isolating the color filters is added As shown in FIG. The black matrix prevents color interference that may occur at the edges of the color filters.

The pixel electrodes PXE and the vertical common electrodes VCE are attached to each other in the first and second array substrates 40 and 50 by a sealing material (not shown). The sealing seal separates the first and second array substrates 40 and 50 so that the injection space of the liquid crystal material 60 can be ensured. The spacing distance between the first and second array substrates 40 and 50 (that is, the distance between the pixel electrode PXE and the vertical common electrode VCE, EPss) Vpds) can be set to approximately 3.4 to 4.0 mu m so that the liquid crystal pixel can be driven effectively. Accordingly, the sealing material separating the first and second array substrates 40 and 50 will be formed to have a height (or thickness) of about 3.4 to 4.0 mu m. For an efficient liquid crystal panel in which the light transmission characteristic for the back-level pixel driving signal Vpds is changed to a more linear form and the amount of optical delay can be minimized, for the liquid crystal panel of the first and second array substrates 40 and 50 It is most preferable that the sealing material is formed to have a height (or thickness) of about 4.0 占 퐉 so that the separation distance EGss is about 4.0 占 퐉. As the constituent material of the liquid crystal layer 60, liquid crystal materials having a refractive index anisotropy value of about 0.08 to about 012, which causes a light delay amount of about 400 to 408 nm, may be used, but a light retardation of about 400 nm A liquid crystal material having a refractive index anisotropy value of about 0.10 is most preferable. For this purpose, any one of the Fluoro substitution-based liquid crystal materials having refractive index anisotropy values in the range of about 0.0950 to 0.1050 will be used as a constituent material of the liquid crystal layer 60. Such fluoro substitution-based liquid crystal materials include liquid crystal materials such as ML-0323, ML-0424, ML-0249 and ML-0567. Further, as the voltage applied between the vertical and horizontal common electrodes VCE and HCE, approximately 8.5 to 9.0 V may be used, but approximately 9.0 V is most preferable.

In the liquid crystal panel according to another embodiment of the present invention, the liquid crystal pixels arranged in the form of a matrix are individually arranged in a horizontal electric field between the pixel electrode (PXE) and the horizontal common electrode (HCE) While it is driven by a vertical electric field between the vertical and horizontal common electrodes (VCE, HCE) at the time of displaying the lowest gray level. In other words, each of the liquid crystal pixels is driven by an electric field not only in the gradations that are brighter (or higher) than the lowest gradation but also in the case of displaying the lowest gradation. Accordingly, the liquid crystal panel according to another embodiment can respond to the pixel driving signal at a high speed.

12 is a block diagram for explaining a liquid crystal display of a fast response speed according to an embodiment in detail. 12 has a main gate driver 102A connected to a plurality of main gate lines MGL1 to MGLn on the liquid crystal panel 100, a plurality of data lines DL1 (DL1) on the liquid crystal panel 100, And a timing controller 106 for controlling the operation timings of the main gate driver 102A and the data driver 104. [ The liquid crystal panel 100 includes a plurality of subgate lines SGL1 to SGLn and a plurality of vertical common voltage lines VCL1 to VCLm (not shown) in addition to a plurality of main gate lines MGL1 to MGLn and a plurality of data lines DL1 to DLm. ). The liquid crystal panel 100 is divided into sub-gate lines SGL1 to SGLn and vertical common voltage lines VCL1 to VCLm by main gate lines MGL1 to MGLn and data lines and / And is divided into mxn pixel regions in the form of a matrix. In each of these pixel regions, a liquid crystal pixel LPX including main and sub-thin film transistors MT and ST and a liquid crystal cell CLC is formed. The liquid crystal cells CLC are electrically common-connected to the horizontal common line HCL. The structure, operation, effect, and the like of the liquid crystal panel 100 will be omitted from the detailed description of the liquid crystal panel 100, as already clearly disclosed with reference to FIGS. 1 and 3. FIG.

The main gate driver 102 is mounted on the liquid crystal panel 100 The main scan lines MGL1 to MGLn sequentially generate main scan signals corresponding to the number n of main gate lines MGL to be sequentially enabled. The main scan signals have a waveform in which the pulse having the width corresponding to the period of the horizontal synchronizing signal Hsync and the gate high voltage Vgh having the high potential are sequentially shifted by that width. In other words, the main gate driver 102A allows the gate high voltage (Vgh) to be applied to one main gate line (MGL) to be enabled while the remaining main gate lines (MGL) are supplied with a low potential gate low voltage Vgl) is supplied. The liquid crystal pixels LPX responding to the main scan signal are charged with the pixel drive signals Vpds on the data lines DL1 to DLm by one line. In order to generate these main scan signals, the main gate driver 102A responds to a gate control signal (GCS) from the timing controller 106. [ The gate control signal GCS includes a gate start pulse GSP generated every period of the vertical synchronization signal Vsync and at least one gate shift clock GSC having the same frequency as the horizontal synchronization signal Hsync .

The data driver 104 converts pixel data VDr of one line from the timing controller 106 into analog data of one line each time one of the main gate lines MGL on the liquid crystal panel 100 is enabled And supplies the converted pixel driving signals Vpds to the data lines DL1 to DLm on the liquid crystal panel 100 by converting them into pixel driving signals Vpds. The line-by-line pixel data VDr is supplied to the data driver 104 from an external video data source (for example, a graphics module of a computer system or a video demodulation module of a television receiver) without passing through the timing controller 106. [ As shown in FIG. The data driver 104 responds to the data control signal DCS from the timing controller 106 in order to convert the pixel data VDr of one line into the pixel driving signal Vpds. The data control signal DCS includes a data enable signal DEN having the same frequency as the horizontal synchronizing signal Hsync and a data clock DCLK indicating a transfer period of the pixel data.

The timing controller 106 is connected to an external video data source (e.g., a graphics module of a computer system or a video demodulation module of a television receiver) to control the operation timing of the main gate driver 102A and the data driver 104. [ The synchronization signal SYNC is input from the input terminal of the memory device. The synchronizing signal SYNC supplied to the timing controller 106 includes a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DEN and a data clock DCLK. The timing controller 106 generates a gate control signal GCS for controlling the operation timing of the main gate driver 102A and a gate control signal GCS for controlling the operation timing of the data driver 104 by using these synchronization signals SYNC. And generates a data control signal DCS. In addition, the timing controller 106 can sequentially input pixel data (VDf) from an external video data source, one frame at a time. The pixel data VDf for one frame is rearranged by the timing controller 106 so as to be divided into pixel data VDr for one line. The pixel data VDf for the rearranged frame is supplied to the data driver 104 in units of one line so as to be synchronized with the data control signal DCS.

The liquid crystal display device with a fast response speed according to the embodiment includes a sub gate driver 102B connected to a plurality of sub gate lines SGL1 to SGLn on the liquid crystal panel 100, And a common voltage generator 110 connected to the line HCL. The sub gate driver 102B is connected to the number of sub gate lines SGL that alternately enable the sub gate lines SGL1 to SGLn on the liquid crystal panel 100 to be synchronized with the corresponding main gate lines MGL (n). < / RTI > The sub scan signals have a waveform whose period and timing coincide with the main scan signals generated by the main gate driver 102A. The liquid crystal pixels LPX responsive to the sub scan signal charges the pixel drive signal Vpds by one line and charges the vertical common voltage Vvcoml or Vvcomh on the vertical common voltage lines VCL1 to VCLm . In order to generate these sub scan signals, the sub gate driver 102A responds to the gate control signal GCS from the timing controller 106 in the same manner as the main gate driver 102A. The sub gate lines SGL1 to SGLn on the liquid crystal panel 100 may be driven by the main scan signal from the main gate driver 102A together with the corresponding main gate lines MSL1 to MSLn. In this case, the sub gate driver 102B can be removed, but the load on the main gate driver 102A becomes large.

The common voltage generating unit 110 generates the horizontal common voltage Vhcom corresponding to the base voltage level of the pixel driving signal Vpds. The horizontal common voltage Vhcom generated in the common voltage generator 110 is supplied to all the liquid crystal pixels LPX on the liquid crystal panel 100 via the horizontal common voltage line HCL on the liquid crystal panel 100 In detail, the horizontal common electrode HCE of all the liquid crystal cells CLC). The common voltage generating unit 110 generates a common voltage Vhcom that is higher than the highest voltage level (that is, the voltage level corresponding to the back level) of the pixel driving signal Vpds based on the horizontal common voltage Vhcom And generates a voltage Vvcomh. The vertical common voltage Vvcomh at a high electric potential may be set at a voltage level approximately 8.5 to 9.5 V higher than the vertical common voltage Vhcom but is preferably set to be higher by about 9.0 V than the horizontal common voltage Vhcom It is good.

Furthermore, the liquid crystal display device of a fast response speed according to the embodiment includes a data converter 108 for inputting pixel data VDr for one line from the timing controller 106, And a vertical common voltage line driver 112 connected to the common voltage lines VCL1 to VCLm. The data converter 108 converts each line of pixel data from the timing controller 106 into black level control data. The black level control data (CVDr) for one line converted by the data converter 108 is sequentially supplied to the vertical common voltage line driver 112. The black level control data is enabled by a logical value of "1" (or "0") when the pixel data is a black level tone value (for example, "000000" in the case of 6-bit pixel data). Alternatively, when the pixel data has a gradation value (for example, "at least 000001" in the case of 6-bit pixel data) higher than the black level, the black level control data is set to a logical value of "0" And is disabled. In order to convert such pixel data into black level control data, the data converter 108 includes a NOR gate or an OR gate for performing a NOR operation or an OR operation.

The vertical common voltage line driver 112 outputs black level control data (CVDr) for one line from the data converter 108 whenever one of the sub gate lines SGL on the liquid crystal panel 100 is enabled, A vertical common voltage Vvcoml having a high potential equal to the vertical common voltage Vvcomh or the horizontal common voltage Vhcom is supplied to the vertical common voltage lines VCL1 to VCLm on the liquid crystal panel 100, . For example, when the black level control data has a logic value of "1" (or "0"), the vertical common voltage line driver 112 applies a common voltage to the vertical common voltage line VCL So that the vertical common voltage Vvcomh at a high potential from the voltage generating portion 110 is supplied. Alternatively, if the black level control data has a logical value of "0" (or "1"), the vertical common voltage line driver 112 supplies the vertical common voltage line VCL corresponding to the black level control data So that the horizontal common voltage Vhcom from the common voltage generator 110 is supplied as the vertical common voltage Vvcoml of the potential. In order to switch the low potential and the high potential vertical common voltages Vvcoml and Vvcomh to the vertical common voltage lines VCL1 to VCLm according to the black level control data CVDr for one line, (112) responds to the data control signal (DCS) from the timing controller (106) in the same manner as the data driver (104).

Each of the liquid crystal pixels LPX on the liquid crystal panel 100 performing the charging operation for one line as the corresponding main and sub gate lines MGL and SGL are enabled at the same time, (Vvcoml or Vvcomh) of the low potential or the high potential on the corresponding vertical common voltage line (VCL) together with the pixel driving signal (Vpds). When each of the liquid crystal pixels LPX is charged with the pixel drive signal Vpds of a voltage higher than the black level and the vertical common voltage Vvcoml of a low potential, (Vpds), and passes the light amount corresponding to the voltage of the pixel driving signal (Vpds). Thus, the liquid crystal pixel displays the gray level corresponding to the voltage of the pixel drive signal Vpds. On the other hand, when each of the liquid crystal pixels LPX is charged with the pixel driving signal Vpds of the black level and the vertical common voltage Vvcomh of the high potential, the liquid crystal molecules constituting the liquid crystal cell CLC have the high potential And returns quickly to the initial arrangement state by the vertical common voltage (Vvcomh) so that light is not transmitted. At this time, the liquid crystal pixel LPX displays black.

As described above, the liquid crystal display according to the embodiment allows the liquid crystal pixels to be driven by the pixel driving signal Vpds individually at the time of displaying the grayscale lighter than the lowest grayscale (i.e., black), while at the time of displaying the lowest grayscale And is initialized by the vertical common voltage (Vvcomh) of high potential. In other words, in the liquid crystal display according to the embodiment, the liquid crystal pixels are controlled by the electric field even in the display of the lowest gray level as well as the gray level that is brighter (or higher) than the lowest gray level. Accordingly, the liquid crystal display device according to the embodiment can display an image responding at a high speed corresponding to the video data. As a result, the liquid crystal display device according to the embodiment can minimize image deterioration and blurring phenomenon. Furthermore, the liquid crystal display device according to the embodiment can improve the image quality.

As described above, embodiments have been described focusing on liquid crystal pixels, liquid crystal panels, and liquid crystal display devices of the fast response speeds shown in FIGS. 1 to 12. However, those skilled in the art It will be understood by those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the technical idea and scope disclosed in the embodiments should not be limited to the description of the embodiment but should be set by the matters described in the appended claims.

1 is a circuit diagram for explaining a liquid crystal pixel of a fast response speed according to an embodiment in detail.

2 is a waveform diagram for explaining a waveform of signals supplied to the liquid crystal pixel of FIG.

3 is a circuit diagram schematically illustrating the configuration of a liquid crystal panel of a fast response speed according to an embodiment.

4A and 4B are plan views illustrating in detail the planar structure of the first and second array substrates included in the liquid crystal panel of the fast response speed according to the embodiment.

FIG. 5 is a cross-sectional view of the first and second array substrates of FIG. 4 taken along the line I-I 'in order to explain the cross-sectional structure of a liquid crystal panel of a fast response speed in the embodiment in detail.

6, And is a characteristic diagram for explaining light transmission characteristics of a liquid crystal pixel according to a distance between a pixel electrode and a horizontal common electrode with respect to a back-level pixel driving signal.

Figure 7 FIG. 4 is a characteristic view for explaining light transmission characteristics of a liquid crystal pixel according to a distance between the first and second array substrates with respect to a back-level pixel driving signal; FIG.

8 is a characteristic diagram for explaining maximum transmittance characteristics of a liquid crystal pixel according to the distance between the first and second array substrates with respect to the refractive index anisotropy value of the liquid crystal material.

9 is a graph showing the relationship between the potential difference between the vertical common electrode (VCE) and the horizontal common electrode (HCE) in a state where the distance between the first and second array substrates is 3.4 占 퐉 and the refractive index anisotropy value of the liquid crystal material is set to 0.12. FIG. 5 is a characteristic diagram for comparing and explaining the light transmission characteristics of a liquid crystal pixel with respect to FIG.

10A and 10B are plan views illustrating in detail the planar structure of the first and second array substrates included in the liquid crystal panel of the fast response speed according to the embodiment.

11 is a cross-sectional view taken along the line II-II 'of the first and second array substrates of FIG. 10 in order to explain a cross-sectional structure of a liquid crystal panel having a fast response speed according to an embodiment.

12 is a block diagram for explaining a liquid crystal display of a fast response speed according to an embodiment in detail.

DESCRIPTION OF REFERENCE NUMERALS

10, 40: first array substrate 12, 42: first transparent substrate

14, 24, 54: insulating film 16: protective layer

20, 50: second array substrate 22, 52: second transparent substrate

26: overcoat layer 44: interlayer insulating film

46: gate insulating film 100: liquid crystal panel

102A: main gate driver 102B: sub gate driver

104: Data driver 106: Timing controller

108: Data converter 110: Common voltage generator

112: vertical common line driver

Claims (21)

A liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel drive signal to be supplied from the data line to the pixel electrode of the liquid crystal cell in response to a scan signal on the gate line; And a second switch element for switching a vertical common voltage to be supplied from a vertical common line to a vertical common electrode of the liquid crystal cell in response to the scan signal on the gate line, Wherein the vertical common voltage has a high potential level higher than a maximum voltage level of the pixel driving signal and a low potential level corresponding to a voltage on the horizontal common voltage line, The vertical common voltage When the pixel driving signal has a black level voltage, And when the pixel driving signal is higher than the black level voltage, the liquid crystal pixel has the low potential level. delete delete The method according to claim 1, Wherein the gate line includes main and sub gate lines, The first switch element responds to a main scan signal on the main gate line, And the second switch element responds to a sub-scan signal on the sub-gate line. Each of the unit areas divided by a plurality of main gate lines and a plurality of data lines intersecting with each other includes a horizontal common electrode common-connected to the horizontal common voltage line, a pixel electrode alternately arranged with the horizontal common electrode, A main gate line, and a data line and A first substrate on which a main thin film transistor connected between pixel electrodes is formed; A plurality of subgate lines opposed to the main gate lines and a plurality of vertical common voltage lines opposed to the data lines, A second substrate formed with a vertical common electrode located in each of the regions, and a sub-thin film transistor connected between the corresponding sub gate line, a corresponding vertical common voltage line, and a corresponding horizontal common electrode; And And a liquid crystal layer disposed between the pixel and the horizontal common electrode of the first substrate and the vertical common electrode of the second substrate, A vertical common voltage to be supplied to the vertical common electrode is higher than a voltage level on the horizontal common voltage line and a high electric potential level that is higher than a maximum voltage level of the pixel driving signal by comparing the pixel driving signal to be supplied to the pixel electrode with a black level voltage Lt; RTI ID = 0.0 > low < / RTI & The vertical common voltage When the pixel driving signal has a black level voltage, And when the pixel driving signal is higher than the black level voltage, the liquid crystal panel has the low potential level. 6. The method of claim 5, Wherein the pixel electrode and the horizontal common electrode are spaced apart from each other by 3.0 to 5.0 mu m. 6. The method of claim 5, Wherein the pixel electrode and the horizontal common electrode are spaced apart from each other by 4.0 mu m. 6. The method of claim 5, Wherein the first and second substrates are spaced apart from each other in a range of 3.4 to 5.0 mu m.        6. The method of claim 5, Wherein the first and second substrates are spaced apart from each other by 4.0 mu m. 6. The method of claim 5, Wherein the liquid crystal layer comprises a liquid crystal material having a light delay amount in the range of 380 to 440 nm. 6. The method of claim 5, Wherein the liquid crystal layer comprises a liquid crystal material with a light delay amount of 400 nm. 6. The method of claim 5, Wherein the liquid crystal layer comprises any one of Fluoro substitution liquid crystal materials. 6. The method of claim 5, Wherein the vertical common voltage line is selectively supplied with a low potential voltage corresponding to a voltage supplied to the horizontal common line and a high potential voltage having a voltage higher than the low potential voltage by 9.0V. 6. The method of claim 5, And the horizontal common electrode is located in the same layer as the gate line. 6. The method of claim 5, And the horizontal common electrode is located below the gate line. A plurality of main gate lines and a plurality of data lines intersecting with each other to divide unit areas, a horizontal common electrode provided in each of the unit areas to be connected to a horizontal common voltage line, a pixel electrode arranged alternately with the horizontal common electrode, Corresponding main gate and data lines and Forming a main thin film transistor connected between pixel electrodes on a first substrate; A plurality of subgate lines opposed to the main gate lines, a plurality of vertical common voltage lines opposed to the data lines, a unit divided by the subgate lines and the vertical common voltage lines Forming a sub-thin film transistor on the second substrate, the sub-thin film transistor being connected between a corresponding one of the sub-gate lines, a corresponding vertical common voltage line and a corresponding horizontal common electrode; Disposing the first and second substrates such that the pixel and the horizontal common electrode face the vertical common electrode; And And injecting a liquid crystal material between the first and second substrates, A vertical common voltage to be supplied to the vertical common electrode is higher than a voltage level on the horizontal common voltage line and a high electric potential level that is higher than a maximum voltage level of the pixel driving signal by comparing the pixel driving signal to be supplied to the pixel electrode with a black level voltage Lt; RTI ID = 0.0 > low < / RTI & The vertical common voltage When the pixel driving signal has a black level voltage, And when the pixel driving signal is higher than the black level voltage, the liquid crystal panel has the low electric potential level. A liquid crystal cell arranged in each unit region divided by a plurality of gate lines and a plurality of data lines, a horizontal common electrode provided in each of the unit regions so as to be connected to a horizontal common voltage line, A first switch element for selectively connecting the pixel electrodes of the liquid crystal cells corresponding to the corresponding data lines in response to the scan signals on the corresponding gate lines and arranged alternately with the horizontal common electrodes, A liquid crystal panel having a second switch element for selectively connecting a vertical common line and a vertical common electrode of a corresponding liquid crystal cell in response to the scan signal on the line; A data converter for converting the pixel data stream into a black level control data stream; A gate driver sequentially driving the gate lines on the liquid crystal panel; A data driver for driving the data lines in response to a pixel data stream; And And a vertical common line driver for selectively driving each of the plurality of vertical common voltage lines in response to the black level control data stream, A vertical common voltage to be supplied to the vertical common electrode is higher than a voltage level on the horizontal common voltage line and a high electric potential level that is higher than a maximum voltage level of the pixel driving signal by comparing the pixel driving signal to be supplied to the pixel electrode with a black level voltage Lt; RTI ID = 0.0 > low < / RTI & Wherein the black level control data has an enable value when the pixel data has black gradation. delete 18. The method of claim 17, Wherein the data converter comprises a logic circuit for performing NOR and OR operations on the pixel data. Converting the pixel data stream into a black level control data stream; Sequentially driving a plurality of gate lines on a liquid crystal panel; Driving a plurality of data lines on the liquid crystal panel in response to a pixel data stream; And And selectively driving each of the plurality of vertical common voltage lines on the liquid crystal panel corresponding to the data lines in response to the black level control data stream. The liquid crystal display device according to claim 20, A liquid crystal cell disposed in each of the plurality of gate lines and the unit regions divided by the plurality of data lines; A first switch element for selectively connecting a pixel electrode of a corresponding liquid crystal cell to a corresponding data line in response to a scan signal on a corresponding gate line; And And a second switch element for selectively connecting a vertical common line of a corresponding liquid crystal cell to a corresponding vertical common line in response to the scan signal on a corresponding gate line.

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