KR20090048745A - Liquid crystal pixel and panel and display device including the same - Google Patents

Abstract

A liquid crystal pixel capable of quickly responding to an electrical signal is disclosed.

The liquid crystal pixel includes a liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel driving signal to be supplied to a pixel electrode of the liquid crystal cell from a data line in response to a scan signal on a gate line; And a second switch element for switching a vertical common voltage to be supplied to a vertical common electrode of the liquid crystal cell from a vertical common line in response to the scan signal on the gate line.

Vertical electric field, horizontal electric field, response speed, liquid crystal, transverse mode common electrode, longitudinal mode common electrode, return time.

Description

Liquid Crystal Pixel and Panel and Display Device including the same}

The present specification relates to a liquid crystal pixel displaying a flash point by controlling the light transmittance of the liquid crystal. In addition, the present disclosure relates to a liquid crystal panel and a liquid crystal display device including the liquid crystal pixel.

A typical liquid crystal pixel adjusts an amount of light passing through a liquid crystal layer in response to an electrical signal to display a flash point corresponding to pixel data. The liquid crystal molecules included in the liquid crystal layer are rearranged in the initial alignment state (eg, horizontal or vertical alignment state) to the formation direction of the electric field (eg, vertical or horizontal direction) to control the amount of transmitted light. When the electric field is removed, the liquid crystal molecules of the liquid crystal layer return to the initial alignment state from the rearranged state. The return to the initial alignment state of the liquid crystal molecules proceeds not by the electric field but by the elastic force of the liquid crystal molecules, the rotational viscosity of the liquid crystal molecules, and the anchoring energy between the alignment film and the liquid crystal molecules. The elastic force of the liquid crystal molecules, the rotational viscosity of the liquid crystal molecules, and the anchoring energy between the alignment film and the liquid crystal molecules are significantly smaller than the electric field energy.

For this reason, the rate of return of the liquid crystal molecules to the initial alignment state is inevitably slower than the rearrangement rate. The slow recovery speed of the liquid crystal molecules acts as a factor in reducing the response speed of the liquid crystal pixel to the electrical signal. Even in a liquid crystal panel in which liquid crystal pixels are arranged in a matrix form, the response speed of an image to video data is inevitably limited. In addition, deterioration and blurring of outlines and colors may occur in an image displayed by a liquid crystal display using a liquid crystal panel. For this reason, the liquid crystal display device has no choice but to degrade the image quality.

Accordingly, the present specification will provide an embodiment of a liquid crystal pixel that can respond more quickly to an electrical signal.

In the present specification, embodiments of a liquid crystal panel and a method of manufacturing the same that can respond more quickly to an electrical signal will be provided.

Furthermore, the present specification will provide embodiments of a liquid crystal display and a driving method thereof capable of improving image quality.

In an embodiment, a liquid crystal pixel includes a liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel driving signal to be supplied to a pixel electrode of the liquid crystal cell from a data line in response to a scan signal on a gate line; And a second switch element for switching a vertical common voltage to be supplied to a vertical common electrode of the liquid crystal cell from a vertical common line in response to the scan signal on the gate line.

The vertical common voltage may selectively have a high potential level higher than the maximum voltage level of the pixel driving signal and a low potential level corresponding to the voltage on the horizontal common voltage line according to the voltage of the pixel driving signal. The vertical common voltage maintains the high potential level when the pixel drive signal has a black level voltage, while the vertical common voltage has the low potential level when the pixel drive signal is higher than the black level voltage.

The gate line may include a main and a sub gate line. In this case, the first switch element will respond to the main scan signal on the main gate line, and the second switch element will respond to the sub scan signal on the sub gate line.

According to an exemplary embodiment, a liquid crystal panel includes a horizontal common electrode common-connected to a horizontal common voltage line in each of the unit regions divided by a plurality of main gate lines and a plurality of data lines that cross each other, and alternately with the horizontal common electrode. Arrayed pixel electrodes, and corresponding main gate lines, and data lines; A first substrate having a main thin film transistor connected between the pixel electrodes; A unit divided by a plurality of sub gate lines facing the main gate lines and a plurality of vertical common voltage lines facing the data lines. A second substrate having a vertical common electrode positioned in each of the regions, and a sub thin film transistor connected between a corresponding sub gate line, a corresponding vertical common voltage line, and a corresponding horizontal common electrode; And a liquid crystal layer disposed between the pixel and the horizontal common electrode of the first substrate and the vertical common electrode of the second substrate.

According to an exemplary embodiment, a liquid crystal panel manufacturing method includes a plurality of main gate lines, a plurality of data lines, and a horizontal common electrode provided in each of the unit regions so as to be connected to a horizontal common voltage line. A pixel electrode alternately arranged with the electrode, and corresponding main gate and data lines; Forming a main thin film transistor connected between the pixel electrodes on the first substrate; A unit divided by a plurality of sub gate lines facing the main gate lines, a plurality of vertical common voltage lines facing the data lines, and these sub gate lines and vertical common voltage lines Forming on the second substrate a vertical common electrode located in each of the regions and a sub thin film transistor connected between a corresponding sub gate line, a corresponding vertical common voltage line and a corresponding horizontal common electrode; Disposing the first and second substrates such that the pixel and the horizontal common electrode face the vertical common electrode; And injecting a liquid crystal material between the first and second substrates.

In an exemplary embodiment, a liquid crystal display includes a liquid crystal cell disposed in each of unit regions divided by a plurality of gate lines and a plurality of data lines, vertical common voltage lines corresponding to the data lines, and corresponding gate lines. A first switch element for selectively coupling a pixel electrode of a corresponding liquid crystal cell in response to a scan signal on the corresponding liquid crystal cell, and a liquid crystal corresponding to a corresponding vertical common line in response to the scan signal on a corresponding gate line A liquid crystal panel having a second switch element for selectively connecting the vertical common electrode of the cell; A data converter for converting the pixel data stream into the black level control data stream; A gate driver sequentially driving the gate lines on the liquid crystal panel; A data driver driving the data lines in response to a pixel data stream; And a vertical common line driver for selectively driving each of the plurality of vertical common voltage lines in response to the black level control data stream.

A driving method of a liquid crystal display according to an embodiment may include converting a pixel data stream into a black level control data stream; Sequentially driving a plurality of gate lines on the liquid crystal panel; Driving a plurality of data lines on the liquid crystal panel in response to a pixel data stream; And selectively driving each of a plurality of vertical common voltage lines on the liquid crystal panel corresponding to the data lines in response to the black level control data stream.

According to the above configuration, the liquid crystal pixel according to the embodiment causes the liquid crystal cell to be driven by a horizontal electric field between the pixel electrode and the horizontal common electrode when displaying a gray level that is brighter than the lowest gray scale (ie, black). In addition, the liquid crystal pixel causes the liquid crystal molecules of the liquid crystal cell to be initialized by the vertical electric field between the vertical common electrode and the horizontal common electrode when displaying the lowest gray scale. In other words, the liquid crystal cell is controlled by the electric field at the time of displaying the lowest gray level as well as the brightest (or higher) gray level than the lowest gray level. Accordingly, in the liquid crystal pixel according to the embodiment, the response speed of light to the pixel driving signal may be significantly increased.

In the liquid crystal panel according to the embodiment, the liquid crystal pixels to be arranged in a matrix form are individually driven by a horizontal electric field when displaying a brighter gray level than the lowest gray scale (ie, black), while a liquid crystal panel is displayed by a vertical electric field when displaying a lowest grayscale. Driven. In other words, the liquid crystal panel causes each of the liquid crystal pixels to be driven by an electric field at the time of displaying the lowest gray level as well as brighter (or higher) gray levels than the lowest gray level. Accordingly, the liquid crystal panel according to the embodiment may respond quickly to the pixel driving signal.

As described above, the liquid crystal display according to the exemplary embodiment allows the liquid crystal pixels to be individually driven by the pixel driving signal in the display of the brightest grayscale than the lowest grayscale (i.e. black), while in the display of the lowest grayscale, Initialized by vertical common voltage. In other words, in the liquid crystal display according to the exemplary embodiment, the liquid crystal pixels are controlled by the electric field during display of the lowest gray level as well as the brightest (or higher) gray level than the lowest gray level. Accordingly, the liquid crystal display according to the embodiment may display an image that responds at high speed in response to video data. As a result, the liquid crystal display according to the exemplary embodiment may minimize image deterioration and blurring. Furthermore, the liquid crystal display according to the embodiment may improve the image quality.

In addition to the above embodiments, other objects, other features and other advantages of the present specification will become apparent from the detailed description of the embodiments associated with the accompanying drawings.

Hereinafter, embodiments of a liquid crystal pixel, a liquid crystal panel, and a liquid crystal display device capable of quickly responding to an electrical signal will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram illustrating in detail a liquid crystal pixel of a fast response speed according to an embodiment. 1 includes a liquid crystal cell CLC connected to a horizontal common voltage line HCL, a main thin film transistor MT connected to a main gate line MGL, and a sub thin film connected to a sub gate line SGL. A transistor SM is provided. The liquid crystal cell CLC includes the horizontal common electrode HCE connected to the horizontal common voltage line HCL, the pixel electrode PXE connected to the source electrode of the main thin film transistor MT, and the source of the sub thin film transistor ST. A vertical common electrode VCE connected to the electrode is provided. The same scan signal is supplied to the main and sub gate lines MGL and SGL.

The main thin film transistor MT switches the pixel driving signal Vpds to be supplied to the pixel electrode PXE of the liquid crystal cell CLC from the data line DL in response to a scan signal on the main gate line MGL. . The pixel driving signal Vpds has a gray voltage corresponding to the gray of the pixel to be displayed among the gray voltage sets. The gray level voltage set includes a black level corresponding to the horizontal common voltage Vhcom, a positive (or negative) back level voltage higher than (or lower) a constant voltage than the horizontal common voltage Vhcom, and these black level voltages and the back level. And 2 ^k-1 gray voltages set to have the same level difference or variable level difference between the voltages. When the scan signal Vsn has a high potential voltage (ie, high logic), the main thin film transistor MT is turned on so that the pixel driving signal Vpds on the data line DL is liquid crystal. It is supplied to the pixel electrode PXE of the cell CLC. At this time, the voltage between the pixel driving signal Vpds and the horizontal common voltage Vhcom is charged between the pixel electrode PXE and the horizontal common electrode HCE of the liquid crystal cell CLC. The voltage charged between the pixel electrode PXE and the horizontal common electrode HCE is maintained until the main thin film transistor MT is turned on again. On the contrary, when the scan signal Vsn has a low potential voltage (ie, low logic), the main thin film transistor MT is turned off to turn off the pixel driving signal Vpds on the data line DL. It does not transfer to the pixel electrode PXE of the liquid crystal cell CLC.

The sub thin film transistor ST may be supplied to the vertical common electrode VCE of the liquid crystal cell CLC from the vertical common voltage line VCL in response to a scan signal on the sine gate line SGL. Switch to. In the vertical common voltage line VCL, as shown in FIG. 2, the pixel driving signal (Vvcoml) or the horizontal common voltage Vhcom having a low potential corresponding to the same level as the horizontal common voltage Vhcom. A high high potential vertical common voltage Vvcomh corresponding to a level much higher than the maximum gray level voltage (i.e., the back level) of Vpds may be supplied. The low potential vertical common voltage Vvcoml is a vertical common voltage line V when the pixel driving signal Vpds on the data line DL has a gradation level voltage higher than the black level as in the period of " T1 " VCL). Unlike this, when the pixel driving signal Vpds on the data line DL is a black level voltage as in the period "T2" of FIG. 2, the high potential vertical common voltage Vvcomh is the vertical common voltage line VCL. Is supplied. When the scan signal Vsn on the sub gate line SGL has a high potential voltage (ie, a high logic), the sub thin film transistor ST is turned on, so that the low vertical common voltage on the vertical common voltage line VCL ( Vvcoml or the high vertical common voltage Vvcomh is supplied to the vertical common electrode VCE of the liquid crystal cell CLC. In this case, a difference voltage between the low or high vertical common voltage Vvcoml or Vvcomh and the horizontal common voltage Vhcom is charged between the vertical common electrode VCE and the horizontal common electrode HCE of the liquid crystal cell CLC. The voltage charged between the vertical common electrode VCE and the horizontal common electrode HCE is maintained until the sub thin film transistor ST is turned on again. On the contrary, when the scan signal Vsn has a low potential voltage (ie, low logic), the sub thin film transistor ST is turned off to be the vertical common voltage Vcom on the vertical common voltage line VCL. ) Is not transmitted to the vertical common electrode VCE of the liquid crystal cell CLC.

When the pixel driving signal Vpds having a voltage higher than the black level is charged between the pixel electrode PXE and the horizontal common electrode HCE, while the low potential vertical common voltage Vvcoml is charged in the vertical common electrode VCE. The liquid crystal molecules included in the liquid crystal cell CLC are rearranged to be twisted by the voltage of the pixel driving signal Vpds (ie, the horizontal electric field) between the pixel electrode PXE and the horizontal common electrode HCE to drive the pixel. The amount of light corresponding to the voltage of the signal Vpds is passed through. Accordingly, the liquid crystal pixel including the liquid crystal cell CLC displays a gray level corresponding to the voltage of the pixel driving signal Vpds. On the other hand, when the pixel driving signal Vpds of the black level is charged in the pixel electrode PXE, while the vertical common electrode VCE is charged in the vertical common electrode VCE, the liquid crystal cell CLC is closed. The constituent liquid crystal molecules are quickly returned to the initial arrangement state by the high potential vertical common voltage Vvcomh (that is, the vertical electric field) charged between the vertical common electrode VCE and the horizontal common electrode HCE, so that light is not transmitted. Do not At this time, the liquid crystal pixel including the liquid crystal cell CLC displays black.

As such, the liquid crystal molecules of the liquid crystal cell are rearranged by the horizontal electric field between the pixel electrode PXE and the horizontal common electrode HCE when the gray scale is displayed brighter than the lowest gray scale (ie, black). In addition, during the display of the lowest gray scale, the liquid crystal molecules of the liquid crystal cell return to the initial arrangement state by the vertical electric field between the vertical common electrode VCE and the horizontal common electrode HCE. In other words, the arrangement of the liquid crystal molecules is controlled by the electric field when displaying not only the brightest (or higher) gradations but also the lowest gradations. Accordingly, in the liquid crystal pixel according to the embodiment, the response speed of light to the pixel driving signal may be significantly increased.

3 is a circuit diagram illustrating in detail a configuration of a liquid crystal panel having a high response speed according to an embodiment. The liquid crystal panel of FIG. 3 includes a plurality of data lines DL1 to DLm arranged side by side in one direction (eg, a horizontal direction), and a plurality of lines arranged side by side in another direction (eg, a vertical direction). Main gate lines MGL1 to MGLn. The data lines DL1 to DLm cross the main gate lines MGL1 to MGLn so that the liquid crystal panel is divided into a plurality of pixel regions (for example, m × n pixel regions) arranged in a matrix form. do.

In the liquid crystal panel according to the exemplary embodiment, a plurality of vertical common voltage lines VCL1 to VCLm corresponding to the data lines DL1 to DLm, and a plurality of subs respectively corresponding to the main gate lines MGL1 to MGLn, respectively. Gate lines SGL1 to SGLn are arranged. The vertical common voltage lines VCL1 to VCLm and the sub gate lines SGL1 to SGLn also divide the liquid crystal panel into a plurality of pixel regions (for example, m × n pixel regions) in a matrix form. Cross each other.

The liquid crystal pixel LPX is formed in each of the plurality of pixel areas. As shown in FIG. 1, the liquid crystal pixel LPX includes a main thin film transistor MT connected to a corresponding main gate line MGL and a corresponding data line DL, a corresponding sub gate line SGL, and the like. A sub thin film transistor ST connected to a corresponding vertical common voltage line VCL, and a liquid crystal cell CLC connected to the main and sub thin film transistors MT and ST and a horizontal common voltage line HCL. . The horizontal common voltage line HCL is commonly connected to all of the liquid crystal cells CLC. Since the configuration, operation, effects, and features of each of these liquid crystal pixels LPX are apparent from the description of FIG. 1, the description of the liquid crystal pixels LPX will be omitted.

The liquid crystal pixels LPX to be arranged in a matrix form are individually driven by a horizontal electric field when displaying a lighter gray level than the lowest grayscale (i.e. black), while driving by a vertical electric field when displaying a lowest grayscale. do. In other words, each of the liquid crystal pixels LPX is driven by an electric field at the time of displaying the lowest gray level as well as brighter (or higher) gray levels than the lowest gray level. Accordingly, the liquid crystal panel according to the embodiment may respond quickly to the pixel driving signal.

The fast response speed liquid crystal panel as in FIG. 3 will constitute first and second array substrates (ie, lower and upper array substrates) disposed on both sides of the liquid crystal layer. 4A and 4B are plan views illustrating the planar structures of the first and second array substrates included in the liquid crystal panel according to an exemplary embodiment. Although FIGS. 4A and 4B show only a planar structure of some liquid crystal pixels (ie, three liquid crystal pixels), anyone of ordinary skill in the art with respect to the liquid crystal panel disclosed herein may have some liquid crystal pixels shown. It will be readily appreciated that liquid crystal pixels arranged in a matrix form can be implemented by repeating in the vertical and horizontal directions.

Referring to FIG. 4A, the first array substrate 10 includes data lines DL and main gate lines MGL disposed to cross each other. By the data lines DL and the main gate lines MGL, the first array substrate 10 is divided into a plurality of pixel regions P in a matrix form. The main thin film transistor MT is disposed near the intersection of the corresponding data line DL and the corresponding main gate line MGL. The main thin film transistor MT includes a gate electrode MGE formed on the bottom surface of the semiconductor pattern MSP and source and drain electrodes MSE and MDE arranged on the surface of the semiconductor pattern MSP at regular intervals. The gate electrode MGE is formed to protrude from the main gate line MGL. The drain electrode MDE is formed to protrude from the data line DL. In addition, the first array substrate 10 includes a horizontal common voltage line HCL disposed in parallel with the main gate line MGL. The horizontal common electrodes HCE extending in parallel with the data line DL from the horizontal common voltage line HCL are disposed in each of the pixel regions P by a predetermined number. In addition, a predetermined number of pixel electrodes PXE is disposed in each of the pixel regions P. FIG. Like the horizontal common electrodes HCE, the pixel electrodes PXE are formed in parallel with the data line DL. A certain number of pixel electrodes PXE and horizontal common electrodes HCE included in each pixel area P are alternately arranged. In addition, the pixel electrodes PXE and the horizontal common electrodes HCE may be formed in various shapes such as a zigzag shape or a boomerang shape instead of a rod shape. The pixel electrode PXE on each pixel area P is electrically connected to the source electrode MSE of the corresponding main thin film transistor MT via the contact MCT.

The second array substrate 20 illustrated in FIG. 4B includes vertical common voltage lines VCL and sub gate lines SGL disposed to cross each other. The vertical common voltage lines VCE are disposed at positions corresponding to the data lines DL on the first array substrate 10, and the sub gate lines SGL are also the main gate lines on the first array substrate 10. It is disposed at a position corresponding to the MGL. By the vertical common voltage lines VCE and the sub gate lines SGL, the second array substrate 20 is divided into a plurality of pixel regions P having a matrix form. The sub thin film transistor ST is disposed near an intersection of the corresponding vertical common voltage line VCE and the corresponding sub gate line SGL. The sub thin film transistor ST includes a gate electrode SGE formed on the bottom surface of the semiconductor pattern SSP, and source and drain electrodes SSE and SDE arranged on the surface of the semiconductor pattern SSP at predetermined intervals. The gate electrode SGE of the sub thin film transistor ST is formed to protrude from the sub gate line SGL. The drain electrode SDE of the sub thin film transistor ST is formed to protrude from the vertical common voltage line VCL. In addition, the second array substrate 20 includes a vertical common electrode VCE disposed in each of the pixel regions P. Referring to FIG. The vertical common electrode VCE is formed to occupy the remaining pixel region P except for a portion of the sub thin film transistor ST. The vertical common electrode VCE is electrically connected to the source electrode SSE of the corresponding sub thin film transistor ST via the contact SCT.

5 is a view illustrating a cross-sectional structure of a liquid crystal panel having a high response speed according to an embodiment. 5 is a cross-sectional view illustrating a cross section taken along line II ′ of the first and second array substrates 10 and 20 of FIG. 4. The liquid crystal panel of FIG. 5 has a layer of liquid crystal material 30 implanted between the first and second array substrates 10, 20.

The first array substrate 10 includes a gate electrode MGE and a horizontal common electrode HCE formed on the first transparent substrate 12. The first transparent substrate 12 may be any one of a plastic film and a glass substrate made of an insulating material having good light transmittance. The gate electrode MGE is connected to the main gate line MGL (not shown) as well as formed at the same time as the main gate line MGL. The horizontal common electrode HCE is connected to the horizontal common voltage line HCL, which is not shown, as well as simultaneously with the horizontal common voltage line HCL and the main gate line MGL and the gate electrode MGE through a lift-off process. Is formed on the same layer. In practice, the gate electrode MGE and the main gate line MGL deposit and deposit a conductive material layer comprising any one of Cu, Al, AlNd, Au, Ag and Mo on the first transparent substrate 12. It is formed by patterning the conductive material. Subsequently, a photoresist pattern (not shown) is formed on the first transparent substrate 12 on which the gate electrode MGE and the main gate line MGL are formed. The photoresist pattern exposes a surface of the first transparent substrate 12 on which the horizontal common electrode HCE and the horizontal common voltage line HCL are to be formed. A transparent conductive material (not shown) such as indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the photoresist pattern and the exposed surface of the first transparent substrate 12. The transparent conductive material on the pot resist pattern is removed along with the photoresist pattern through the cleaning process. Accordingly, the horizontal common electrode HCE and the horizontal common voltage line HCL are formed on the same layer as the gate electrode MGE and the main gate line MGL. The insulating film 14 has the same thickness on the entire surface of the first transparent substrate 12 on which the gate electrode MGE, the main gate line MGL, the horizontal common electrode HCE, and the horizontal common voltage line HCL are formed. do. The insulating film 14 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the first transparent substrate 12.

The first array substrate 10 may include the semiconductor material pattern MSP and the data line DL disposed on the insulating layer 14, and the drain and source electrodes MDE disposed on the semiconductor material pattern MSP at predetermined intervals. MSE). The drain and source electrodes MDE and MSE constitute the main thin film transistor MT together with the semiconductor material pattern MSP and the gate electrode MGE. The semiconductor material pattern MSP is formed on the insulating layer 14 to be positioned above the gate electrode MGE. The drain electrode MDE is connected to the data line DL on the insulating layer 14 as well as formed at the same time as the source electrode MSE and the data line DL. The semiconductor material pattern MSP will be formed by depositing a semiconductor material over the insulating film 14 and patterning the deposited semiconductor material layer through a lithography process. On the entire surface of the insulating film 14 having the semiconductor material pattern MSP, a conductive material layer including one of Cu, Al, AlNd, Au, Ag, and Mo is deposited. As the conductive material layer on the insulating layer 14 is patterned through a lithography process, the drain and source electrodes MDE and MSE and the drain electrode MDE are disposed on the semiconductor material pattern MSP at regular intervals. And a data line DL are formed.

The first array substrate 10 includes a passivation layer 16 formed on the entire surface of the first transparent substrate 12 having the main thin film transistor MT and pixel electrodes PXE disposed on the passivation layer 16. It is further provided. The pixel electrodes PXE are formed to be electrically connected to each other in each pixel region P while being electrically separated from the pixel electrodes of other pixel regions. The pixel electrodes PXE in each pixel area P are electrically connected to the source electrode MSE of the main thin film transistor MT by the contact MCT penetrating the protective layer 16. The protective layer 16 is formed to have a flat surface through a process of applying an insulating material such as silicon nitride or silicon oxide. In the protective layer 16, a contact hole exposing a part of the source electrode MSE of the main thin film transistor MT is formed. The contact hole is formed by partially removing the protective layer 16 through a lithography process. Next, a transparent conductive material such as ITO or IZO is deposited on the entire surface of the protective layer 16 exposing a part of the source electrode MSE of the main thin film transistor MT. At this time, the transparent conductive material is embedded in the contact hole to form a contact MCT. The transparent conductive material layer on the protective layer 16 is patterned through a lithography process to be electrically connected to the source electrode MSE of the main thin film transistor MT and alternately arranged with the lower horizontal common electrodes HCE. Pixel electrodes PXE to be formed are formed. The pixel electrodes PXE are spaced apart from the horizontal common electrode HCE at regular intervals to improve light transmittance for each gray level of the image. The distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is found to be approximately 3.0 to 5.0 μm through experiments of the light transmission characteristics of the pixel drive signal VPds at the back level. It became. The light transmittance of the pixel driving signal VPds having the back level is shown to have a response characteristic as shown in FIG. 6 according to the separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE. In FIG. 6, "ED1" indicates light transmission characteristics with respect to the back level pixel driving signal Vpds when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 3.0 µm. Indicates. "ED2" indicates light transmission characteristics with respect to the back level pixel drive signal VPds when the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 4.0 占 퐉. "ED3" indicates light transmission characteristics with respect to the back level pixel driving signal VPds when the separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is 5.0 µm. As can be seen in FIG. 6, when the separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE is about 4.0 μm, the light transmission characteristic of the back level pixel driving signal Vpds is best. . Therefore, the protective layer 16 is formed to have a thickness of about 4.0 μm so that the separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE can be maintained at about 4.0 μm. desirable.

The first array substrate 10 may further include a color filter layer (not shown) positioned between the gate electrode MGE and the main gate line MGL and the first transparent substrate 12. The color filter layer includes alternatingly-arranged red, green and blue filters. Each of the red, green, and blue filters is formed in a size corresponding to the pixel area. Furthermore, the first array substrate 10 is located between the gate electrode MGE and the main gate line MGL and the first transparent substrate 12, and adds a black matrix (not shown) to isolate the color filters. It can be provided as. The black matrix prevents color interference that may occur at the edges of the color filters.

The second array substrate 20 includes a gate electrode SGE formed on the second transparent substrate 22. As the second transparent substrate 22, any one of a plastic film and a glass substrate made of an insulating material having good light transmittance may be used, similar to the first transparent substrate 12. The gate electrode SGE is connected to the sub gate line SGL (not shown) and is formed simultaneously with the sub gate line SGL. The gate electrode SGE and the sub gate line SGL have a conductive material including any one of Cu, Al, AlNd, Au, Ag, and Mo deposited on the second transparent substrate 22, and the deposited conductive material. By being patterned, it is formed in an integrated form. The insulating film 24 is formed to have the same thickness on the entire surface of the second transparent substrate 22 on which the gate electrode SGE and the sub gate line SGL are formed. The insulating film 24 is formed to have a uniform thickness by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the second transparent substrate 12.

The second array substrate 20 may include the semiconductor material pattern SSP and the vertical common voltage line VCL disposed on the insulating layer 24, and the drain and source electrodes spaced apart from each other on the semiconductor material pattern SSP. (SDE, SSE). These drain and source electrodes SDE and SSE together with the semiconductor material pattern SSP and the gate electrode SGE constitute a sub thin film transistor ST. The semiconductor material pattern SSP is formed on the insulating layer 24 to be positioned above the gate electrode SGE. The drain electrode SDE is connected to the vertical common voltage line VCL on the insulating layer 24 as well as formed at the same time as the source electrode SSE and the vertical common voltage line VCL. The semiconductor material pattern SSP will be formed by depositing a semiconductor material over the insulating film 24 and patterning the deposited semiconductor material layer through a lithography process. Subsequently, a conductive material layer including any one of Cu, Al, AlNd, Au, Ag, and Mo is deposited on the entire surface of the insulating film 24 having the semiconductor material pattern SSP. As the conductive material layer on the insulating layer 24 is patterned through a lithography process, the drain and source electrodes SDE and SSE and the drain electrode SDE disposed on the semiconductor material pattern MSP at regular intervals may be formed. An integrated vertical common voltage line VCL is formed.

The second array substrate 20 may include an overcoating layer 26 formed on the entire surface of the second transparent substrate 22 having the sub thin film transistor ST and a vertical common electrode disposed on the overcoating layer 26. VCE) is further provided. The vertical common electrode VCE is formed to occupy the remaining pixel area P except for a part of the area occupied by the sub thin film transistor ST. The vertical common electrode VCE is formed to overlap a portion of the source electrode SSE of the sub thin film transistor ST. The vertical common electrode VCE is electrically connected to the source electrode SSE of the sub thin film transistor ST by a contact SCT penetrating the overcoat layer 26. The overcoat layer 26 is formed to have a flat surface by applying an insulating material such as silicon nitride or silicon oxide to the entire surface of the insulating film 24 having the sub thin film transistor ST through an application process. In the overcoat layer 26, a contact hole exposing a part of the source electrode SSE of the sub thin film transistor ST is formed. The contact hole is formed by partially removing the overcoating layer 26 through a lithographic process. Next, a transparent conductive material such as ITO or IZO is deposited on the entire surface of the overcoat layer 26 exposing a part of the source electrode SSE of the sub thin film transistor ST. In this case, the transparent conductive material is buried in the contact hole to form a contact SCT. The transparent conductive material layer on the overcoating layer 26 is patterned through a lithography process to be electrically connected to the source electrode SSE of the sub thin film transistor ST.

The second array substrate 20 may further include a color filter layer (not shown) positioned between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 22. The color filter layer includes alternatingly-arranged red, green and blue filters. Each of the red, green, and blue filters is formed in a size corresponding to the pixel area. Further, the second array substrate 20 is located between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 22, and adds a black matrix (not shown) to isolate the color filters. It can be provided as. The black matrix prevents color interference that may occur at the edges of the color filters.

The first and second array substrates 10 and 20 are bonded to each other so that the pixel electrode PXE and the vertical common electrode VCE face each other by a sealing material (not shown). The sealing material spaces apart the first and second array substrates 10 and 20 to secure an injection space of the liquid crystal material. The separation distance of the first and second array substrates 10 and 20 (that is, the separation distance EPss of the pixel electrode PXE and the vertical common electrode VCE) may correspond to the pixel driving signal supplied to the pixel electrode PXE. Vpds) should be appropriately set so that the liquid crystal pixel can be driven effectively. The separation distance EGss between the first and second array substrates 10 and 20 for the effective driving of the liquid crystal pixels is a test of the light transmission characteristics of the liquid crystal cell CLC with respect to the pixel drive signal VPds at the back level. Throughout this, it has been found that approximately 3.0 to 5.0 μm or so is applicable. In fact, when a liquid crystal material having a refractive index anisotropy value of 0.11 is injected between the first and second array substrates 10 and 20 and a back level pixel driving signal Vpds is supplied to the pixel electrode PXE, the liquid crystal pixel The light transmittance of was shown to have a response characteristic as shown in FIG. 7 according to the separation distance (EGss) between the first and second array substrates 10 and 20. In FIG. 7, "SD1" denotes light transmission of the liquid crystal pixel with respect to the back level pixel driving signal Vpds when the separation distance EGss between the first and second array substrates 10 and 20 is 3.4 µm. Characteristics. "SD2" indicates light transmission characteristics of the liquid crystal pixel with respect to the back level pixel driving signal Vpds when the separation distance EGss between the first and second array substrates 10 and 20 is 4.0 µm. "SD3" indicates light transmission characteristics of the liquid crystal pixel with respect to the back level pixel driving signal Vpds when the separation distance EGss between the first and second array substrates 10 and 20 is 5.0 µm. As can be seen in FIG. 7, when the separation distance EGss between the first and second array substrates 10 and 20 is about 3.4 to 4.0 μm, light transmission of the liquid crystal pixel to the back level pixel driving signal Vpds is performed. The property appears to change to a near-linear form. In this regard, the sealing material has a height (or thickness) of about 3.4 to 4.0 μm so that the separation distance (EGss) between the first and second array substrates 10 and 20 can be maintained at about 3.4 to 4.0 μm. Can be formed.

In relation to the maximum transmittance of the liquid crystal pixel, the separation distance EGss of the first and second array substrates 10 and 20 and the refractive index anisotropy value of the liquid crystal material have opposite characteristics. In fact, when the separation distance EGss between the first and second array substrates 10 and 20 becomes long, a high transmittance of the liquid crystal pixel is obtained only when the liquid crystal material has a low refractive index anisotropy value. On the contrary, when the separation distance EGss between the first and second array substrates 10 and 20 is shortened, a high transmittance of the liquid crystal pixel is obtained only when the liquid crystal material has a high refractive index anisotropy value. In addition, the separation distance EGss of the first and second array substrates 10 and 20 and the refractive index anisotropy value of the liquid crystal material should be set so that the optical retardation of the liquid crystal pixel is as small as possible. The optical retardation amount of the liquid crystal pixel is appropriate for the liquid crystal material according to the separation distance (EGss) of the first and second array substrates 10 and 20 through an experiment of the maximum transmittance characteristic of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material. It can be measured with the refractive index anisotropy value. By these experiments, it was measured that the light retardation amount of the liquid crystal pixel is applicable to 380 nm to 440 nm.

FIG. 8 illustrates the maximum transmittance characteristics of the liquid crystal pixel according to the separation distance EGss of the first and second array substrates 10 and 20 with respect to the refractive index anisotropy value of the liquid crystal material. In FIG. 8, "RA1" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10 and 20 is 3.4 µm. "RA2" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10 and 20 is 4.0 µm. "RA3" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10 and 20 is 4.5 µm. "RA4" represents the maximum transmittance of the liquid crystal pixel with respect to the refractive index anisotropy value of the liquid crystal material when the separation distance EGss between the first and second array substrates 10 and 20 is 5.0 µm. As can be seen in FIG. 8, when the separation distance EGss between the first and second array substrates 10 and 20 is 3.4 μm, the refractive index anisotropy value of the liquid crystal material is 0.12, and the first and second array substrates ( As the separation distance (EGss) between 10 and 20 is increased to 4.0 µm, 4.5 µm and 5.0 µm, the refractive index anisotropy values of the appropriate liquid crystal material are lowered to 0.10, 0.05 and 0.08. Next, the amount of light delay in the liquid crystal pixel including the liquid crystal material having the appropriate refractive index anisotropy value for each of the separation distances EGss of the first and second array substrates 10 and 20 is 3.4 μm, 40 μm, 4.5 μm, It was measured to be 408 nm, 400 nm, 405 nm and 400 nm at the separation distances of the first and second array substrates 10, 20 of 50 μm, respectively.

Furthermore, in the liquid crystal panel having a fast response speed according to the embodiment, in order to minimize light leakage during black level display, an appropriate potential difference between the vertical common electrode VCE and the horizontal common electrode HCE should be set. To this end, the light leakage of the first and second array substrates 10 and 20 according to the potential difference between the vertical common electrode VCE and the horizontal common electrode HCE is measured by measuring the light transmittance according to the separation distance (EGss). The voltage to be applied between the vertical common electrode VCE and the horizontal common electrode HCE, which enables the minimization of H, can be obtained. In practice, the vertical common electrode VCE and the horizontal common electrode are formed with the separation distance EPss of the first and second array substrates 10 and 20 being 3.4 μm and the refractive index anisotropy value of the liquid crystal material set to 0.12. The light transmittance of the liquid crystal pixel was measured while varying the voltage between HCE in a region higher than the voltage of the pixel driving signal Vpds at the back level. The light transmittance of the liquid crystal pixel at the time of black level display was minimum when a voltage of 8.5 V was supplied between the vertical common electrode VCE and the horizontal common electrode HCE as shown in FIG. 9. In this form, the light transmittance of the liquid crystal pixel when the separation distance EPSs of the first and second array substrates 10 and 20 is 4.0 μm and the refractive index anisotropy value of the liquid crystal material is 0.10 is 9.0 V. It was measured to be minimum when supplied between the vertical and horizontal common electrodes VCE and HCE. Further, the light transmittances of the liquid crystal pixels when the separation distances (EPss) of the first and second array substrates 10 and 20 are 4.5 μm and 5.0 μm and the refractive index anisotropy values of the liquid crystal material are 0.09 and 0.08 are all 8.5V. The voltage of was measured to be minimum when supplied between the vertical and horizontal common electrodes (VCE, HCE).

The maximum transmittance (LTRmax) of the liquid crystal pixel, the refractive index anisotropy value (△ n) of the liquid crystal material, and the light of the liquid crystal pixel according to the separation distance (EGss) of the first and second array substrates 10 and 20 obtained through the above experiments. The delay amount Δnd and the high potential vertical common voltage Vvcomh may be summarized as shown in Table 1 below.

EGss (㎛) LTRmax △ n Δnd (nm) Vvcomh (V) 3.4 0.352562 0.12 408 8.5 4.0 0.461057 0.10 400 9.0 4.5 0.463481 0.09 405 8.5 5.0 0.475367 0.08 400 8.5

As can be seen from FIG. 7 and Table 1, for an efficient liquid crystal panel in which the light transmission characteristic of the back-level pixel driving signal Vpds is changed to a more linear shape and the light delay amount can be minimized, Most preferably, the second array substrates 10 and 20 have a separation distance of about 4.0 μm and a light retardation amount of about 0.400 nm. For this purpose, about 0.10 and about 9.0V are most preferable also for the voltage between the refractive index anisotropy value of the liquid crystal material and the vertical and horizontal common electrodes VCE and HCE. In view of this, as the liquid crystal material for the fast response liquid crystal panel according to the embodiment, a liquid crystal material having a refractive index anisotropy value in the range of approximately 0.0950 to 0.1050 is most preferred. Therefore, it is preferable that any one of a Fluoro substitution liquid crystal material is used for the liquid crystal layer 30 of the liquid crystal panel having a high response speed according to the embodiment. For example, any one of liquid crystal materials such as ML-0323, ML-0424, ML-0249 and ML-0567 may be used as a constituent material of the liquid crystal layer 30 of the fast response liquid crystal panel according to this embodiment. will be.

The liquid crystal pixels to be arranged in this matrix form are individually driven by a horizontal electric field between the pixel electrode PXE and the horizontal common electrode HCE at the time of displaying a lighter gray level than the lowest gray level (that is, black). In the display of, the vertical electric field is driven by the vertical electric field between the vertical and horizontal common electrodes VCE and HCE. In other words, each of the liquid crystal pixels is driven by an electric field at the time of displaying the lowest gray level as well as the brightest (or higher) gray level than the lowest gray level. Accordingly, the liquid crystal panel according to an exemplary embodiment may respond quickly to the pixel driving signal.

10A and 10B are plan views illustrating in detail a planar structure of first and second array substrates included in a fast response speed liquid crystal panel according to another exemplary embodiment. 10A and 10B show only the planar structure of some liquid crystal pixels (i.e., three liquid crystal pixels) similarly to FIGS. 4A and 4B, but anyone skilled in the art with respect to the liquid crystal panel disclosed herein It will be readily appreciated that a plurality of liquid crystal pixels arranged in a matrix form may be implemented by repeating some of the illustrated liquid crystal pixels in the vertical and horizontal directions.

The first array substrate 40 of FIG. 10A has the same planar structure as the first array substrate 10 of FIG. 4A, except that the contact MCT is removed. Components of FIG. 10A having the same function, structure, and arrangement as those shown in FIG. 4A will be referred to by the same reference numerals and designations. In addition, since the components of FIG. 10A that are identical to those shown in FIG. 4A have already been clearly shown through the description of FIG. 4A, the description about them will be omitted.

In the first array substrate 40 of FIG. 10A, the pixel electrodes PXE on each pixel area P are formed in an integrated form to be electrically connected to each other. A portion of the pixel electrode PXE overlaps a portion of the source electrode MSE of the main thin film transistor MT. The overlapping portions of the pixel electrode PXE and the source electrode MSE of the main thin film transistor MT directly contact each other. Accordingly, the pixel electrode PXE is electrically connected to the source electrode MSE of the main thin film transistor MT without using a contact.

Meanwhile, the second array substrate 50 of FIG. 10B also has the same planar structure as the second array substrate 20 of FIG. 4B except that the contact SCT is removed. Components of FIG. 10B having the same function, structure, and arrangement as those shown in FIG. 4B will be referred to by the same reference numerals and designations. In addition, since the components of FIG. 10B that are identical to those shown in FIG. 4B have already been clearly shown through the description of FIG. 4B, the description about them will be omitted.

In the second array substrate 50 of FIG. 10B, a part of the vertical common electrode VCE on each pixel area P overlaps with a part of the source electrode SSE of the sub thin film transistor ST. The overlapping portions of the vertical common electrode VCE and the source electrode SSE of the sub thin film transistor ST directly contact each other. Accordingly, the vertical common electrode VCE is electrically connected to the source electrode SSE of the sub thin film transistor ST without depending on the contact.

11 is a view illustrating a cross-sectional structure of a liquid crystal panel having a high response speed according to another embodiment. FIG. 11 is a cross-sectional view illustrating a cross section taken along line II-II ′ of the first and second array substrates 40 and 50 of FIG. 10. The liquid crystal panel of FIG. 11 has a layer of liquid crystal material 60 implanted between the first and second array substrates 40 and 50.

The first array substrate 40 includes horizontal common electrodes HCE and an interlayer insulating film 44 sequentially formed on the first transparent substrate 42. The first transparent substrate 42 may be any one of a plastic film and a glass substrate made of an insulating material having good light transmittance. The horizontal common electrode HCE is connected to the horizontal common voltage line HCL (not shown) as well as formed integrally with the horizontal common voltage line HCL. The horizontal common electrode HCE and the horizontal common voltage line HCL are formed by depositing ITO or IZO and a transparent conductive material (not shown) on the first transparent substrate 42, and the deposited transparent conductive material is lithographically printed. By patterning through the process, it is formed in an integrated form. The interlayer insulating film 44 is formed to have a planarized surface on the entire surface of the first transparent substrate 42 on which the horizontal common electrode HCE and the horizontal common voltage line HCL are formed. The interlayer insulating film 44 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the first transparent substrate 42.

The first array substrate 40 includes a gate electrode MGE formed on the interlayer insulating layer 44. The gate electrode MGE is connected to the main gate line MGL (not shown) as well as formed at the same time as the main gate line MGL. In the gate electrode MGE and the main gate line MGL, a conductive material including any one of Cu, Al, AlNd, Au, Ag, and Mo is deposited on the interlayer insulating film 44, and the deposited conductive material is slab. It is formed by patterning through a printing process. The gate insulating film 46 is formed to have the same thickness on the entire surface of the interlayer insulating film 44 on which the gate electrode MGE and the main gate line MGL are formed. The gate insulating film 46 is formed by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the gate electrode MGE, the main gate line MGL, and the interlayer insulating film 44.

In addition, the first array substrate 40 may include the semiconductor material pattern MSP and the data line DL disposed on the gate insulating layer 46, and drain and source electrodes disposed on the semiconductor material pattern MSP at regular intervals. (MDE, MSE) and pixel electrodes PXE electrically connected to the source electrode MSE. These drain and source electrodes MDE and MSE form the main thin film transistor MT together with the semiconductor material pattern MSP and the gate electrode MGE. The semiconductor material pattern MSP is formed on the gate insulating layer 46 to be positioned on the gate electrode MGE. The drain electrode MDE is connected to the data line DL on the gate insulating layer 46 as well as formed at the same time as the source electrode MSE and the data line DL. The pixel electrodes PXE are formed to be electrically connected to each other in each pixel region P while being electrically separated from the pixel electrodes PXE on the other pixel region P. FIG. A portion of the pixel electrode PXE in each pixel region P overlaps with a portion of the source electrode MSE of the main thin film transistor MT. The overlapping portions of the pixel electrode PXE and the source electrode MSE of the main thin film transistor MT are in direct contact so that the pixel electrode PXE is electrically connected to the source electrode MSE of the main thin film transistor MT. In addition, the pixel electrodes PXE are in direct contact with the gate insulating layer 46 and are positioned on the same layer as the data line DL. Furthermore, the pixel electrodes PXE are alternately arranged with the horizontal common electrodes HCE under the gate insulating layer 46.

The semiconductor material pattern MSP will be formed by depositing a semiconductor material over the gate insulating film 46 and patterning the deposited semiconductor material layer through a lithography process. Subsequently, a conductive material layer including any one of Cu, Al, AlNd, Au, Ag, and Mo is deposited on the entire surface of the gate insulating film 46 having the semiconductor material pattern MSP. As the conductive material layer on the insulating film 14 is patterned through a lithography process, the drain and source electrodes MDE and MSE and the gate insulating film 46 that are spaced-spaced on the semiconductor material pattern MSP are disposed. In addition, the data line DL is formed in direct contact with the drain electrode MDE. Next, the semiconductor material pattern (MSP), A photoresist is applied to the entire surface of the gate sectional layer 46 on which the data line DL, the drain and the source electrodes MDE and MSE are formed. The photoresist layer is patterned through an exposure and development process to expose the gate insulating layer 46 corresponding to a region where the pixel electrodes PXE including a portion of the source electrode MSE is to be located. A transparent insulating material such as ITO or IZO is deposited on the photoresist pattern and the gate insulating film 46 thereby exposed to a uniform thickness. Finally, the transparent insulating material on the photoresist pattern is removed along with the photoresist pattern through a cleaning process to form pixel electrodes PXE in direct contact with a portion of the source electrode MSE and the gate insulating film 46. .

The pixel electrodes PXE are spaced apart from the horizontal common electrode HCE at regular intervals to improve light transmittance for each gray level of the image. The separation distance EGph between the pixel electrode PXE and the horizontal common electrode HCE may be set to about 3.0 to 5.0 μm. Accordingly, the interlayer insulating film 44 and the gate insulating film 46 can be formed such that their total thickness has any value within the range of approximately 3.0 to 5.0 mu m. In order to maximize light transmittance, the interlayer insulating film 44 and the gate insulating film 46 are approximately 4.0 so that the distance EGph between the pixel electrode PXE and the horizontal common electrode HCE can be maintained at about 4.0 μm. Most preferably, it is formed to a total thickness on the order of μm.

The first array substrate 40 is disposed between the horizontal common electrode VCE and the horizontal common voltage line VGL and the first transparent substrate 42 or between the horizontal common electrode VCE and the horizontal common voltage line VGL. A color filter layer (not shown) positioned between the insulating films 44 may be further provided. The color filter layer includes alternatingly-arranged red, green and blue filters. Each of the red, green, and blue filters is formed in a size corresponding to the pixel area. Further, the first array substrate 40 may be disposed between the horizontal common electrode VCE and the horizontal common voltage line VGL and the first transparent substrate 42 or between the horizontal common electrode VCE and the horizontal common voltage line VGL. A black matrix (not shown) may be further provided between the insulating layers 44 and to isolate the color filters. The black matrix prevents color interference that may occur at the edges of the color filters.

The second array substrate 50 includes a gate electrode SGE formed on the second transparent substrate 52. As the second transparent substrate 52, any one of a plastic film and a glass substrate made of an insulating material having good light transmittance may be used, similar to the first transparent substrate 42. The gate electrode SGE is connected to the sub gate line SGL (not shown) and is formed simultaneously with the sub gate line SGL. The gate electrode SGE and the sub gate line SGL deposit and deposit a conductive material layer including any one of Cu, Al, AlNd, Au, Ag, and Mo on the second transparent substrate 52. By patterning the material, it is formed in an integrated form. The insulating film 54 is formed to have the same thickness on the entire surface of the second transparent substrate 52 on which the gate electrode SGE and the sub gate line SGL are formed. The insulating film 54 is formed to have a uniform thickness by applying an insulating material such as silicon oxide or silicon nitride to the entire surface of the second transparent substrate 52.

The second array substrate 50 may include a semiconductor material pattern SSP and a vertical common line VCL disposed on the insulating layer 54, and drain and source electrodes spaced apart at regular intervals on the semiconductor material pattern SSP. SDE, SSE, and vertical common electrode VCE. These drain and source electrodes SDE and SSE constitute the sub thin film transistor ST together with the semiconductor material pattern SSP and the gate electrode SGE. The semiconductor material pattern SSP is formed on the insulating layer 54 to be positioned above the gate electrode SGE. The drain electrode SDE is connected to the vertical common voltage line VCL on the insulating layer 24 as well as formed at the same time as the source electrode SSE and the vertical common voltage line VCL. The vertical common electrode VCE occupies the remaining pixel area P except a part of the area occupied by the sub thin film transistor ST. The vertical common electrode VCE overlaps a portion of the source electrode SSE of the sub thin film transistor ST. The overlapping portions of the vertical common electrode VCE and the source electrode SSE of the sub thin film transistor ST are in direct contact with each other so that the vertical common electrode VCE is electrically connected to the source electrode SSE of the sub thin film transistor ST. To be. In addition, the vertical common electrode VCE is in direct contact with a portion of the source electrode SSE of the sub thin film transistor ST and the insulating layer 54 through a lift-off process, and also has a layer such as the vertical common line VCL. It is formed to be located.

The semiconductor material pattern SSP will be formed by depositing a semiconductor material over the insulating film 54 and patterning the deposited semiconductor material layer through a lithography process. Subsequently, a conductive material layer including any one of Cu, Al, AlNd, Au, Ag, and Mo is deposited on the entire surface of the insulating film 54 having the semiconductor material pattern SSP. The conductive material layer on the insulating layer 54 is patterned through a lithography process, so that the drain and source electrodes SDE and SSE and the drain electrode SDE are spaced apart at regular intervals on the semiconductor material pattern MSP. An integrated vertical common voltage line VCL is formed. Next, a photoresist is applied to the entire surface of the section film 54 in which the semiconductor material pattern SSP, the vertical common voltage line VCL, the drain and the source electrodes SDE and SSE are formed. The photoresist layer is patterned through an exposure and development process to expose the insulating film 54 corresponding to the region where the vertical common electrode VCE including a part of the source electrode MSE is to be located. A transparent insulating material such as ITO or IZO is deposited to a uniform thickness on the photoresist pattern and the insulating film 54 exposed thereby. Finally, the transparent insulating material on the photoresist pattern is removed along with the photoresist pattern through a cleaning process to form a vertical common electrode VCE in direct contact with a portion of the source electrode MSE and the insulating film 54.

In addition, the second array substrate 50 may further include a color filter layer (not shown) between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 52. The color filter layer includes alternatingly-arranged red, green and blue filters. Each of the red, green, and blue filters is formed in a size corresponding to the pixel area. Further, the second array substrate 50 is located between the gate electrode SGE and the sub gate line SGL and the second transparent substrate 52, and adds a black matrix (not shown) to isolate the color filters. It can be provided as. The black matrix prevents color interference that may occur at the edges of the color filters.

In the above-described first and second array substrates 40 and 50, the pixel electrode PXE and the vertical common electrode VCE are bonded to each other by a sealing material (not shown). The sealing mill spaces the first and second array substrates 40 and 50 so that an injection space of the liquid crystal material 60 can be secured. The separation distance between the first and second array substrates 40 and 50 (that is, the separation distance EPss between the pixel electrode PXE and the vertical common electrode VCE) may correspond to the pixel driving signal supplied to the pixel electrode PXE. Vpds) may be set to about 3.4 to 4.0 占 퐉 so that the liquid crystal pixel can be effectively driven. Accordingly, the spaced apart sealing material of the first and second array substrates 40 and 50 will be formed to a height (or thickness) of approximately 3.4 to 4.0 μm. For an efficient liquid crystal panel in which the light transmission characteristic of the back level pixel driving signal VPds is changed to a more linear shape and the light delay amount can be minimized, the first and second array substrates 40 and 50 Most preferably, the sealing material is formed to a height (or thickness) of about 4.0 μm so that the separation distance EGss is about 4.0 μm. In addition, as the constituent material of the liquid crystal layer 60, liquid crystal materials having refractive index anisotropy values of about 0.08 to 012 that cause light delay amounts of about 400 to 408 nm may be used. Most preferred is a liquid crystal material having a refractive index anisotropy value of about 0.10. To this end, any one of the Fluoro-substituted liquid crystal materials having a refractive index anisotropy value in the range of about 0.0950 to 0.1050 may be used as a constituent material of the liquid crystal layer 60. Such fluoro substituted liquid crystal materials include liquid crystal materials such as ML-0323, ML-0424, ML-0249 and ML-0567. Furthermore, about 8.5 to 9.0 V may be used as the voltage applied between the vertical and horizontal common electrodes VCE and HCE, but about 9.0 V is most preferable.

Also in the liquid crystal panel of this other embodiment, the liquid crystal pixels arranged in a matrix form, respectively, the horizontal electric field between the pixel electrode PXE and the horizontal common electrode HCE at the time of displaying a lighter gray level than the lowest gray level (ie, black). In the case of display of the lowest gray scale, it is driven by a vertical electric field between the vertical and horizontal common electrodes VCE and HCE. In other words, each of the liquid crystal pixels is driven by an electric field at the time of displaying the lowest gray level as well as the brightest (or higher) gray level than the lowest gray level. Accordingly, the liquid crystal panel according to another exemplary embodiment may respond quickly to the pixel driving signal.

12 is a block diagram illustrating in detail a liquid crystal display device having a fast response speed according to an exemplary embodiment. 12 includes a main gate driver 102A connected to a plurality of main gate lines MGL1 to MGLn on the liquid crystal panel 100, and a plurality of data lines DL1 on the liquid crystal panel 100. And a timing controller 106 for controlling the operation timings of the main gate driver 102A and the data driver 104. In addition to the plurality of main gate lines MGL1 to MGLn and the plurality of data lines DL1 to DLm, the liquid crystal panel 100 includes a plurality of sub gate lines SGL1 to SGLn and a plurality of vertical common voltage lines VCL1 to VCLm. ). The liquid crystal panel 100 is divided by main gate lines MGL1 to MGLn and data lines and / or by sub gate lines SGL1 to SGLn and vertical common voltage lines VCL1 to VCLm. The matrix is divided into m × n pixel areas. In each of these pixel regions, a liquid crystal pixel LPX including main and sub thin film transistors MT and ST and a liquid crystal cell CLC is formed. The liquid crystal cells CLC are electrically common-connected to the horizontal common line HCL. The configuration, operation, and effects of such a liquid crystal panel 100 will be omitted in detail as described above with reference to FIGS. 1 and 3 as described above.

Main gate driver 102 on liquid crystal panel 100 The main scan signals corresponding to the number n of the main gate lines MGL are sequentially generated so that the main gate lines MGL1 to MGLn are alternately enabled. The main scan signals have a waveform in which a pulse having a width corresponding to a period of the horizontal synchronization signal Hsync and a gate high voltage Vgh of high potential are sequentially shifted by the width thereof. In other words, the main gate driver 102A causes the gate high voltage Vgh to be applied to any one of the main gate lines MGL to be enabled, while the gate low voltage of the low potential is applied to the remaining main gate lines MGL. Vgl) is supplied. The liquid crystal pixels LPX in response to the main scan signal charge the pixel driving signal Vpds on the data lines DL1 to DLm by one line. To generate these main scan signals, main gate driver 102A responds to gate control signal GCS from timing controller 106. The gate control signal GCS includes a gate start pulse GSP generated for each period of the vertical synchronization signal Vsync and at least one gate shift clock GSC having the same frequency as the horizontal synchronization signal Hsync. .

Whenever any one of the main gate lines MGL on the liquid crystal panel 100 is enabled, the data driver 104 may output pixel data VDr from the timing controller 106 in an analog form. The pixel driving signals Vpds converted by converting the pixel driving signals Vpds are supplied to the data lines DL1 to DLm on the liquid crystal panel 100, respectively. The pixel data VDr for each line is transmitted from an external video data source (for example, a graphic module of a computer system or an image demodulation module of a television receiver) without passing through the timing controller 106. Can also be supplied directly to. The data driver 104 responds to the data control signal DCS from the timing controller 106 to convert the pixel data VDr for each line into the pixel drive signal VPds. The data control signal DCS includes a data enable signal DEN having the same frequency as the horizontal synchronization signal Hsync, a data clock DCLK indicating a transmission cycle of pixel data, and the like.

The timing controller 106 uses an external video data source (eg, a graphics module of a computer system or an image demodulation module of a television receiver) to control the operation timing of the main gate driver 102A and the data driver 104. Input the synchronization signal SYNC from. The synchronization signal SYNC supplied to the timing controller 106 includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DEN, and a data clock DCLK. The timing controller 106 uses these synchronization signals SYNC to control the gate control signal GCS for controlling the operation timing of the main gate driver 102A and the operation timing for the data driver 104. Generate a data control signal DCS. In addition, the timing controller 106 may sequentially input pixel data VDf from an external video data source by one frame. The pixel data VDf for each frame is rearranged by the timing controller 106 so as to be divided into the pixel data VDr for each line. The rearranged frame pixel data VDf is supplied to the data driver 104 one line at a time so as to be synchronized with the data control signal DCS.

In addition, the liquid crystal display device having a high response speed according to the embodiment may include a sub gate driver 102B connected to a plurality of sub gate lines SGL1 to SGLn on the liquid crystal panel 100 and a horizontal common voltage on the liquid crystal panel 100. The common voltage generator 110 is connected to the line HCL. The sub gate driver 102B sequentially turns the sub gate lines SGL1 to SGLn on the liquid crystal panel 100 to alternately enable the sub gate lines SGL to be synchronized with the corresponding main gate line MGL. Generates sub scan signals corresponding to (n). The sub scan signals have a waveform whose period and timing coincide with the main scan signals generated by the main gate driver 102A. The liquid crystal pixels LPX responsive to the sub scan signal charge the pixel driving signal Vpds one by one line, and also charge the vertical common voltage Vvcoml or Vvcomh on the vertical common voltage lines VCL1 to VCLm. Done. To generate these sub scan signals, the sub gate driver 102A, like the main gate driver 102A, responds to the gate control signal GCS from the timing controller 106. In another embodiment, the sub gate lines SGL1 to SGLn on the liquid crystal panel 100 may be driven by the main scan signal from the main gate driver 102A together with the corresponding main gate lines MSL1 to MSLn. In this case, the sub gate driver 102B can be removed, but the load burden on the main gate driver 102A becomes large.

The common voltage generator 110 generates a horizontal common voltage Vhcom corresponding to the base voltage level of the pixel driving signal Vpds. The horizontal common voltage Vhcom generated by the common voltage generator 110 is connected to all liquid crystal pixels LPX on the liquid crystal panel 100 via the horizontal common voltage line HCL on the liquid crystal panel 100. Specifically, it is commonly supplied to the horizontal common electrode HCE of all the liquid crystal cells CLC. In addition, the common voltage generator 110 may have a vertical high common potential that is significantly higher than the highest voltage level (ie, the voltage level corresponding to the back level) of the pixel driving signal Vpds based on the horizontal common voltage Vhcom. Generate the voltage Vvcomh. The high potential vertical common voltage Vvcomh may be set to a voltage level that is about 8.5 to 9.5 V higher than the vertical common voltage Vhcom, but is preferably set to about 9.0 V higher than the horizontal common voltage Vhcom. It is good.

Furthermore, the liquid crystal display of the fast response speed according to the embodiment includes a data converter 108 for inputting pixel data VDr for each line from the timing controller 106, and a plurality of vertical lines on the liquid crystal panel 100. The vertical common voltage line driver 112 is connected to the common voltage lines VCL1 to VCLm. The data converter 108 converts each line of pixel data from the timing controller 106 into black level control data. One line of black level control data CVDr converted by the data converter 108 is sequentially supplied to the vertical common voltage line driver 112. The black level control data is enabled with a logical value of "1" (or "0") when the pixel data is a gray level value (for example, "000000" in case of 6-bit pixel data). In contrast, when the pixel data has a gradation value higher than the black level (for example, "at least 000001" for 6-bit pixel data), the black level control data is set to a logical value of "0" (or "1"). It is disabled. In order to convert such pixel data into black level control data, the data converter 108 includes a NOR gate or an OR gate that performs an NOR operation or an OR operation.

The vertical common voltage line driver 112 may control the black level control data CVDr by one line from the data converter 108 whenever one of the sub gate lines SGL on the liquid crystal panel 100 is enabled. The vertical common voltage Vvcoml having the same high voltage as the vertical common voltage Vvcomh or the horizontal common voltage Vhcom at each of the vertical common voltage lines VCL1 to VCLm on the liquid crystal panel 100. To supply. For example, if the black level control data has a logic value of "1" (or "0"), the vertical common voltage line driver 112 is common to the vertical common voltage line VCL corresponding to the black level control data. The high potential vertical common voltage Vvcomh from the voltage generator 110 is supplied. Alternatively, if the black level control data has a logic value of "0" (or "1"), the vertical common voltage line driver 112 may store low on the vertical common voltage line VCL corresponding to the black level control data. As the vertical common voltage Vvcoml of the potential, the horizontal common voltage Vhcom from the common voltage generator 110 is supplied. Vertical common voltage line driver for switching the low potential and high potential vertical common voltages Vvcoml and Vvcomh to each of the vertical common voltage lines VCL1 to VCLm according to the black level control data CVDr by one line. 112 responds to the data control signal DCS from the timing controller 106 similarly to the data driver 104.

As the corresponding main and sub gate lines MGL and SGL are enabled at the same time, each of the liquid crystal pixels LPX on the liquid crystal panel 100 performing the charging operation by one line may be formed on the corresponding data line DL. The low voltage or high potential vertical common voltage Vvcoml or Vvcomh on the corresponding vertical common voltage line VCL is charged together with the pixel driving signal Vpds. Each of the liquid crystal pixels LPX includes a pixel driving signal in which the liquid crystal molecules included in the liquid crystal cell CLC are charged when the pixel driving signal Vpds having a voltage higher than the black level and the vertical common voltage Vvcoml having a low potential are charged. By rearranging by Vpds, the amount of light corresponding to the voltage of the pixel driving signal Vpds is passed. Accordingly, the liquid crystal pixel displays a gray level corresponding to the voltage of the pixel driving signal Vpds. In contrast, each of the liquid crystal pixels LPX is charged with a high potential when the black level pixel driving signal Vpds and the high potential vertical common voltage Vvcomh are charged. The vertical common voltage Vvcomh allows for a quick return to the initial arrangement so that light is not transmitted. At this time, the liquid crystal pixel LPX displays black.

As described above, in the liquid crystal display according to the exemplary embodiment, the liquid crystal pixels are individually driven by the pixel driving signal Vpds at the time of displaying the grayscale which is brighter than the minimum grayscale (that is, black), and at the time of displaying the minimum grayscale. It is initialized by the high potential vertical common voltage (Vvcomh). In other words, in the liquid crystal display according to the exemplary embodiment, the liquid crystal pixels are controlled by the electric field during display of the lowest gray level as well as the brightest (or higher) gray level than the lowest gray level. Accordingly, the liquid crystal display according to the embodiment may display an image that responds at high speed in response to video data. As a result, the liquid crystal display according to the exemplary embodiment may minimize image deterioration and blurring. Furthermore, the liquid crystal display according to the embodiment may improve the image quality.

As described above, the embodiments of the present invention have been described with reference to the liquid crystal pixels, the liquid crystal panel, and the liquid crystal display devices of the fast response speed shown in FIGS. It will be apparent that various modifications, changes, and equivalent other embodiments may be made without departing from the spirit and scope disclosed by the embodiments. Accordingly, the spirit and scope disclosed in the embodiments should not be limited to the description of the embodiments, but should be set by the matters set forth in the appended claims.

1 is a circuit diagram illustrating in detail a liquid crystal pixel of a fast response speed according to an embodiment.

FIG. 2 is a waveform diagram illustrating waveforms of signals supplied to the liquid crystal pixel of FIG. 1.

3 is a circuit diagram schematically illustrating a configuration of a liquid crystal panel having a high response speed according to an embodiment.

4A and 4B are plan views illustrating in detail the planar structures of the first and second array substrates included in the fast response liquid crystal panel according to the embodiment.

FIG. 5 is a cross-sectional view of the first and second array substrates of FIG. 4 taken along the line II ′ of FIG. 4 to describe in detail the cross-sectional structure of a liquid crystal panel having a high response speed according to an embodiment.

6 is FIG. 6 is a characteristic diagram illustrating light transmission characteristics of a liquid crystal pixel according to a separation distance between a pixel electrode and a horizontal common electrode for a pixel driving signal of a back level.

7 is A characteristic diagram illustrating light transmission characteristics of liquid crystal pixels according to separation distances of the first and second array substrates with respect to the back level pixel driving signal.

FIG. 8 is a characteristic diagram illustrating maximum transmittance characteristics of liquid crystal pixels according to separation distances of first and second array substrates with respect to refractive index anisotropy values of the liquid crystal material.

FIG. 9 illustrates a potential difference between the vertical common electrode VCE and the horizontal common electrode HCE while the separation distance between the first and second array substrates is 3.4 μm and the refractive index anisotropy value of the liquid crystal material is set to 0.12. Is a characteristic diagram comparing and explaining the light transmission characteristics of the liquid crystal pixel with respect to.

10A and 10B are plan views illustrating in detail a planar structure of first and second array substrates included in a fast response speed liquid crystal panel according to an exemplary embodiment.

FIG. 11 is a cross-sectional view taken along line II-II ′ of the first and second array substrates of FIG. 10 to describe in detail a cross-sectional structure of a liquid crystal panel having a high response speed according to an embodiment.

12 is a block diagram illustrating in detail a liquid crystal display device having a fast response speed according to an exemplary embodiment.

`` Explanation of symbols for main parts of drawings ''

10,40: first array substrate 12,42: first transparent substrate

14,24,54 insulating film 16: protective layer

20,50: second array substrate 22,52: second transparent substrate

26: overcoating layer 44: interlayer insulating film

46 gate insulating film 100 liquid crystal panel

102A: Main Gate Driver 102B: Sub Gate Driver

104: data driver 106: timing controller

108: data converter 110: common voltage generator

112: vertical common line driver

Claims (21)

A liquid crystal cell having a horizontal common electrode connected to a horizontal common voltage line; A first switch element for switching a pixel driving signal to be supplied to a pixel electrode of the liquid crystal cell from a data line in response to a scan signal on a gate line; And a second switch element for switching a vertical common voltage to be supplied to a vertical common electrode of the liquid crystal cell from a vertical common line in response to the scan signal on the gate line. The method of claim 1, wherein the vertical common voltage And a low potential level corresponding to a voltage on the horizontal common voltage line and a high potential level higher than the maximum voltage level of the pixel drive signal, in accordance with the voltage of the pixel drive signal. The method of claim 2, wherein the vertical common voltage is Maintain the high potential level when the pixel driving signal has a black level voltage, And the low potential level when the pixel drive signal is higher than the black level voltage. The method of claim 1, The gate line includes a main and a sub gate line, The first switch element is responsive to a main scan signal on the main gate line, And the second switch element responds to a sub scan signal on the sub gate line. A horizontal common electrode common-connected to the horizontal common voltage line, a pixel electrode alternately arranged with the horizontal common electrode, and corresponding to each of the unit regions divided by the plurality of main gate lines and the plurality of data lines crossing each other; Main gate line, and data line and A first substrate having a main thin film transistor connected between the pixel electrodes; A unit divided by a plurality of sub gate lines facing the main gate lines and a plurality of vertical common voltage lines facing the data lines A second substrate having a vertical common electrode positioned in each of the regions, and a sub thin film transistor connected between a corresponding sub gate line, a corresponding vertical common voltage line, and a corresponding horizontal common electrode; And And a liquid crystal layer disposed between the pixel and the horizontal common electrode of the first substrate and the vertical common electrode of the second substrate. The method of claim 5, wherein The pixel electrode and the horizontal common electrode are arranged to be spaced apart from each other by about 3.0 ~ 5.0㎛. The method of claim 5, wherein And the pixel electrode and the horizontal common electrode are spaced apart from each other by about 4.0 μm. The method of claim 5, wherein The first and second substrates are disposed about 3.4 to 5.0㎛ spaced apart from each other. The first and second substrates are disposed about 4.0㎛ spaced apart from each other. And the liquid crystal layer comprises a liquid crystal material having an optical retardation amount of about 380 to 440 nm. And the liquid crystal layer comprises a liquid crystal material having an optical retardation amount of about 400 nm. Wherein the liquid crystal layer comprises any one of a Fluoro-substituted liquid crystal material. The method of claim 5, wherein And wherein the vertical common voltage line is selectively supplied with a low potential voltage corresponding to a voltage supplied to the horizontal common line and a high potential voltage approximately 9.0V higher than the low potential voltage. The method of claim 5, wherein And the horizontal common electrode is on the same layer as the gate line. The method of claim 5, wherein And the horizontal common electrode is positioned under the gate line. A plurality of main gate lines and a plurality of data lines crossing each other so as to distinguish the unit regions, a horizontal common electrode provided in each of the unit regions to be connected to a horizontal common voltage line, a pixel electrode alternately arranged with the horizontal common electrode, and Corresponding main gate and data lines, and Forming a main thin film transistor connected between the pixel electrodes on the first substrate; A unit divided by a plurality of sub gate lines facing the main gate lines, a plurality of vertical common voltage lines facing the data lines, and these sub gate lines and vertical common voltage lines Forming on the second substrate a vertical common electrode located in each of the regions and a sub thin film transistor connected between a corresponding sub gate line, a corresponding vertical common voltage line and a corresponding horizontal common electrode; Disposing the first and second substrates such that the pixel and the horizontal common electrode face the vertical common electrode; And And injecting a liquid crystal material between the first and second substrates. Liquid crystal cells disposed in each of the unit regions divided by the plurality of gate lines and the plurality of data lines, vertical common voltage lines corresponding to the data lines, and corresponding data in response to scan signals on the corresponding gate lines. A first switch element for selectively connecting a pixel electrode of a liquid crystal cell corresponding to the line, and selectively connecting a vertical common electrode of a corresponding liquid crystal cell with a corresponding vertical common line in response to the scan signal on the corresponding gate line A liquid crystal panel having a second switch element; A data converter for converting the pixel data stream into the black level control data stream; A gate driver sequentially driving the gate lines on the liquid crystal panel; A data driver driving the data lines in response to a pixel data stream; And And a vertical common line driver for selectively driving each of the plurality of vertical common voltage lines in response to the black level control data stream. The method of claim 17, And the black level control data has an enable value when the pixel data has black gradation. The method of claim 17, And the data converter comprises a logic circuit which performs one of NOR and OR operations on pixel data. Converting the pixel data stream into a black level control data stream; Sequentially driving a plurality of gate lines on the liquid crystal panel; Driving a plurality of data lines on the liquid crystal panel in response to a pixel data stream; And Selectively driving each of a plurality of vertical common voltage lines on the liquid crystal panel corresponding to the data lines in response to the black level control data stream. 21. The liquid crystal display of claim 20, wherein the liquid crystal panel is A liquid crystal cell disposed in each of the unit regions divided by the plurality of gate lines and the plurality of data lines; A first switch element selectively connecting a pixel electrode of a corresponding liquid crystal cell with a corresponding data line in response to a scan signal on a corresponding gate line; And And a second switch element for selectively connecting a corresponding vertical common line and a vertical common electrode of a corresponding liquid crystal cell in response to the scan signal on the corresponding gate line.

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