KR101427517B1 - Method and apparatus for transmitting data - Google Patents

Abstract

The present invention relates to an apparatus and a method to transmit data which transmits data by applying pre-emphasis. According to an embodiment of the present invention, a method to transmit data in a method to transmit data inputted by bit stream includes: a step of detecting the pattern of input data; a step of determining a time delay value corresponding to the detected data pattern; a step of controlling the time delay of the input data in accordance to the determined time delay value; and a step of applying pre-emphasis to the input data of the controlled time delay.

Description

[0001] METHOD AND APPARATUS FOR TRANSMITTING DATA [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method and apparatus, and more particularly, to a data transmission method and apparatus for transmitting data by applying pre-emphasis.

As the image quality required by each display product increases, the amount of data to be transmitted increases greatly. The capacitance of each device is reduced by the scaling of the semiconductor process, and the processing speed of the data has been developed to the level that satisfies it. However, the channel development speed is not satisfied and is limited due to the attenuation phenomenon and noise added in the channel. In order to solve this problem, a receiver is required to compensate for the attenuation of the channel by adding an equalizer. In the transmitter, the pre-emphasis method for predicting the degree of attenuation of data in the channel to the output driver is mainly used. .

Pre-emphasis, which is widely used to compensate for channel effects in the transmitter, is a technique for amplifying the high frequency components of data using additional taps in the output driver. When pre-emphasis is performed, the high-frequency components of the data are amplified and the low-frequency components are not amplified. Therefore, a difference in the data amplitudes depending on the pattern of the data occurs, which increases the jitter of the output data. Therefore, it is important to optimize pre-emphasis without increasing the amount of jitter in the transmitter.

Patent Document No. 10-2007-0109418 discloses a method of generating a serialized signal by serializing n-bit parallel data signals, generating a delayed signal by delaying the serialized signal by a predetermined delay time, And generating a pre-emphasis signal by combining the serialized signal and the inverted signal, wherein the amplitude of the inverted signal is smaller than the amplitude of the serialized signal, A transmission method is disclosed.

However, the technique of applying the optimum pre-emphasis by reducing the jitter caused by the difference of the data amplitudes according to the pattern of the data is not disclosed in the patent document 10-2007-0109418.

Therefore, there is a need for research on techniques for implementing optimum pre-emphasis by reducing jitter caused by differences in data amplitudes according to data patterns.

It is an object of the present invention to provide a method and apparatus for transmitting data by applying optimum pre-emphasis by reducing jitter caused by a difference in data adaptation according to a pattern.

According to an aspect of the present invention, there is provided a method of transmitting data input through a bitstream, the method comprising: detecting a pattern of input data; Determining a time delay value corresponding to a pattern of the detected data; Adjusting a time delay of the input data by the determined time delay value; And applying a pre-emphasis to the input data whose time delay is adjusted.

According to an aspect of the present invention, there is provided a data transmitting apparatus for transmitting data input through a bit stream, the apparatus comprising: a pattern detector for detecting a pattern of input data; A delay value determiner for determining a time delay value corresponding to a pattern of the detected data; A delay adjusting unit for adjusting a time delay of the input data by the determined time delay value; A pre-emphasis unit for applying a pre-emphasis to the input data whose time delay is adjusted; And a control unit for controlling the pattern detecting unit, the delay value determining unit, the delay adjusting unit, and the pre-emphasis applying unit.

The method and apparatus for transmitting data according to an embodiment of the present invention can minimize jitter of output data in applying optimal pre-emphasis in a manner of reducing jitter caused by a data pattern.

In addition, according to one embodiment of the present invention, when applying pre-emphasis, a method of reducing jitter by applying a different delay degree according to a pattern is employed, so that the jitter of output data is obtained regardless of the semiconductor process, Can be minimized.

1 is a block diagram of a data transmitting apparatus according to an embodiment of the present invention.
2 is a flow diagram illustrating a data transmission method in accordance with an embodiment of the present invention.
3 to 4 are circuit diagrams of a pre-output driver of a data transmitting apparatus according to an embodiment of the present invention.

Hereinafter, a data transmission method and apparatus according to an embodiment of the present invention will be described with reference to the drawings.

As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. In this specification, the terms "comprising ", or" comprising "and the like should not be construed as necessarily including the various elements or steps described in the specification, Or may be further comprised of additional components or steps.

1 is a block diagram of a data transmitting apparatus according to an embodiment of the present invention.

1, the data transmission apparatus 100 includes a data input unit 110, a pattern detection unit 120, a delay value determination unit 130, a delay control unit 130, a pre-emphasis application unit 150, 160 and a control unit 170. [

The data input unit 110 can receive input data. The input data may be in the form of a bit stream. The current bit and the next bit in the input bitstream can maintain a constant delay (e.g., 1 UI). In the present specification, 1UI means a unit time set for driving a circuit.

The pattern detector 120 can detect a data pattern for a predetermined bit (e.g., a current bit, a 1 UI delay bit, and a 2 UI delay bit) in an input bitstream. The data pattern detection can be performed in real time. The pattern detector 120 can detect a data pattern by discriminating delay data using an AND gate and an OR gate. A specific example of the data pattern detection method will be described later.

In this specification, the current bit or current data means currently input data, and the delay data or delay bit means data to be inputted after a predetermined time later than the current input data (or input bit).

The delay value determination unit 130 may determine a time delay corresponding to the detected data pattern. The time delay value means a value used for delaying the current input data. The time delay value corresponding to the pattern may be set in advance. For example, if the data pattern is 010, the time delay value may be set to Ts1, and when the data pattern is 011, the time delay value may be set to Ts2.

The delay adjustment unit 140 may delay the current input data according to the determined time delay value. The time delay adjustment may be performed through a pre-output circuit including an NMOS transistor and a PMOS transistor. This will be described with reference to FIG.

The pre-emphasis application unit 150 may apply pre-emphasis to the input data whose time delay is adjusted. Pre-emphasis is a technique used to amplify the high-frequency components of data by using an additional tap on the output driver, which is widely used to compensate for channel effects in the transmitter.

The transmission unit 160 may transmit the data to which the pre-emphasis is applied.

The control unit 170 controls the data input unit 110, the pattern detection unit 120, the delay value determination unit 130, the delay control unit 140, the pre-emphasis application unit 150, and the transmission unit 160 .

2 is a flow diagram illustrating a data transmission method in accordance with an embodiment of the present invention.

First, the pattern detector 120 may detect the current input data and the delay data, and detect a data pattern for a predetermined bit (for example, a current bit, a 1 UI delay bit, and a 2 UI delay bit) in an input bitstream S210).

The delay value determination unit 130 determines a time delay value corresponding to the detected data pattern (S220). The time delay value may be pre-mapped according to a data pattern.

The delay adjusting unit 130 may delay the current input data based on the determined time delay value (S230). The reason for delaying the current input data is to prevent jitter due to the data pattern in the output driver with pre-emphasis.

The pre-emphasis application unit 150 receives the input data whose time delay is adjusted and applies pre-emphasis (S240).

The transmitting unit 160 transmits the data to which the pre-emphasis is applied (S250).

The steps S210 to S230 from the data transmission method to the pre-emphasis application step S240 may be performed through a pre-output driver circuit of the data transmission apparatus 100. [

3 is a circuit diagram of a pre-output driver of a data transmitting apparatus according to an embodiment of the present invention.

As shown, the pre-output driver circuit 300 includes an AND gate 311, an OR gate 312, a switch 320 for delay value adjustment, and a delay controller 330 ).

In the present embodiment, D '(n) is the current input data, D' (n-1) is data delayed by 1 UI from the current input data, and D '(n-2) do. Further, D (n) denotes output data of the pre-output driver circuit 300. In this embodiment, a data pattern is discriminated based on 3-bit input data including current input data and delay data. It also adjusts the time delay of the current input data when a transition of the data occurs (eg, 0-> 1 or 1-> 0).

The delay data D '(n-1) and D' (n-2) can be discriminated through the AND gate 311 and the OR gate 312.

For example, when the current data changes from 0 to 1, the delay data D '(n-1) and D' (n-2) Lt; / RTI > An OR gate 312 is used which can control the NMOS for further determining the above two cases and allowing the current to flow further.

The delay data D '(n-1) and D' (n-2) may have the case of (1,1) or (1,0) respectively at the moment when the current value changes from 1 to 0 have. An AND gate 311 is used which can control the PMOS for determining the above two cases and allowing the additional current to flow.

As described above, an AND gate 311 and an OR gate 312 can be used to determine the previous two delay bits.

The switch 320 may be externally adjusted to control the amount of time delay. The on / off state of each of the switches 320 can be set in advance according to the operation environment of the chip. The reason why the switch 320 is used is that the amount of current flowing through the MOSFET is different depending on the operating environment and the degree of data dependency jitter (DDJ) caused thereby is different. If you do not compensate for this properly (ie, you do not control the switch 320) and you keep it fixed, then a data-dependent jitter (DDJ) may occur. Therefore, in order to prevent this, the switch 320 is used so that the amount of current to be flowed from the outside can be adjusted.

The delay controller 330 can adjust the time delay of the current input data by controlling the amount of current by controlling the PMOS or the NMOS according to the determined two delay bits. The delay controller 330 includes a plurality of MOSFETs, and can adjust the time delay of current input data by adjusting the amount of current by the plurality of MOSFET operations.

According to an embodiment of the present invention, the delay of the current data D '(n) and the next delayed data D' (n-1) can be maintained at 1 UI.

4 is a circuit diagram of a pre-output driver for maintaining the delay of the current data D '(n) and the immediately following delay data D' (n-1) at 1 UI.

In FIG. 3, three tabs for adjusting the delay have been added, and the 1UI can be maintained as much as possible by compensating the delay to some extent. The circuit of FIG. 4 minimizes the delay difference difference between D '(n) and D' (n-1) by always monitoring the influence of the delay according to the pattern in the circuit shown in FIG. .

As described above, the data transmission apparatus 100 may apply pre-emphasis to prevent data from being attenuated by a channel. The data transmission apparatus 100 may detect the data pattern and delay the data differently in order to prevent jitter according to the data pattern in the output driver accompanied by the pre-emphasis.

The above-described data transmission method may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable recording medium. At this time, the computer-readable recording medium may include program commands, data files, data structures, and the like, alone or in combination. On the other hand, the program instructions recorded on the recording medium may be those specially designed and configured for the present invention or may be available to those skilled in the art of computer software.

The computer-readable recording medium includes a magnetic recording medium such as a magnetic medium such as a hard disk, a floppy disk and a magnetic tape, an optical medium such as a CD-ROM and a DVD, a magnetic disk such as a floppy disk, A magneto-optical media, and a hardware device specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like.

The recording medium may be a transmission medium, such as a light or metal line, a wave guide, or the like, including a carrier wave for transmitting a signal designating a program command, a data structure, and the like.

The program instructions also include machine language code, such as those generated by the compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

The above-described data transmission method and apparatus are not limited to the configuration and method of the embodiments described above, but the embodiments may be modified so that all or some of the embodiments are selectively combined .

100: Data transmission device
110: pattern detector
130: Delay value determination unit
140:
150: pre-emphasis application part
160:
170:

Claims (10)

A method of transmitting data to be input as a bitstream,
Detecting a pattern of input data;
Determining a time delay value corresponding to a pattern of the detected data;
Adjusting a time delay of the input data by the determined time delay value; And
Applying pre-emphasis to the time delay adjusted input data,
Wherein the step of detecting the pattern of the input data comprises the step of discriminating delay data for the current input data by using at least one of the AND gate and the OR gate. delete 2. The method of claim 1,
If the current input bit changes from 0 to 1, the OR gate is used,
Wherein an AND gate is used when the current input bit changes from 1 to 0. 2. The method of claim 1, wherein the time delay adjustment step
And a current amount adjustment is performed. The method according to claim 1,
Wherein the delay amount of the current input data and the next delay data is kept constant. A data transmission apparatus for transmitting data to be input as a bit stream,
A pattern detector for detecting a pattern of input data;
A delay value determiner for determining a time delay value corresponding to a pattern of the detected data;
A delay adjusting unit for adjusting a time delay of the input data by the determined time delay value;
A pre-emphasis unit for applying a pre-emphasis to the input data whose time delay is adjusted; And
And a control unit for controlling the pattern detection unit, the delay value determination unit, the delay control unit, and the pre-emphasis application unit. 7. The apparatus of claim 6, wherein the pattern detector of the input data comprises:
And an AND gate and an OR gate for determining delay data for the current input data. 8. The method of claim 7,
The OR gate is used when the current input bit changes from 0 to 1,
Wherein the AND gate is used when the current input bit is changed from 1 to 0. 7. The apparatus of claim 6, wherein the time delay adjuster comprises:
And adjusts the time delay by adjusting a current amount. The method according to claim 6,
Wherein the delay amount of the current input data and the next delay data is kept constant.

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