KR101408670B1 - Method for manufacturing thermoelectric module using silicon-mask - Google Patents

Abstract

The present invention relates to a method for manufacturing a thermoelectric device using a silicon mask and, more particularly, to a method for manufacturing a thermoelectric device, capable of simplifying a manufacturing process of a micro thermoelectric device and forming N-type and P-type semiconductor layers at high temperatures. According to the present invention, the thermoelectric device is manufactured by depositing the P-type and N-type semiconductor layers at high temperatures by deposition using the silicon mask.

Description

[0001] The present invention relates to a method of manufacturing a thermoelectric device using a silicon mask,

The present invention relates to a method of manufacturing a thermoelectric device using a silicon mask, and more particularly, to a thermoelectric device manufacturing method capable of simplifying a manufacturing process of a micro-thermoelectric device and forming an N-type and P-type semiconductor layer at a high temperature .

In addition, the present invention relates to a method of manufacturing a thermoelectric device that can reduce the number of cleaning processes and patterning processes due to the absence of a photoresist residue due to the use of a silicon mask.

The physical phenomena in which heat flow and currents interact with each other, such as the Seebeck effect and the Peltier effect, are collectively referred to as "thermoelectric effects".

And, the thermoelectric effect occurs in circuits bonded with dissimilar metals or heterogeneous semiconductors with different thermoelectric properties (thermoelectric properties).

If there is a temperature difference between the junctions of these dissimilar metals or hetero-semiconductors, the phenomenon of current generation in this circuit is called Seebeck effect. The Seebeck effect is widely used in the field of temperature measurement sensors and in the practical use of thermoelectric conversion devices using waste heat.

When a DC current is applied to a circuit obtained by bonding a dissimilar metal circuit or a hetero semiconductor, a phenomenon occurs in which one of the junction generates heat and the other absorbs heat. This phenomenon is referred to as a Peltier effect.

Such a Peltier effect is used for thermoelectric cooling various chips and devices including a CPU (Central Processing Unit).

As a technique for manufacturing such a thermoelectric element, there is a method of manufacturing a thermoelectric element by using a shadow mask. A view showing such a shadow mask is shown in FIG. The shadow mask of FIG. 1 has a membrane pattern layer 141 'and a membrane reinforcing layer 142'.

Referring to FIG. 1, a lower opening 140'-1 penetrating the membrane pattern layer 141 'is formed in the membrane pattern layer 141'. The lower opening 140'-1 extends from the lower end of the first lower opening 140'-1a and the lower end of the first lower opening 140'-1 a forming the upper layer of the lower opening 140'- And a second lower opening 140'-1b that forms a lower layer portion of the first lower opening 140'-1. The membrane pattern layer 141 'may be formed by depositing Ni or the like by a plating process.

Accordingly, the membrane pattern layer 141 'is formed with a lower membrane pattern 141'-1' in which the upper membrane pattern layer 141'-1 and the second lower opening 140'-1b, in which the first lower opening 140'- And a layer 141'-2. The upper membrane pattern layer 141'-1 and the lower membrane pattern layer 141'-2 are formed through a plating process.

Referring to FIG. 1, a membrane reinforcing layer 142 'is deposited on the membrane pattern layer 141'. An upper opening 140'-2 penetrating the membrane reinforcing layer 142 'is formed in the membrane reinforcing layer 142' so that the upper opening 140'-2 communicates with the lower opening 140'-1. .

1, the membrane reinforcing layer 142 'includes a silicon wafer pattern layer 142'-1, a first insulating pattern layer 142'-2, an adhesion assisting pattern layer 142'-3, The other side insulating pattern layer 142'-5, and the etching protection pattern layer 142'-6.

1, the one side insulating pattern layer 142'-2 is laminated on the lower side of the silicon wafer pattern layer 142'-1, and the adhesion auxiliary pattern layer 142'-3 is laminated on the other side insulating pattern layer 142 ' -2).

Referring to FIG. 1, the plating front-side pattern layer 142'-4 is laminated on the lower part of the adhesion assisting pattern layer 142'-3 so that the lower surface thereof is in contact with the upper surface of the upper membrane pattern layer 141'-1. The plating front-side pattern layer 142'-4 may have a structure in which a first plating electrode pattern layer 142'-4a and a second plating electrode pattern layer 142-4b are sequentially stacked. The first plating electrode pattern layer 142'-4a may be formed of titanium (Ti) or tantalum (Ta), and the second plating electrode pattern layer 142-4b may be formed of copper (Cu).

1, the other insulating pattern layer 142'-5 is laminated on the silicon wafer pattern layer 142'-1, and the etching protection pattern layer 142'-6 is formed on the other insulating pattern layer 142 ' -5).

According to the prior art, there is a need for a cleaning process to remove photoresist residues on the substrate.

Further, since the shadow mask is a soft material, it is difficult to deposit the P-type and N-type semiconductor layers at a high temperature.

Further, since the thermal expansion coefficient of the wafer differs from that of the shadow mask, residual stress is generated on the substrate.

In addition, a patterning process such as UV (Utraviolet) process, spin coating process, and strip process is required.

Korean Published Patent [10-2006-0050777]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a thermoelectric device for depositing P type and N type semiconductor layers at a high temperature in order to overcome the disadvantages of the prior art.

It is another object of the present invention to provide a method of manufacturing a thermoelectric device that removes residual stress caused by a difference in thermal expansion coefficient between a mask and a wafer.

It is another object of the present invention to provide a method of manufacturing a thermoelectric device that eliminates a photoresist residue to reduce the cleaning process.

It is another object of the present invention to provide a method of manufacturing a thermoelectric device capable of reducing the patterning process such as UV (ultraviolet) process, spincoating process, and stripping process.

One embodiment of the present invention provides a method of manufacturing a thermoelectric device using a silicon mask to accomplish the above-mentioned problems. The thermoelectric-element manufacturing method includes: sequentially forming a silicon oxide film and an electrode on one side of a substrate; Placing a first mask having a first electrode layer recess and a first opening connected to the first electrode layer recess on a lower surface of the silicon substrate so as to face the first surface of the silicon substrate; Depositing a semiconductor layer into the first opening by sputtering means; A semiconductor layer recess is formed at a lower end of the first mask to interpolate the deposited semiconductor layer, a second opening portion spaced apart from the semiconductor layer recess by a predetermined distance is formed, and the semiconductor layer recess and the second opening Depositing a second mask having a second electrode layer recess on the one side of the silicon substrate so as to face the first side of the silicon substrate; Depositing a hetero semiconductor layer different from the semiconductor layer in the second opening by the sputtering means; Removing the second mask and connecting the upper surface of the semiconductor layer and the hetero semiconductor layer formed on the different electrode to each other with a connection electrode plate; And attaching a thermally conductive cover to the surface of the connecting electrode plate.

Another embodiment of the present invention provides a method of manufacturing a thermoelectric device using a silicon mask. The thermoelectric-element manufacturing method includes: sequentially forming a silicon oxide layer and an electrode on one side of a first silicon substrate; Placing a first mask having a first electrode layer recess and a first opening portion connected to the first electrode layer recess on a bottom surface of the substrate so as to face the one side surface of the silicon substrate; Depositing a semiconductor layer into the first opening by sputtering means; Forming a silicon oxide layer and an electrode sequentially on one side surface of the second substrate; Placing a first mask having a first electrode layer groove and a first opening portion connected to the first electrode layer groove on a bottom surface of the substrate so as to face the first surface of the substrate; Depositing a hetero semiconductor layer different from the semiconductor layer in the first opening by the sputtering means; And joining and joining the second substrate to one side of the first substrate.

At this time, the substrate and the mask are made of the same material, and the material is silicon.

In this case, the semiconductor layer is an N-type semiconductor layer, and the hetero semiconductor layer is a P-type semiconductor layer.

In this case, the substrate and the mask have the same thermal expansion coefficient.

According to the present invention, it is possible to manufacture a thermoelectric device by depositing P-type and N-type semiconductor layers at a high temperature even at a high temperature because of deposition using a silicon mask.

Another advantage of the present invention is that it is possible to manufacture a thermoelectric device that eliminates the residual stress generated on the substrate by using the silicon mask and having the same thermal expansion coefficient as the silicon mask and the wafer.

In addition, another advantage of the present invention is that it is possible to manufacture a thermoelectric device which can reduce the cleaning process because there is no photoresist residue on the substrate using a silicon mask.

Another advantage of the present invention is that it is possible to manufacture a thermoelectric device capable of reducing the patterning process such as UV (ultraviolet) process, spin-coating process, and stripping process by using a silicon mask Points can be mentioned.

1 is a cross-sectional view of a shadow mask used in a method of manufacturing a thermoelectric device according to the prior art.
2 is a plan view showing an arrangement of electrodes 220 on a substrate of a thermoelectric device according to an embodiment of the present invention.
3 is a cross-sectional view of the substrate cut along the X-X 'axis in FIG.
4 is a view illustrating a process of manufacturing a thermoelectric device according to an embodiment of the present invention.
5 is a perspective view showing a thermoelectric device manufactured according to the process of FIG.
6 is a view showing a two-wafer process according to another embodiment of the present invention.

The terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms and the inventor may appropriately define the concept of the term in order to best describe its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention, and not all of the technical ideas of the present invention are satisfied. Therefore, various equivalents It should be understood that water and variations may be present.

Hereinafter, a method of manufacturing a thermoelectric device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing an arrangement of electrodes 220 on a substrate of a thermoelectric device according to an embodiment of the present invention. Referring to FIG. 2, the electrodes 220 are arranged on the substrate 200 in rows and columns at regular intervals. Of course, the " + "total end stage 201 and the" - " total end stage 202 are provided on the left side. The "+" and "-" leading and trailing ends 201, 202 are for illustrative purposes and the leading and trailing ends 201, 202 can be "-" and "+", respectively.

2, when an N type semiconductor layer (not shown) and a P type semiconductor layer (not shown) are formed on the electrode 220, current flows into the "+ " And exits to the extreme end 202 side. To make it easy to understand, you can think of an excel pipe, which is piped to the floor, arranged like the large intestine and small intestine of the human body. A diagram showing this for easy understanding is shown in Fig.

3 is a cross-sectional view of the substrate cut along the X-X 'axis in FIG. Referring to FIG. 3, only a portion of the electrode 220 in the plan view of FIG. 2 is cut along the X-X 'axis. Referring to this cross-sectional view, a silicon oxide film 210 is deposited on a silicon substrate 200. The silicon substrate 200 is made of single crystal silicon, and a silicon oxide film 210 is formed on one main surface of the substrate 200. The silicon oxide film 210 is used as a pad oxide film for stress relief and may have a thickness of about 30 to 50 nm.

The silicon oxide film 210 is deposited by chemical vapor deposition (CVD), low pressure CVD (LPCVD), or plasma enhanced CVD (PECVD). For example, the high temperature LPCVD or APCVD (atmospheric CVD) method is a method of depositing by supplying two or more source gases, PECVD deposition is reactive, such as the O _2, N _2O, O ₃ of TEOS (tetraethly orthosilicate) precursor a method to generate a gas by adding a gas or mixture of such as Ar, O _2, N _2O the SiH ₄ to the plasma to obtain a silicon oxide film in a gas phase state.

Titanium / platinum (Ti / Pt) 221, chromium (Cr) 222 and gold (Au) 223 are sequentially deposited on the silicon oxide film 210 by a sputtering process. The titanium / platinum 221, the chrome layer 222, and the gold layer 223 become the electrodes 220.

Accordingly, a substrate 200 having an arrangement as shown in Fig. 2 is provided.

4 is a view illustrating a process of manufacturing a thermoelectric device according to an embodiment of the present invention. Referring to FIG. 4, a process of forming an N-type semiconductor layer and a P-type semiconductor layer on a substrate 200 having an arrangement as shown in FIG. 2 is sequentially shown.

4A is a view showing a state in which a silicon mask 400 is placed on a substrate 200. FIG. Referring to FIG. 4A, the silicon mask 400 has an opening 401 through which the upper portion of the silicon mask 400 passes, and a first electrode layer recess 402 is formed at the lower end of the opening 401. The first electrode layer recesses 402 are formed in such a manner that the electrode 220 protrudes from the surface of the silicon oxide layer 210 so that the silicon oxide layer 210 and the silicon mask 400 are closely contacted with each other. Of course, the adhesion between the silicon mask 400 and the substrate 200 uses a polymer tape or a clamping means or the like.

Here, the silicon mask 400 is made of a silicon (Si) material. Therefore, since the silicon mask 400 and the substrate 200 use the same silicon material, the silicon mask 400 and the substrate 200 are extended together. In addition, residual stress does not occur on the substrate 200 during the sputtering process.

4B is a view showing an N type semiconductor layer 410 grown as a thin film by using a sputtering method. In addition, nanoparticles ionized by a sputtering apparatus (not shown) grow in the openings 401 of FIG. 4A to form a thin film of the N-type semiconductor layer 410.

Normally, sputtering is performed by introducing an inert material (mainly Ar gas) into a sputtering gas in a vacuum maintained chamber, applying a DC voltage between the substrate and the target (such as Cr / Ti) Collides with the target, and is repelled and flies to form a target material on the substrate. In the case of the N-type semiconductor layer 410, a Bi ₂ Te ₃ thin film which is a Bi-Te thin film is formed by using, for example, pure Bi and Te targets.

4C is a view showing a state in which the second silicon mask 430 is laid.

In the case of the P-type semiconductor layer 450, for example, (BiSb) 2Te3 is typically used. Referring to FIG. 4C, the second silicon mask 430 has an opening 431 through which the N-type semiconductor layer 410 is deposited on the left side. A two-electrode layer recess 433 is formed.

A second electrode layer recess 433 for extrapolating the electrode 220 is formed at the bottom of the second silicon mask 430. The second electrode layer groove 433 protrudes from the surface of the silicon oxide layer 210 so that the silicon oxide layer 210 and the silicon mask 430 are closely contacted with each other to reduce the gap therebetween. Here, the silicon mask 400 is made of a silicon (Si) material.

4D is a view showing a P-type semiconductor layer 450 grown as a thin film using a sputtering method. In addition, as described above, the nanoparticles ionized by a sputtering apparatus (not shown) are grown in the openings 431 of FIG. 4C to form a thin film of the P-type semiconductor layer 410.

4E is a view showing a state in which an N type semiconductor layer 410 and a P type semiconductor layer 430 are formed. 4E shows a state in which an N-type semiconductor layer 410 and a P-type semiconductor layer 430 are formed on the same electrode 220 of FIG.

4F is a view illustrating a state in which a P-type semiconductor layer 450a and an N-type semiconductor layer 410b formed on the first electrode 220a and the second electrode 220b are connected to each other by a connection electrode plate 470. FIG. Referring to FIG. 4F, a P-type semiconductor layer 450a formed on the first electrode 220a and an N-type semiconductor layer 450b formed on the second electrode 220b are formed on the connection electrode Lt; / RTI >

4E, the N-type semiconductor layer 410 and the P-type semiconductor layer 450 are deposited on the electrode 220 according to the electrode arrangement shown in FIG. 2, And is connected by the connecting electrode plate 470 so that a current flows between the electrodes 220.

5 is a perspective view showing a thermoelectric device manufactured according to the processes of FIGS. 4A to 4F. In addition, the thermoelectric element of FIG. 5 shows a thermoelectric device manufactured by a repeated arrangement of an N-type semiconductor layer and a P-type semiconductor layer. 5, the P-type semiconductor layer 450 and the N-type semiconductor layer 410 are connected to the electrodes 220. The P-type semiconductor layer 450, which is disposed at one end side, And the + electrode 201 connected to the outside is connected to the lower end surface of the N-type semiconductor layer 410 disposed on the other end side.

The P type semiconductor layer 450 and the N type semiconductor layer 410 are connected in series between the electrode 202 and the electrode 201 in a " That is, the "P" type semiconductor layer 450 and the N-type semiconductor layer 410 are arranged in the row arrangement 510 and the column arrangement 520.

A good thermally conductive substrate 500 is in contact with the electrode 220 connected to the upper surface of the P-type semiconductor layer 450 and the N-type semiconductor layer 410.

The substrate 200 is in contact with the electrodes 201, 202, and 220 connected to the lower surface of the P-type semiconductor layer 450 and the N-type semiconductor layer 410. Of course, the substrate 200 may be a thermally conductive material.

When a direct current is supplied between the electrode 202 and the electrode 201 and the electrode 201 is set to the plus side and the electrode 202 is set to the minus side, Type semiconductor layer 450 and the N-type semiconductor layer 410, the heat-absorbing substrate 200 is cooled by absorbing heat in the heat-conducting substrate 200 depending on the current direction, and the heat is emitted from the heat- do.

On the other hand, a load is connected between the electrode 202 and the electrode 201 to constitute a closed circuit. The thermally conductive substrate 200 is set to the low temperature side, the thermally conductive cover 500 is set to the high temperature side, When a temperature difference is given between the covers 500, a current flows through the closed circuit to obtain power.

Therefore, the basic configuration of the thermoelectric element is substantially the same, and the thermoelectric element can be used as a thermoelectric module and a thermoelectric cooling module since the temperature can be controlled by using the Pebble effect and the Sekebek effect.

6 is a view showing a two-wafer process according to another embodiment of the present invention. That is, FIG. 6A illustrates a state in which the N-type semiconductor layer 410 is formed on the first substrate 600 by FIGS. 4A to 4F.

FIG. 6B is a view showing a state in which the P-type semiconductor layer 450 is formed on the second substrate 600 by FIGS. 4A to 4F.

6C is a view showing a state in which the first substrate 600 of FIG. 6A is superimposed on the second substrate 610 of FIG. 6B. Therefore, it is possible to manufacture a thermoelectric device by a two-wafer process. Of course, in the case of the two-wafer method, a process of connecting the electrode plate as shown in FIG. 4F is not necessary.

 Of course, for this purpose, two silicon masks may be prepared, one of which has the same opening as that of 401 of FIG. 4A, and the other of which has openings formed at regular intervals. Alternatively, it is possible to use the same silicon mask structure, but the first substrate 600 may be rotated 180 degrees and then superimposed and bonded onto the second substrate 610.

Here, the first substrate 600 and the second substrate 610 may be made of a thermally conductive silicon. Therefore, it can be used as the above-described thermoelectric module and thermoelectric cooling module.

200: silicon substrate
201: + the extreme 202: - the extreme
210: silicon oxide film 221: titanium / platinum layer
222: chrome layer 223: gold layer
400: first silicon mask 401: opening
402: First electrode layer recess 410: N-type semiconductor layer
430: second silicon mask 431: opening
433: second electrode layer recess 435: semiconductor layer recess
450: P-type semiconductor layer 470: connection electrode plate
500: a good thermally conductive substrate
510: row array 520: column array
600: first substrate 610: second substrate

Claims (5)

Forming a silicon oxide film (210) and an electrode (220) on one side of the substrate (200) in sequence;
A first mask 400 having a first electrode layer recess 402 and a first opening 401 connected to the first electrode layer recess 402 is formed on the lower surface of the silicon substrate 200, Placing on one side of the silicon substrate (200) so as to face one side;
Depositing a semiconductor layer in the first opening (401) by sputtering means;
A semiconductor layer recess 435 is formed at the lower end of the first mask 400 to expose the deposited semiconductor layer and a second opening 431 spaced apart from the semiconductor layer recess 435 by a predetermined distance And a second mask 430 having a second electrode layer recess 433 formed in the semiconductor layer recess 435 and the second opening 431 and interpolating the electrode 220 is formed on the silicon substrate 200, Placing on one side of the silicon substrate (200) so as to face one side;
Depositing a hetero semiconductor layer different from the semiconductor layer in the second opening (431) by the sputtering means;
Removing the second mask 430, and connecting the hetero semiconductor layer and the upper surface of the semiconductor layer formed on the different electrode 220 to each other with a connection electrode plate; And
Attaching the thermally conductive cover (500) to the surface of the connecting electrode plate
The method of manufacturing a thermoelectric device using the silicon mask according to claim 1,
delete The method according to claim 1,
Wherein the substrate (200) and the mask are made of the same material, and the material is silicon.
The method according to claim 1,
Wherein the semiconductor layer is an N type semiconductor layer and the hetero semiconductor layer is a P type semiconductor layer.
The method according to claim 1,
Wherein the substrate (200) and the mask have the same thermal expansion coefficient.

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