KR101389030B1 - Method and apparatus for reconditioning a carrier wafer for reuse - Google Patents

Abstract

The disclosure generally relates to the deposition of thin or thin foil materials, and more particularly to the deposition of epitaxial single crystal or pseudo single crystal silicon films (epi films) for use in the manufacture of high efficiency solar cells. In operation, a method of reducing the repayment cost of a reusable substrate or template used in the manufacturing process of silicon and other semiconductor solar cells and extending the reusable lifetime is disclosed.

Description

METHOD AND APPARATUS FOR RECONDITIONING A CARRIER WAFER FOR REUSE}

Cross-reference to related application

This application claims priority to US Provisional Patent Application No. 61 / 490,562, filed May 26, 2011, which is hereby incorporated by reference in its entirety.

This application is also a partial continuing application of US Patent Application No. 13 / 341,976, filed December 31, 2012, and a partial continuing application of US Patent Application No. 13 / 209,390, filed August 13, 2011, Both texts are incorporated herein by reference.

FIELD The present disclosure generally relates to the field of photovoltaic power generation, and more particularly to the field of repeatedly manufacturing thin film photovoltaic substrates using semiconductor templates.

Crystalline silicon (including polycrystalline and monocrystalline silicon) is the most common absorber material in commercial photovoltaic applications. The relatively high efficiency, combined with abundant materials and associated with mass production crystalline silicon solar cells, is of interest for continued use and improvement. However, the relatively high cost of the crystalline silicon material itself limits the widespread use of such solar modules. Currently, the "wafering" cost of crystallizing silicon and cutting the wafer accounts for about 40% to 60% of the final solar module manufacturing cost. If more direct methods of manufacturing wafers are possible, great advances can be made in reducing the cost of solar cells.

Various methods are known for growing a single crystal or quasi single crystal semiconductor such as silicon and peeling or transferring the grown wafer. Regardless of these methods, the low cost epitaxial silicon deposition process achieved by the mass production valuable low cost method of forming the exfoliation (sacrificial liftoff separation) layer is a requirement for wider use of silicon solar cells.

Another requirement is the availability of a reusable template to repeatedly perform a sequence of delamination layer formation, thin film deposition, on-template processing, thin film delamination, template recovery / reconditioning.

In the microelectronics industry, economies of scale are achieved with greater yields by increasing the number of dies (or chips) per wafer, scaling wafer size, and improving chip functionality (or integration density) per successive new product production. do. In the photovoltaic industry, low cost and high productivity equipment is used to achieve economic feasibility through the module manufacturing process and the industrialization of solar cells. Further economics are achieved through the reduction of the cost of the raw materials through the reduction of the materials used per watt output of the solar cell (also by eliminating the consumption of expensive materials and replacing them with cheaper materials).

In order to achieve the economics required for the photovoltaic industry, process cost modeling is being investigated to identify and optimize equipment performance. Several categories of costs, such as fixed costs (FC), unusual costs (RC), and yield costs (YC), make up the total cost situation. FC consists of items such as equipment purchase price, installation cost, robotics or automation cost. RC consists primarily of electricity, gas, chemicals, operator salaries, and maintenance technical support. YC can be interpreted as the total value of parts lost during production.

In order to achieve the reduced total cost of ownership (CoO) figures required by the solar sector, all aspects of the cost situation must be optimized. The characteristics of the low cost process are (in priority) 1) high productivity, 2) high yield, 3) low RC, and 4) low FC.

To design high productivity and economical methods and process equipment, it is necessary to fully understand the process requirements and incorporate those requirements into the equipment architecture. High yield demands robust processes and reliable equipment as equipment productivity increases, and so is yield cost. That RC is also a requirement for the whole that CoO. RC may affect plant site selection based on, for example, local power costs or availability of bulk chemicals. FC, though important, is diluted in importance by equipment productivity.

Thus, high productivity, reliable and efficient manufacturing process flows and equipment are essential for low cost solar cells.

Thus, there is a need for a high productivity thin film deposition method and system. In accordance with the disclosure, a method of reconstructing a reusable semiconductor template that provides significant cost savings in the manufacture of a thin film semiconductor substrate (TFSS) is disclosed.

The disclosure relates generally to the deposition of thin or thin foil materials, and more particularly to the deposition of epitaxial single crystal or pseudo single crystal silicon films (epi films) for use in the manufacture of high efficiency solar cells. In operation, a method of reducing the repayment cost of a substrate or template used in the manufacturing process of a silicon solar cell and extending the reusable life is disclosed. In one embodiment, the method includes grinding the reusable template to remove deposited residue.

These and other advantages of the disclosure, together with novel additional features, will be apparent from the description provided herein. This Summary is not intended to be an exhaustive description of the disclosure, but rather to provide a brief description of some of the functions of the disclosure. Other systems, methods, features, and advantages provided herein will be apparent to those skilled in the art upon reading the following brief description and detailed description of the drawings. It is intended that all such additional systems, methods, features, and advantages be included herein within the scope of the claims.

The features, properties, and advantages of the disclosure will become more apparent from the following detailed description, taken in conjunction with the drawings, wherein like reference numerals designate like features.
1A-1C illustrate one embodiment of forming surface features on a reusable semiconductor template.
FIG. 2A illustrates a patterned semiconductor template, porous semiconductor multilayer, and TFSS. FIG.
2B is an electron micrograph of a flat template with a sacrificial layer having two different porosities.
3A illustrates a hexagonal patterned semiconductor template, porous semiconductor multilayer, and TFSS.
3B is a photograph of the exfoliated hexagonal TFSS of FIG. 3A.
4 is an electron micrograph of the interface between the template and the TFSS.
5 shows a TFSS ready to be peeled from the template.
6A illustrates two templates with different amounts of TFSS overdeposition.
6B illustrates TFSS peeled off from a template.
6C illustrates the overdeposited TFSS removed from the template.
FIG. 6D illustrates the use of grinding tape to remove residual TFSS material from the template. FIG.
FIG. 6E illustrates the use of an edge grinder to remove residual TFSS material from a template. FIG.
6F illustrates the use of a laser at various angles of incidence to remove residual TFSS material from the template.
6G illustrates removal of excess front side TFSS material by grinding.
7A-7C illustrate the main process steps of a three-dimensional structural template when the three-dimensional structural template is reconstructed in accordance with the disclosure.
8A and 8B illustrate the main process steps of a three-dimensional structural template when the three-dimensional structural template is reconstructed to mitigate defect areas.
9A-9C illustrate key fabrication steps in the adjustment of a wafer in accordance with the disclosure.
10A and 10B illustrate two process flow embodiments illustrating key fabrication steps for fabricating high efficiency crystalline thin film solar cells in accordance with the disclosure.
11A and 11B are cross-sectional views of a template in accordance with the disclosure.
12 is a cross-sectional view of the template after multiple reuse cycles.
13 is a cross-sectional view of a template in anodization equipment.
14 and 15 illustrate two parallel bevel grinding embodiments in accordance with the disclosure.
16A, 16B, 16C illustrate a device for removing residue from a template.
17A and 17B illustrate a device for removing residue with strong holding force.
FIG. 18 illustrates a thermal induced cleave stationary on a release layer. FIG.
19 is a process flow diagram illustrating one embodiment of a structure for solar cell thin film semiconductor film edge trimming.

Although the present disclosure is described with reference to specific embodiments, those skilled in the art can apply the principles described herein to other areas and / or embodiments without undue experimentation.

In operation, particularly in the photovoltaic art, the disclosure enables low cost fabrication of thin film substrates used in solar cell manufacturing by templates that can be used repeatedly to make thin film substrates. The field of the present disclosure includes several apparatuses and methods for handling templates used to create thin film substrates and manufacture thin film substrates, with the goal of restoring the template to be reused more times.

The process of manufacturing thin or thin foil epitaxial solar cells involves using single crystal silicon or a suitable crystalline semiconductor material wafer as a reusable template. The present disclosure includes process flows, methods, apparatuses, and variations thereof that allow the repeated use of templates used in the manufacture of thin film layers that are subsequently processed to be solar cells.

The present disclosure may include a starting crystalline semiconductor wafer (called a template) with accurate resistance to enable anodization to form porous semiconductor material on one or both sides. The semiconductor used may comprise crystalline silicon, and in particular may comprise single crystal silicon. The template outline can be any suitable shape, including rounded, square (with or without notches or flats), or pseudo squares with rounded corners, truncated edges, or chamfered edges, and the template is also planar, approximately It may be planar or may have a three-dimensional structure. The porous semiconductor material may consist of several layers having discrete porosity or differential porosity. At least one portion of the porous semiconductor layer system functions as a designated weakening layer that facilitates separation of the TFSS from the template.

The present disclosure includes the use of reusable templates to repeatedly make thin crystalline solar cell substrates from a template, during which time the solar electric substrate can be made on one side of the template or on both sides of the template. Although the figures in this disclosure deal specifically with single-sided processing, it is understood that all embodiments of the present disclosure apply in the case of double-sided substrate processing using both sides of the template as well as single-sided substrate processing to essentially manufacture a solar cell substrate. Can be considered

With respect to the starting wafer, various structural architecture options are described below, but the wafer and the resulting template may be of any shape, planar, textured, or have any three-dimensional structure. In the simplest embodiment, the template may be essentially flat, ie the surface is cut, wrapped or ground, etched, ground, for example by removing saw damage. Or may even be of any selected surface quality, such as mirror polished. In another embodiment, the wafer may be textured using alkali random texturing, for example, prior to formation of the porous semiconductor layer system described above. Thus, the textured surface is directly transferred onto the thin film solar cell substrate. As a third alternative, the template can be a three-dimensional structure created using a process such as patterned wet or dry etching. Such a template having a three-dimensional pattern can be obtained by using photolithography and patterning techniques such as wet or dry etching, but is not limited to this example.

An example of a process for forming a three-dimensional template is described with reference to FIGS. 1A-1C. In FIG. 1A, a starting wafer 100 is provided. To form a three-dimensional structure, a hard mask is typically formed using, for example, thermal oxide or other deposited etch resistive layers or etch resistive layers, such as deposited silicon nitride or silicon dioxide, as materials, but such examples It is not limited. A hard mask layer (SiO ₂ ) 102 is shown formed on the surface of the wafer 100. The desired pattern of photoresist 104 is then lithographically patterned onto hard mask layer 102. In FIG. 1B, the wafer is located in a holder / chamber 106 and sealed with an O-ring 108 to protect the front almost. The hard mask layer 102 is then etched to produce the desired pattern, removing all hard masks except the hard mask underneath the remaining photoresist.

In FIG. 1C, an optional heated concentrated alkali wet etched through dry etching such as deep reactive ion etching (DRIE) or using chemicals such as potassium hydroxide, sodium hydroxide, tetramethyl ammonium hydroxide (TMAH) or the like. Semiconductor etching process is employed through wet etching such as concentrated alkaline wet etch. This creates the desired pattern on the surface of the wafer as shown in the example of FIG. 1C which includes the large inverted pyramid structures 112 and the small inverted pyramid structures 110 defined by the ridge 113. do. Finally, the photoresist and hard mask are stripped from the wafer and the wafer is cleaned. Thus, the porous semiconductor is ready to be formed on the textured surface. Other similar processes are readily derived from the figures by those skilled in the art.

Three-dimensional template patterning is shown to include more embodiments in most of the figures of the present disclosure. However, unless otherwise noted, the drawings, process flows, methods, and apparatus of the present disclosure are uniformly applicable to flat or randomly textured templates.

With the use of a patterned or non-patterned template, the subsequent process step is the formation of a porous semiconductor (by anodization, such as wet anode etching in HF-based chemicals), followed by rinsing and drying as needed. Porous semiconductors such as porous silicon on the crystalline silicon template are formed at least in cross section of the template. In the case where the semiconductor is silicon, the process of forming porous silicon is disclosed in the existing literature, for example in US Patent Application Publication No. 2011/0030610, the entirety of which is incorporated herein by reference. As shown in FIG. 2A, porous semiconductor formation involves the formation of at least one low current low porosity region 114 and at least one high current high porosity layer 116 closer to the template 120 at the surface. can do. Importantly, a single porous layer or differential porous layer may be used.

The template with the formed porous semiconductor layers can then be transferred to an epitaxial deposition reactor in which an epitaxial layer is deposited on at least a cross section of the template. 2A shows an epitaxial layer 118 deposited on top of the porous semiconductor layer system. 2B is a photograph of a porous semiconductor bilayer structure on a flat template 122 with a low porous layer 124 on top and a high porous layer 126 below.

3A is a diagram illustrating the deposition of an epitaxial silicon layer 134 on a porous silicon layer 132 formed on a three-dimensional hexagonal template 130. 3B is a top view of the exfoliated epitaxial thin film silicon layer, such as the epitaxial silicon layer 134 of FIG. 3A after exfoliation from the hexagonal template.

Prior to epitaxial deposition, during the ramp-up phase, or during a separate pre-deposition time, the template is heated in a hydrogen atmosphere for various uses, and the upper layer of the porous semiconductor is reflowed to simulate the ultrathin seed layer of the semiconductor. The single crystal growth surface QMS is formed again. In addition, hydrogen baking functions to reduce any oxide semiconductor back to elemental form. In addition, the highly porous semiconductor layers are combined to form a weakening layer that can function as a peel boundary between the subsequently grown layer and the template.

If the semiconductor is silicon, during the initial stage of deposition or baking, reflow can be assisted by small amounts of chlorine-free species such as silanes or using very low flow rates of other silicon containing gases such as trichlorosilane (TCS). have. This is one option for process components that function to safely prevent mechanism malfunctions that may occur during incomplete reflows, described below. Other problems and mechanism malfunctions that may occur during reflow are disclosed in US patent application Ser. No. 13 / 209,390, filed August 13, 2011, which is incorporated herein by reference in its entirety.

There is a potential mechanism malfunction that can occur during reflow. A solution to this mechanism malfunction is part of the present disclosure, and as the template is heated in a semiconductor deposition reaction apparatus such as, for example, an epitaxial reaction apparatus, the template comes into contact with the susceptor at multiple locations. These contact points can contribute to the non-ideality of the reflow of the porous semiconductor layer described above. These contact points can also contribute to the local wear of the porous semiconductor layer. As a result, the porous semiconductor layer can include local regions that are not closed.

An example of a mechanism malfunction is illustrated in the photograph of FIG. 4, showing a template 138, a QMS layer 140 (which typically contains some entrapped holes), and a deposited epitaxial layer 142. do. As deposition begins after reflow, two phenomena can be observed, namely a) deposition of the material directly onto the template base through the QMS 140 layer. Fused spot 144 is an example of this phenomenon. These regions do not have a weakened sublayer and thus resist subsequent peeling processes (described below). In the case where the non-closed area is sealed immediately after the start of the deposition, there is a possibility that the deposition gas is trapped under the upper deposition layer. Such deposition gases may contain etching components such as chlorine containing species as a byproduct of the deposition reaction of silicon from the TCS molecule. Such byproducts may contribute to the subsequent etching of the template material. The etched and volatilized template material may be redeposited on the top layer, thereby peeling off the chlorine containing species again. In FIG. 4, some redeposited template material 146 can be seen. Thus, in a pseudo-sealed local environment, the process can continue and observe severe template etching up to several micrometers. One option to avoid this etching and redeposition mechanism is to start deposition using a reactant that does not have etching species as a byproduct. One example of such a reactant is silane in the case of silicon deposition. Another option to avoid deposition directed directly onto the template and local etching of the template is to properly form the contact area that the template shares with the susceptor. Low contact areas are preferred with moderately large radii in the contact areas. This is necessary to enable a uniform thermal ramp and profile in and between the templates, with a suitable heater configuration.

For the epitaxial deposition process, the epitaxially deposited TFSS may include an in situ emitter in situ deposited in the semiconductor deposition chamber. The emitter may also be added later as an ex situ emitter external to the epitaxy chamber. The structure on the template may have an emitter above (emitter last during deposition) or below (emitter first during deposition). Epitaxial or non-epitaxial deposition may or may not include an appropriate dopant gradient designed to assist the desired flow of generated carriers through the device.

The layer structure of the semiconductor thus deposited on the weakening layer on the high temperature capable template is very valuable. This can carry a thin film on a solid template, allowing greater flexibility for the so-called on-template processing that follows.

In this on-template process, the template is a thermal process such as oxidation or film deposition such as thermal oxidation, pulsed nanoseconds (ns), pulsed picoseconds (ps) or scribing, doping, ablation, or the like. Other laser processes, lithography, screen printing, stencil printing, inkjet printing, aerosol printing, spray coating or etching, ion implantation, impregnation or single side cleaning, etching or deposition (plating), lamination, die attach or bonding, peeling, surface Move and support thin, brittle TFSS across several on-template processing steps including chemical vapor deposition (CVD) and physical vapor deposition (PVD) processes such as wet chemical texturing or dry texturing, surface rinsing, cleaning and drying. Function as a carrier, but are not limited to these examples. The unique feature here is that the template is clean, compatible with solar cells, rigid and rigid, resistant to high temperatures, and reworkable.

After proper on-template treatment, the TFSS may be stripped from the template carrier (optionally after being reinforced with a backplane sheet laminated, coated, printed, or otherwise attached to the TFSS). A conceptual diagram of peeling the TFSS 154 from the template 150 along the porous sacrificial layer 152 is shown in FIG. 5. Peeling can be performed with or without the use of a temporary or permanent reinforcing plate or sheet that is attached to the epi layer prior to epi peeling. The reinforcement plate or sheet may or may not include a structure such as a dielectric or conductive cell interconnect material at this time or later. If used, the reinforcement plate may include holes or other plurality of conductive locations that enable electrical contact of the TFSS through or around the reinforcement plate, which holes may be present during TFSS peeling or may be formed later. have. Suitable reinforcing materials may include plastics such as silicon, glass, silicon-aluminum alloys, prepregs or other dielectric adhesives, metals such as polymers, aluminum, ceramics, or combinations thereof. At appropriate times prior to exfoliation, boundary cutting or formation of the TFSS region to exfoliate can be achieved using, for example, a laser. 4 illustrates boundary cut 156 surrounding TFSS 154.

This boundary cutting can be performed before or after exfoliation of the TFSS. Depending on the reinforcement process and the material, it may be advantageous to perform the cutting both before and after peeling. Boundary cuts also function to weaken thin TFSS and thus facilitate easier peeling. Another potential way to facilitate easier peeling is to use grinding or otherwise wear methods that are preferably applied to the edges of the template. By doing so, the TFSS epitaxial layer region at the edge of the template can function as a weak spot, from which point peeling can be initiated. This preliminary delamination grinding can also facilitate air flow into the weakened region between the TFSS 154 and the template 150, thereby enabling pressure equalization and eliminating pressure differential induction resistance to delamination movements. Can be. Peeling itself may be performed by using local weak areas that function as a starting position for peeling.

Optionally, a pulse force can be applied, for example, by pulsing a vacuum on both sides of the template and the substrate sandwich. In this way, the peeling process can be extended over location and time (not different from opening the zipper) rather than having to overcome the atmospheric holding force plus full area bonding force on the template. Alternatively, during the process of essentially keeping the TFSS partially delaminated with the template, in order to avoid excessive stress and potential cracking of the active TFSS layer, the delamination is initiated at the edge or corner of the substrate and thereafter This can be done from.

After exfoliation of the active TFSS, a thin film deposited outside of the active area may remain, especially if the template is somewhat oversized relative to the active TFSS. 6A shows two possibilities. The template 200 has a porous semiconductor layer 202 extending beyond the edge of the TFSS 204. This does not cause a problem in peeling.

However, conventional CVD deposition processes can deposit materials not only on the front but also on the back and edges of the template, depending on the design. The degree of membrane coverage is illustrated in template 210. Thick semiconductor layer deposition in the bevel region may be undesirable. Depending on the process, backside deposition may be detrimental to subsequent processing, or in the case of double sided treatment, it may be desirable if backside deposition produces a significant film compared to frontside deposition. Instead of the template 210, various precautions can be taken to be a template such as the template 200. One mode for avoiding or minimizing backside and bevel deposition is to use a neutral gas such as hydrogen as a purge gas near the backside and edge of the template during the deposition step. Another mode for avoiding or minimizing backside and bevel deposition is to use a shadow mask to mask areas where deposition is unnecessary from the deposition gas. A third mode for reducing backside and bevel deposition is to use a susceptor design with a large surface area or else use an optimized geometry that can function to preferentially deposit material from the gas phase. Depletion of deposition gas in unnecessary areas. Deposition processes may have preferred locations and orientations where the material is deposited more or less in undesirable areas. It may be advantageous to balance deposition of undesirable materials over multiple reuses of the same template. To this end, template orientation can be tracked as needed, and specific changes in orientation or position can be programmed as part of the production flow.

In the template 210, the porous silicon layer 212 partially wraps around the edge of the template, while the TFSS 214 wraps further. In situations where the TFSS extends beyond the edge of the porous semiconductor, other methods may be employed to remove portions of the TFSS that are in direct contact with the template.

6B illustrates TFSS peeling in the case of template 200. TFSS 204 is peeled off, with little or no edge residue. After exfoliation, the TFSS 204 may be cut to a desired size by the laser 206.

FIG. 6C shows the template 210 in which the TFSS extends beyond the edge of the porous semiconductor layer or the porous semiconductor is not formed without porosity or thickness in the bevel area suitable for easy peeling off of the TFSS. The TFSS 214 is cut to a predetermined size by the laser 216 and then peeled off from the template 210. After exfoliation, the remaining film can be subsequently removed. The portion 218 coupled to the porous semiconductor layer and not directly coupled to the template 210 is compressed air, high pressure water or elevated pressure water or other suitable fluid, taping-detapping process, sonic (ultra or megasonic). It may be removed by using a machining process such as grinding or wrapping the remaining film away from the energy or template. Grinding can be accomplished using, for example, grinding materials or soft materials that shear excessive thin film deposits, which are abrasive and have an appropriate hardness relative to the hardness of the semiconductor. The latter takes advantage of the fact that the excessive binding force of the material is smaller and controlled by the weakening layer between the thin film and the template. Excess thin films can also be removed by appropriate chemical etching. Appropriate chemical etching may be selected to produce good dopant concentration or composition based selectivity between the deposited film and the template. It may also utilize controlled local etching.

The deposited thin film can be removed in a single wafer unit or in batch mode. The removal processes described so far are designed to remove material in the flat portion of the template that extends at least outside the active area and onto the bevel of the template at the bevel edge. Other methods may be used to remove the remainder 220 of the TFSS that is directly bonded to the template 210 due to the local absence or incomplete quality of the porous semiconductor layer.

Independently of the foregoing precautions, it may be advantageous to remove excess deposition material in the bevel or back region. Removal of such excess deposition material may be performed after each reuse cycle or after several reuse cycles and may be repeated throughout the life of the template. FIG. 6D shows the removal of residue 220 and local imperfections 222 using grinding tape 224, and FIG. 6E shows the use of a machine tool for grinding, polishing or else a grinding device. do. By using such a device, excessive deposition material in the bevel or backside region can be reduced or eliminated completely. In the case of tape-based grinders, the template can be rotated in the presence of tape, typically embedded with diamond or silicon carbide. For non-circular template geometries such as squares or pseudo-squares, the removal setting must be different, for example, the template is not rotated and is laterally moved, swiveled, or oscillated, or the tape retention / feed mechanism. It can be moved, swiveled, or oscillated. The removal process may be adjusted to preferentially remove material in areas where the material is more heavily deposited. Removal of the deposited material at different points in the bevel or back region can be accomplished by attaching the tool, tape, or sheet at different angles, inputs, or locations towards the template. Other removal embodiments for the deposited material will be apparent to those skilled in the art. An alternative process of this type of mechanical removal of excess deposits from a template is to use appropriate chemicals applied locally to remove excess deposits from the template.

In FIG. 6E, a precision grinding wheel 226 (or abrasive wheel or slurry) is used to remove the film around the edge of the template 210. However, this may leave a residue 228 on the rear side that may be removed using, for example, the rear grinder 230. It is also conceivable to combine the functions of the bevel grinding wheel and the edge back grinding wheel into one tool.

Another process to replace tape, sheet, or precision bevel grinding / polishing steps is to remove the bevel and underside of the template and reshape the bevel using a direct or water jet guided laser. The effect of the laser based bevel material removal process is shown in FIG. 6F. This method may have the advantage of enabling particularly precise control of the dimension. Combinations of the above methods are also possible. As shown, the template 210 was rarely removed or not removed at all by the laser edge ablation employed in FIG. 6F.

In some cases, the processes described above in conjunction with FIGS. 6C-6E still leave some unnecessary extra TFSS material on the back and front sides of the template. In this case, as shown in FIG. 6G, the grinder 232 may be used to remove the material. If this is not done, the next TFSS generated on the template 210 due to the remaining front-side TFSS material "fixes" at that point, making peeling more difficult. This problem can be alleviated by removing excess material before reusing the template.

After removing the unnecessary TFSS material by any method, a conventional flow may, for example, first make the template reusable to withstand repeated reuse, and secondly, to remove the sacrificial sacrificial layer. Removes the remainder, then removes metal contaminants that are detrimental to the lifetime of subsequent TFSSs to be deposited on the same template, and finally removes harmful residues of any on-template processes such as organic or metal containing residues. Reusable washes that function to do so. Typically, after a reuse wash, the template is again subjected to a porous semiconductor forming process, thereby forming another peel off sacrificial layer. Subsequent deposition of the thin film to be exfoliated is then followed. Subsequent processing continues as described above.

Residual deposition extending to the backside of the template may be detrimental to further processing and may accumulate as the template repeatedly undergoes sacrificial layer formation / deposition / additional treatment / peel / post peeling treatment. Residual deposition on the back side can cause template surfaces that are detrimental to handling and not smooth and can cause the template to be destroyed. Thus, avoidance or removal of the backside deposition material (described above) may be advantageous. This can be done after each reuse cycle or after several reuse cycles and can be repeated over the life of the template. These methods can be done by removing material from the complete backside area or by only locally removing material at the wafer edge that is deposited primarily on the backside edge.

Templates are high value raw materials for the whole process. Thus, any process that functions to extend the potential number of deposition cycles (template reuse cycles) that a template can maintain is substantially added to the value proposition (by reducing the cost of crediting a template per cell). Thus, in the case of peeling or removing the TFSS film or defective processing on the template, the template may go through an adjustment process. This adjustment process may consist of grinding and / or grinding of the entire area of the template or only the problematic parts of the template. After continuous adjustment, the template can be re-entered into the process loop and resume reuse.

Grinding and / or grinding may be accomplished using single or double side grinders / polishing machines. The grinding / polishing process is chosen according to the needs of the surface finish. The above-described TFSS for forming a substrate for a solar cell later does not depend on the mirror polished surface finish of the substrate. Therefore, it is important to point out that a porous semiconductor sacrificial layer can be formed on a template surface that does not have to start as a mirror polished semiconductor surface. It is not known at what stage the incomplete treatment of the substrate occurs and if the thickness is known, the HVM-compatible grind / polishing process uses the minimum amount of material from the starting template, so that multiple templates at the same time in the grinder / grinder It is advantageous to inspect the templates and classify them into thickness ranges in one step following the peeling process so that they can be processed to the target thickness. Classification of local residues and thicknesses from the foregoing depositions can be done simultaneously with suitable equipment, such as optical, capacitive, or gas back pressure based detection.

TFSS that has been peeled from the template carrier and has undergone several processes on the template can be further processed after peeling. Various embodiments are available for further handling for sufficient layer thickness of TFSS and TFSS, which can be self-supported and handled through further processes as is. If the template used to deposit the TFSS material has a structure for forming three-dimensional structures such as pyramids, arrays of prisms, or other geometric three-dimensional shapes, the TFSS can self-support even with very small amounts of deposited TFSS material. have. This structural feature is a potential advantage of 3D templates and TFSS. If the layer thickness is not sufficient for the TFSS to self-support, the TFSS may be supported during further processing through a suitable support plate, sheet, or film.

The goal of the disclosed methods is to extend the useful life of these templates and to reduce the cost of repayment of making and using these templates. This is referred to herein as " adjustment material " with pseudo doping or at least suitable doping, to form porous semiconductor / silicon on these templates by anodization (or anode etching) using an appropriate doping level of epitaxial deposition. This can be accomplished by adding a similar material called. For example, if the starting template consists of p + doped silicon, the epitaxial film is also in-situ doped with a p-type dopant, such as boron (p +), and the added adjustment material is appropriately doped (p + doping) using an anodic oxidation process. To form a porous layer.

This deposition process can be used whenever needed or whenever advantageous, such as when each template reuse cycle or preferably each of multiple template reuse cycles or template thicknesses is smaller than a desired value, to add thickness and material strength. .

In general, such adjustment materials can be used to a) extend the useful life of a template that is defective or very thin (in terms of the number of uses of the template reuse cycle), b) allowing the template to provide a longer useful life cycle and A thicker template can be provided that lowers the cost of sugar repayment template, and c) improves / planarizes the surface of the starting wafer to provide a smooth surface for subsequent processing, and d) is more uniform over the lifetime of the template. Template thickness ranges can be provided, thereby minimizing process variability that can be caused by excessively different template thicknesses, such as variability with respect to the thermal mass of the template, and are not limited to this example of variability.

As noted above, after the TFSS has been stripped from the template, the template may repeat this on-template treatment, removal process, adjustment process including formation of the same porous silicon (PS), deposition of TFSS, and attachment or adhesion of an optional support backplane. And further processing steps using surface etching / cleaning and other processes to be rough. During these cycles, the template does not maintain thickness.

However, practically there is a limit to the acceptable template thickness loss and because of the material thickness loss, the template strength can be reduced and the breakage rate of the template can be excessive, resulting in significant yield loss.

To avoid these template thickness loss shortcomings, the disclosed methods extend template life by thickening the template with a similar doping, crystalline, preferably epitaxial or otherwise pseudo epitaxial film. Here, the pseudo epitaxial film is defined as a film grown on a template which is a pseudo single crystal template from a silicon wafer produced from a pseudo single crystal ingot. This process is outlined in FIGS. 7A-7C showing a template of a three-dimensional structure as one exemplary embodiment, and planar, approximately planar, and randomly pre-textured templates can employ the same methods. . As the template 300 goes through TFSS fabrication processes, the thickness of the template shown in FIG. 7A as the initial thickness hA is reduced to a smaller thickness hB as shown in FIG. 7B (for example, the thickness reduction is a constant rate). Not shown). In FIG. 7A, the ridges of the inverted pyramids 302, which are three-dimensional in structure, note that the front side template edge (edge is an unused portion of the template) is on a flat uniform surface. However, in FIG. 7B, after the template is thinned from the anode etch and / or the wet etch, the ridges of the three-dimensional structure are not uniform planes with flat template edges, and these ridges are lower. The thickness of the template may then be increased by epitaxially depositing a similar material 304 on the template, which increases the template thickness shown by hC in FIG. 7C. As the starting template shown in FIG. 7A, a semiconductor material 304 of the same type and doping concentration is illustrated. It is also noted that the ridges of the three-dimensional structure have been restored to be on a uniform face with flat template edges. Thus, the template thickness and three-dimensional structure were recovered by the deposition of a layer of similar material on the template top surface (used to form the PS).

Importantly, the methods provided may be applied to a template or wafer having any three-dimensional surface topography, typically a three-dimensional surface topography including a cavity defined by ridges that form openings in the cavity on the surface of the template. It can be applied.

The thickening process can be performed several times during the life cycle of the template. This makes the template even more valuable, especially if the epitaxial deposition process on a given template can be done in a more cost effective manner than producing the starting template by the wafering process. For example, periodic thickening of the template when the thickness is reduced below a predetermined threshold or after a predetermined number of reuses is advantageous for the maintenance of the production line, thermal drive annealing, growth or deposition. , Printing or lithography processes, processes such as lamination, and other processes where smaller thickness ranges are advantageous for maintaining tight control.

As a variant, it is possible to start with a lightly doped template and do more heavy doping only through the epitaxial deposition of the thickening layer through subsequent anodic oxidation cycles (shown in the figure as the top surface of the template). This makes it possible to use low cost starting templates because the price of semiconductor wafers is typically influenced by the amount of dopant. In addition, throughout the ingot, the doping level typically goes through a significant profile. Thus, the potential impact of this doping strain on the formation of TFSS over the formation of numerous TFSSs and the lifetime of the template can be reduced by depositing the conditioning material only on the template surface layer that is anodized to form the porous layer. Another embodiment includes depositing lower doping concentrations at the surface starting with higher doping concentrations for the template. Although potentially added to the template cost, this configuration allows for highly effective homogenization of the electric field across the wafer during the anodic oxidation process used to form the porous semiconductor layer or porous semiconductor layers.

Other advantages of depositing a relatively thick layer of epitaxial silicon on a template to thicken the template thickness include smoothing process imperfections that occur throughout the reuse cycles of the template.

First, as part of the removal of the thin film (TFSS) from the template, for example, a cutting process using a laser may be employed, but is not limited to this example. This cutting process may intentionally or accidentally create cuts and marks on the surface of the template due to variations. Such cuts may be smoothed by subsequent etching to provide a crystalline growth surface. Thick epitaxial deposition for thickening is used to planarize the new starting surface, thus preventing subsequent negative effects of the cutting marks.

Second, in general, due to contact forces from the handling, carrier or susceptor, or due to particulate contamination, the PS anodization layer may have incomplete areas / areas on the template. Then, during the baking process before epitaxial TFSS deposition, the top layer does not completely reflow in the affected areas. This can lead to zones on the template where the complete removal of the TFSS is no longer possible because part of the TFSS is fixed to the template. This phenomenon is particularly likely to occur in template edge regions. Since the TFSS generally does not have the correct doping to enable subsequent PS formation, the fixed region is surrounded by the silicon itself deposited on the fixed regions without surrounding regions obtaining optimal current density during anodization. It provides a retaining force that resists the removal of material, so it can increase in height and width.

By re-depositing the PS by depositing a thick epitaxial film of the correct doping concentration, these defective spots / areas can again be suitable for exfoliation. This process is illustrated in Figures 8A and 8B, where a template of three-dimensional structure is shown, but the same concept may be applied to approximately flat or randomly pre-textured templates. 8A shows template 310 and residual epi layer 312 after several TFSS fabrication and reuse cycles. The remaining epi layer 312 has an incorrect doping concentration for PS formation and becomes a permanent defect in the TFSS formation process since no porous semiconductor or porous silicon can be formed on this layer.

In FIG. 8B, epitaxially grown layer 314 was formed over the remaining epi layer 312 as well as the rest (top) of the template surface used to form the PS. The epitaxial growth layer 314 has the appropriate doping for forming porous semiconductor / silicon (PS), and allows the formation of PS over the entire template surface, thereby mitigating the defective residual epi layer 312. And enable effective and clean peeling of TFSS from the template.

After epitaxial deposition of the thickening layer, optionally, treatment may be followed for the bevel edge of the template to remove the thickening layer over the bevel edge. This further treatment is part of the epitaxial growth features and can reduce sharp facets at the edges, which can be detrimental to template strength, for example.

Such edge treatment may be performed in a number of ways, such as through edge tape bevel grinding / polishing, through a grinding / polishing wheel, through a laser edge bevel process, or through chemical etching close to the template edge. These same methods may be performed at the edge of the back side of the template to reduce the effect of backside deposition at any template edge, along with area grinding / polishing.

The cost of producing a single crystal or pseudo single crystal semiconductor wafer is the starting material cost, typically an ingot growth performed by Czochralski growth or casting, in the latter case potentially a single crystal seeded pseudo single crystal ingot, followed by cropping of the wafer. It is often controlled by processes associated with manufacturing steps such as cropping, squaring, slicing, bevel grinding, lapping, etching, polishing, and the like.

In order to use such a wafer as a template for the effective cost of repeated semiconductor material deposition and removal / peeling processes, it is necessary to keep the manufacturing costs of these templates at a minimum. Because lapping, grinding, and / or polishing presents a significant cost, it is desirable to avoid all of these steps together or replace these steps with cheaper steps.

Thin film or thin foil solar cell substrates may also be created using a starting substrate that accommodates slicing and optional cutting damage removal etch after bevel grinding. However, these thin film solar cell substrates carry the remaining template topography from the cutting mark even if the associated sub-surface damage is eliminated. Such residual template topography may or may not be desirable.

As part of the deposition process of thin film semiconductor solar cell substrates, high capacity low cost epitaxial reaction devices have been developed. These reactors allow for the deposition of smooth films by the planarization feature at low cost.

Thus, in order to reduce the manufacturing cost of relatively smooth wafers, the sliced wafers may be subjected to epitaxial layer deposition after the optional bevel treatment, at a dopant level that is close to or equal to the level of the starting wafer removal and cleaning. The process can be run to accommodate. 9A-9C show some of the main manufacturing steps of this process. 9A shows wafer 320 with subsurface damage 324 and slicing cut marks 322 generated by slicing the wafer from the ingot. FIG. 9B shows the wafer 320 where a subcutaneous damage 324 was removed by a cutting damage removal etch but not the slicing cutting mark 322. 9C shows template 320 after front / top epitaxial deposition and cutting damage removal etching of layer 326 having a similar doping as wafer 320. The planarization effect of epitaxial deposition of layer 326 provides a smooth surface topography 328 over the slicing cutting marks shown in FIGS. 9A and 9B and allows for further template processing. The wafer surface after such deposition can then be used to form and peel smooth thin film semiconductor solar cell substrates or to process the wafer surface to form textured patterns or three-dimensional surface features. Epitaxial layer deposition is shown as being done on the cross section of the wafer. However, for example, it may be considered to form porous semiconductor exfoliation layers on both sides of the template or wafer and then perform such deposition subsequent or simultaneously to both sides of the wafer so that solar cells can be obtained later on both sides of the template.

As an added benefit, in contrast to wafer wrapping, grinding, or polishing, which consumes all silicon and thins the wafer in the process, using a deposited film substantially thickens the wafer, thus making the wafer available for a large number of reuse cycles. Can be.

From the foregoing disclosure, one skilled in the art can derive other advantages, such as microelectromechanical structure (MEMS), and other advantages of depositing epitaxial layers of suitable thickness and doping type and level for forming templates for solar cell substrate production. have. The following description and the corresponding drawings, which are not limited to the foregoing immediately, are more directly related to the contents disclosed in the present application.

The following disclosure, in conjunction with the foregoing disclosure, is more directly related to the present application, in which a semiconductor wafer, such as a single crystal silicon wafer, is applied to a semiconductor thin film while the thin films are still attached to the template and thus supported by the template. It is to use as a reusable carrier called a "template" for the repeated production of a deposited semiconductor thin film (such as a single crystal silicon film) which is subsequently peeled off from the carriers after completion of a series of processing steps. The exfoliated semiconductor thin film can then be further processed into devices such as solar cells or other semiconductor devices. The disclosure also relates to processes that enable improved performance and yield of semiconductor thin films and solar cells fabricated using the same.

The present disclosure provides a novel structure, method that enables multiple reuse of carrier wafers, such as crystalline semiconductor wafers, in spite of process imperfections such as residues and dimension and quantity changes of carriers during multiple semiconductor thin film fabrication cycles. , And a device. In addition, such methods and apparatus reduce or avoid certain process or dimensional imperfections and variations.

The present disclosure also demonstrates a novel structure and method for avoiding the deposition of excess semiconductor film onto regions on the backside of a wafer where deposition is undesirable. Also disclosed is a method that enables the construction of optimized template form factors and edge shapes over the usable life of the templates described above. In addition, a method of facilitating new implementation planning concepts within a solar cell manufacturing plant that processes semiconductor thin films repeatedly deposited on reusable carrier wafers and repeatedly peeled from such wafers as a manufacturing base for solar cells, The structure and apparatus will be described. In this approach, at least some solar cell processing steps are performed on the semiconductor thin film while the semiconductor thin film is being supported on the carrier wafers and before the semiconductor thin film is reinforced with a reinforcement plate and peeled from the carrier wafer. The present disclosure also discloses the semiconductor thin film during subsequent processing to achieve effective passivation, to enable high quality passivation coating, and to prevent edge crack formation and propagation across the thin film, particularly over the active region of the solar cell. Methods for adequately protecting the edges of the? New methods are also proposed to provide low frontal yields to mitigate overall thermal costs.

Crystalline silicon is currently the dominant absorbing material for photovoltaic solar cells. Much of the manufacturing cost of today's solar cells comes from the manufacture of silicon wafers used to make solar cells. To this end, it is very attractive to use silicon thin films, in particular monocrystalline silicon thin films in the thickness range of several micrometers to several tens of micrometers, for the production of high efficiency solar cells.

It may be particularly advantageous to use crystalline silicon wafers, in particular single crystal silicon wafers, as carrier wafers in monocrystalline silicon thin film manufacturing processes. In one embodiment, a delamination sacrificial layer (or separation layer or cleavage layer) is formed on the surface of the carrier wafer and subsequently a thin crystalline layer (such as single crystal) or a layer system of silicon and / or other semiconductors is placed on the delamination sacrificial layer. It is deposited epitaxially. Optionally, solar cell manufacturing process steps may be performed on the thin crystalline layer while the thin crystalline layer is being supported by the carrier wafer on the carrier wafer. The thin crystalline layer can then be peeled off from the carrier wafer and, optionally, after strengthening with a subsequent carrier plate (which may be a permanent strengthening plate), if desired.

Prior to delamination, the thin film is supported during various processing steps, in particular after, for example, deposition, printing or growth of blanket or patterned isolation layers, patterning of layers, contact openings, deposition of contact material, and subsequently delamination from the carrier wafer. It may be advantageous to use a silicon carrier wafer (reusable template) to support a semiconductor thin film (such as a single crystal thin film on a single crystal carrier wafer) during processes required to form a solar cell, such as attaching a support structure. Here, additional processes are provided that allow for the on-template processes described above.

After exfoliation of the semiconductor thin film from the carrier, optionally, after exfoliation onto the support structure (which may be a permanent support structure such as a solar cell backplane), further processing may be required to complete the manufacture of the solar cell. These post peel processes include processes that can be performed on the peeled surface of the semiconductor thin film (optionally supported on a permanent support plate), such as surface texturing and passivation on the solar side of the solar cell, but herein It is not limited to those provided.

In general, the above-described structures, such as crystalline carrier wafers (such as single crystal silicon) (such as reusable templates) and appropriate stripping sacrificial layers (such as porous silicon), prevent deposition of the high quality single crystal materials required for high efficiency solar cells. Make it possible. Often, to economically perform this process, the carrier wafers (or host template) need to be reused many times so that the starting carrier wafer cost can be repaid over several reuses.

During the semiconductor thin film fabrication process, the carrier wafer is subjected to various fabrication processes such as reuse cleaning, optional etching, formation of delamination sacrificial layers or delamination sacrificial layers (such as porous silicon), and high temperature epitaxial semiconductor deposition. Optionally, the carrier wafer is then subjected to several process steps (e.g., followed by delamination of the thin film, where the delamination can occur after permanent reinforcement of a thin semiconductor layer using a low-cost reinforcement plate, such as a backplane). Back Junction Supports a semiconductor thin film (such as a single crystal silicon layer in a thickness range of less than 1 μm to up to about 100 μm, more preferably less than 50 μm) through most or all of the process steps for the backside of the back contact solar cell. You may. Thus, the disclosure provides an optimized and economical process that allows for repeated use of one carrier during manufacturing steps, such as the manufacturing steps described above.

The disclosure generally relates to the deposition of thin film or thin foil materials, and more particularly to the deposition of epitaxial single crystal or pseudo single crystal silicon films (epi films) for use in the manufacture of high efficiency solar cells. In operation, methods are disclosed that extend the reusable life and reduce the cost of repayment of substrates or templates used in the manufacturing process of silicon solar cells. Also disclosed are methods for providing a conversion of a low quality starting surface to an improved quality starting surface of a silicon wafer.

10A and 10B illustrate key fabrication steps for fabricating a high efficiency crystalline thin film solar cell in accordance with the disclosure, including a back contact / back junction solar cell using a thin single crystal silicon (or other semiconductor) substrate. Although two process flow embodiments are not limited to this example. These two example process flows are only disclosed for illustration as these steps may not necessarily be all necessary, or may be employed for various materials in a different order. Again, the disclosure is applicable to any number of variations of the processes and materials described above.

The starting template for each manufacturing and cycle may be of any shape or dimension, such as round, square, rectangular, pseudo-square, square with corner radius or various other corner truncations, regardless of new or adjusted template. Semiconductor wafers (such as crystalline silicon wafers). However, it may be practical to use common starting template shapes, and some processes are improved by or benefit from the appropriate bevel shape and dimensions and / or shape of the template itself.

During the formation of the release layer or release layers, step 1: porous silicon (or generally porous semiconductor) is used in the release layer or as part of the layer system (eg, porous silicon having at least two different porosities). Afterwards, it may be cost effective to perform deposition in a high productivity batch porous silicon reaction apparatus. Details of suitable methods and apparatus for forming porous silicon have already been disclosed above. For an anodization (or anode etch) reaction, in one embodiment, the electrolyte is sealed between the wafers in a multi-wafer arrangement by proper edge sealing of the templates. Proper edge sealing must be adequate to accommodate dimensional variations and small edge imperfections. As a result, at the edge of the wafer, the seal may surround over at least a small portion of the wafer (as shown in FIG. 12). On the "front" side or on the side being anodized, such sealing enveloping prevents local anodization near the edge of the template (although it can anodize both sides for a solar cell from both sides). can do. As a result, there is no or insufficient structure / thickness of the release layer formed close to the edge. Thus, after deposition of the thin film and subsequent delamination of the thin film from the template, the template surface area without a suitable delamination layer is such that semiconductor thin film deposition (such as epitaxial silicon deposition) is carried out to the wafer bevel vertex and possibly near the edge of the template. It may continue to the back side, and may include residues of the semiconductor thin film.

The method of removing these residues is to use wear methods such as precision grinding wheels or tape grinding / polishing processes (or combinations thereof) at the wafer bevel if the residues must be removed. Alternatively, a wet etch process may be employed that uses a local etch close to the edge of the template. Such wet etching processes employ, for example, light n-doped epi, as compared to heavy p-doped materials, such as materials from templates electrochemically etched to form a porous semiconductor release layer system by employing an appropriate chemical reaction. It can be improved to allow faster etching for light n-doped material from the tactile layer residue. For example, alkaline etchant such as KOH or other hydrides, and acid etchant may be applied for local wet etching near the edge.

Since scratching or groove formation must be limited to wafer bevels for the bevel grinding / polishing method, it may be important to limit the area of incomplete or lost exfoliation layer to wafer bevels only. The area grinding method can be quite difficult to avoid cutting silicon wafers in terms of equipment and abrasive grain size.

The disclosed solution includes templates with custom edge bevels, especially custom edge bevels larger than the bevels used in conventional semiconductor applications. In another embodiment, the edge bevel is larger in terms of being anodized to form porous semiconductors (such as porous silicon). Larger edge bevels are advantageous for addressing edge sealing issues during the exfoliation layer anodization process and subsequent formation of the residue of the epitaxial layer deposited on the bevel.

While templates may be large in diameter or other X or Y direction and subsequently scaled to slightly smaller dimensions, for templates with large size in the Z direction (template thickness), wear removal of wafer thickness may reduce the thickness loss of the template. This is more problematic because it can accelerate and reduce the reuse life of the template. In addition, wear removal of the wafer thickness is difficult to achieve without demonstrating momentum to the wafer, which tends to increase fracture.

The ultimate or total number of template reuse achievable is highly related to template thickness loss per reuse. Therefore, it is desirable to minimize template thickness loss per reuse cycle. Template thickness per reuse cycle is generally lost by anodization processes (porous silicon layer formation) as well as etching steps that enhance residual porous silicon, template silicon, and other imperfections on the surface. In addition, template thickness is lost for the template undergoing complete surface adjustment through means such as grinding, lapping or polishing, including electropolishing or chemical mechanical polishing.

New or new wafers should ideally be made with moderately large (eg 400> um) symmetrical or asymmetrical edge bevels. However, the template wafer loses thickness upon reuse, and is partially transferred onto a thin film layer (preferably a pseudo single crystal upper layer that functions as a seed for the epitaxial film) as an anodic oxide layer is subsequently peeled off as part of the adjustment process (diluted KOH Easily subsequently etch partially (weakly high porosity lower portion of the layer) with a suitable wet etchant, such as a system etchant, thus losing more thickness of the anodized face.

As the template wafer loses thickness asymmetrically during reuse, the bevel shape for the wafer may be optimally adjusted. For example, to maintain consistent bevel encroachment into the wafer (preferably about 1 mm or more), different bevel grinding wheels with different bevel angles (or different angular tape grind / polishing) may be applied during each use. The bevel can be redressed. For example, as the wafer becomes thinner, the bevel angle becomes more acute with respect to the wafer surface.

11A and 11B are cross-sectional views of templates in accordance with the disclosure, illustrating the concept of maintaining a long top bevel for templates that have been reused over time.

12 is a cross-sectional view of the template after a number of reuse cycles, showing a long top bevel for templates that are continuously reused during anodization or wet anode etching (typically in a HF / IPA mixture) to form a porous semiconductor layer or layer structure. It illustrates how to maintain a consistent edge seal of this template.

FIG. 13 is a cross-sectional view of the template of the anodization equipment, and due to the consistent edge sealing of the template during anodization using a flexible seal, the region of the fused deposited thin film may be removed using a bevel grinding mechanism. Illustrate how you can limit it to the bevel area on the template.

Maintaining a substantially uniform electric field for the anodic oxidation process used to form a porous exfoliation (and epitaxial seed) layer or layer structure for forming a semiconductor thin film solar substrate (such as a single crystal semiconductor such as a single crystal silicon thin film), It may be a specific challenge at the edge of the template. Therefore, reliable edge sealing during anodization is important because leakage at the template edge can cause non-uniform anodic oxidation. The disclosed flexible sealing solution provides reliable and repeatable anodic oxidation performance close to the template edge allowing for reliable and repeatable edge sealing performance for the template and thus reliable and repeatable edge residue removal performance.

Anodizing chemistry may be used that provides a uniform electric field close to the template edge and uniform anodization to provide anodizing liquid conductivity.

Common anodic oxidation chemicals may include mixtures of hydrofluoric acid (HF), water, and typically alcohols. For example, since HF acid does not dissociate completely, the conductivity of the fluid is usually limited. However, additives may be selected to increase the conductivity of the anodic oxidation liquid. By increasing the conductivity of the anodic oxidation liquid, field non-uniformity, including non-uniformity caused by roughness or other non- geometrical uniformity commonly found near the edge of the wafer where local disturbances of the electric field are caused by the flexible seal and the holding device The sex can be more easily homogenized. This is particularly applicable to batch anodic oxidation systems where the inter-wafer (inter-template) distance is often chosen small to increase the anodization batch size for economical purposes. In addition, by increasing the conductivity of the anodic oxidation liquid, it is possible to reduce the power dissipation and power requirements of the consistent anode etch tool. Suitable chemicals may include salts whose potential residues are not detrimental to the lifetime of the thin film, which is subsequently deposited on the release layer or layer structure. Other chemicals may include conductivity enhancing materials having a metal component that is known to be free of metal components or that do not form deep traps in crystalline and / or epitaxial semiconductor layers. For example, hydrochloric acid may include hydrochloric acid (HCl) because of the large portion of dissociation that leads to good conductivity even at medium concentrations and because of the propensity to keep the metal in solution rather than plating or depositing on the surface of the porous layer. A further advantage of adding conductivity enhancing additives or salts to the anode etch bath is to reduce liquid bath heating due to ohmic power loss in that bath. Heat reduction reduces power consumption per wafer and increases process repeatability and control due to reduced bath heating and temperature changes.

Another type of additive that may be beneficial for anodization uniformity is an additive that promotes the removal of gas bubbles from the wafer surface during anodization reaction, which may prevent the gas bubbles from remaining close to the surface. For example, hydrogen peroxide is a liquid oxidant that can react with the hydrogen bubbles formed during the anode etch process to reduce the hydrogen bubbles. By adding a small amount of hydrogen peroxide (H ₂ O ₂ ) to the anode etching bath (eg, a mixture of HF + IPA + H ₂ O), hydrogen gas bubbles can be effectively reduced and the porous silicon formation uniformity is better Can be done. However, the disclosed solution extends to any additive that can effectively react with hydrogen bubbles to reduce hydrogen bubbles without deleterious interaction with the anode etch process itself.

An advantage of the asymmetric bevel according to the disclosure is that the smaller radius at the backside of the bevel helps to suppress backside deposition of the thin film. Such backside deposition is typically not advantageous for subsequent vacuum chucking processes or any other process that requires or favors a flat wafer backside or is advantageous. Another solution to excessive backside deposition is to remove the excess film deposited close to the backside bevel, which can be performed using the same bevel grinding tool used to calibrate the bevel.

Also, in areas where flatness is compromised by the existing deposition residues, it is possible to limit excessive backside thin film deposition residues, typically by using grooved flat chucks in regions near the back edge of the template wafer. . The edge grooves of such a check can also be beneficial to prevent excessive stress of the template during chucking, thereby enabling a large number of reuse cycles per template.

Bevel grinding robustness and repeatability to the workpiece (template) can be improved by reducing the loss of any excessive diameter in X, Y, or any dimension during calibration of the edge. Excessive diameter or dimensional loss increases the difficulty of edge sealing during porous silicon anodization processes. To limit this loss, the templates may be presorted with thickness and / or XY dimensions and bevel grinding tools adjusted by following to ensure optimal performance of maintaining bevel and template wafer dimensions.

Rather than pre-align, it is also possible to make thickness measurements on-the-fly or at least on the path of the templates to the grinding process station.

In addition, by using a robust centering process, the template wafer is reliably centered around the beveling chuck or holder. This can be achieved optically or by means of an appropriate clamping station, for example by applying symmetrical / spring forces as known in the art.

Other embodiments include using a reference point for the grinding wheel (tool) for the chuck holding the substrate. The dimensioning of the template prior to the grinding process involves the use of this information for centering with in particular mechanical or optical reference from fewer than all sides of the template. A mechanical or non-mechanical stop or reference to the grinding wheel is applied to the chuck holding the substrate. Such mechanical and non-mechanical stops or references may be, but are not limited to, non-contact stops using optical means or air pressure as a sensed reference or directly for centering. Alternatively or additionally, the same trajectory of template wafers and / or tools to be ground each time for template wafers in a given sorting bin may be used.

By using pre-selection and according to the disclosure and by proper binning and batching of template wafers, the bevel grinding of the wafers can be processed in parallel, that is, the wafers can be batch bevel ground have. For parallel processing of bevel grinding, wafers are stacked (optionally, with spaced plates between them), aligned (optionally all at the same time) and then fixed (e.g., by vertical pressure) Bevel grinding can be performed simultaneously using more than one wheel. This can be accomplished at once on all sides of the wafer or by recharging / reorienting the template wafer stack or tool. In order to keep the X / Y dimensions of the template wafer closely, the grinding dimensions as described above are also applicable to parallel processing. Other modes of parallel processing may include the use of a parallel position that shares at least one or more of the control axes of the precision machine tool used in the abrasive machining operation. Such control axes may comprise a template holder table or pallet as well as a machining tool spindle holder.

In a parallel process, an embodiment may use a movable centering device that can reference each template to its own process station. Such a centering device can be mounted, for example, on a robotic device that can be moved per process station.

In another embodiment, the grinding process of the current templates and the centering process for the next set of templates use separate process stations and separate alignment station locations located on pallets that can be moved or swapped to occur in parallel.

14 and 15 are diagrams of two parallel bevel grinding embodiments according to the disclosure. 14 illustrates a vertical template lamination embodiment for parallel edge grinding, and FIG. 15 shows a side by side or at least separately maintained parallel edge grinding embodiment utilizing at least one of the axes of the machining equipment together for more than one template. Shows. Those skilled in the art may further derive additional parallel processing designs. In one embodiment, centering of the template on the processing chuck before processing is achieved while other templates are being processed.

The grinding machine may also be used to remove intrinsic residues of semiconductor thin films (such as thin silicon), particularly on top of template wafers near the edges. This process removes residues in areas where the porous semiconductor or silicon exfoliation layer structure is very thin or complete exfoliation but still has insufficient porosity for shear by a wear wheel that does not cause abrasion action on the template surface layer itself. Can be used to remove or reduce. For example, this can be done using a separate wheel from the edge grinding wheel or a separate part of the same wheel tool. It is also possible to implement similar parallel modes of operation for the edge grinding process.

FIG. 16A is a diagram of a device in which an abrasive or mechanical removal mechanism exerts a residue intermediate holding force that sufficiently removes the residue into the porous layer. FIG. FIG. 16B shows an enlarged view of the wear effect of the device of FIG. 16A. FIG. 16C shows an enlarged view of the wear effect of the device, such as shown in FIG. 16A, for a more powerful holding force of the residue. Abrasion or mechanical reduction of the residue height is advantageous for further processing by reducing the roughness at the wafer edge which can otherwise prevent proper sealing in the anodic oxidation bath.

17A and 17B show a device for removing residue having a strong holding force with respect to the front side residue as shown in FIG. 17A and with respect to the backside residue as shown in FIG. 17B. . Areas with strong retaining residues due to more imperfections of the deposited thin film that cannot be eliminated with the aforementioned "kiss grind" removal are subject to significant surface adjustments, such as area wrapping, grinding, polishing, or a combination thereof. need. In the same way, excess backside deposited thin film can be removed from the backside by a wear process.

The determination of the processing needs for the adjustment path may use optical or capacitive detection techniques to determine the degree of residue. Depending on the nature, amount, and location of the residue found on the template wafer, the wafers are classified into different control routes, such as light, intermediate, or heavy residues. The appropriate processes are then selected and employed to adjust only the areas affected by the complete template surface or excessive residue (such as edge and / or corner areas).

Template reuse etching and cleaning steps may also be performed in various tool configurations. Such etching and cleaning processes typically have several functions, such as organic contaminant removal, metal contaminant removal, particle residue removal, removal or cleaning of areas on the wafer that may be harmful to further reuse.

The limitations on these etching and cleaning processes are controlled by processing costs and excessive template thickness and X / Y dimension reduction during etching. The latter can adversely affect the amount of obtainable reuse cycles for the template.

If advantageous or necessary, the reuse etch and cleaning steps may be performed only on the cross section of the template. For example, a relatively deep silicon etch is performed on the cross section of the template, for example on a face using silicon etch to smooth out the effects of laser or mechanical cutting into the template.

Chemicals for template reuse cleaning can be optional between metal, organic removal and silicon removal (thus minimizing silicon removal while removing contaminants). Thus, metal complexes can be added to the cleaning and etching chemicals to free all metal cations from the wafer surface to the chemical treatment bath. For example, Cu, Fe, Zn are often metal contaminants from silicon ingots, template wafering processes, and template fabrication before reuse. Metal contamination can occur due to the exchange of surface atoms with intrinsic metal impurities present in the reuse wash chemical reagent.

Silicon removal typically targets the thickness of the template wafer and consequently reduces its thickness. For any silicon controlled etch (single or double sided), most of the silicon can be removed before edge bevel grinding. By doing so, the remaining thin film on the top of the bevel functions to prevent excessive X / Y dimensional loss of the template wafer.

After bevel grinding, a potential additional silicon etch may be used for the wash etch, with significantly less removal. Precleaning is important for the reusability of wafer templates due to the inherent organic and metal contaminants that are physically absorbed on the surface during the bevel grinding process. The addition of complexing agents to the preliminary washing bath and even to the rinsing bath is advantageous for the further sequestration of any metals that can be harmful trace metal contaminants in the process.

After (or during) silicon removal, metal contaminants may be removed before the wafers are subjected to anodization again for another reuse cycle. For example, in this process, routine monitoring using gas phase decomposition (VPD) analysis techniques can be performed to verify surface cleanliness. A total of 31 basic impurities are analyzed and the surface metal concentration is reduced by ¹ × ^{10 9} atoms / cm ² using an inductively coupled plasma mass spectrometer to improve range and surface detection limits. Very small trace metal concentrations on the wafer surface may be due to the combination using semiconductor grades for analyte reaction chemicals and complexing agents. The solution temperature and concentration of the washing chemical can also be important factors.

At any instant of the life cycle of the template wafer, it may be necessary to change the side on which the semiconductor thin film (such as an active solar cell layer) is deposited. To this end, it may or may not be recommended, may or may not be necessary to correct or regrind the bevel and treat the surface with a wear process before the template wafer is subjected to reuse cycling again. Criteria for changing the active surface of the template include excessive traces, scratching, or incompleteness of the laser cut or fitting, or which favors one surface over another.

In addition, both sides of the template may be used simultaneously to double the productivity of the template in terms of semiconductor thin film formation and to form the peeling sacrificial layers of the semiconductor thin films and the porous semiconductor for acquisition in the entire template region on both sides.

Often, in typical current solar cell manufacturing, due to the cost of the marking process, individual solar cells are not labeled with identification numbers or alignment marks, which makes the traceability of wafers across the manufacturing line very difficult.

However, in the reuse cycle, each template wafer can be displayed because the display cost is amortized over many reuses of one template. This indication allows for traceability. The template can be displayed via global or local software (eg per production line or per equipment or equipment type) for the number of reuse cycles. As long as these templates undergo on-template processing, information and indications may also be associated with solar cells made from the templates. Reuse counting may also be used for template binning for subsequent processing steps since the reuse count may be related to template wafer dimensions (such as thickness). Template thickness and dimensional information is valuable for processes such as bevel or area grinding or lapping, anodization, and lamination.

If necessary, the template mark may be reattached if subsequent reuse processes do not allow the identification marks to be fully recognizable. Thus, a single-sided silicon removal etch as described herein where silicon is primarily removed from the top surface of the template wafer may support the retention of such template markings.

In particular, template markings on the back side can be used for identification for alignment or orientation. Thus, other types of markings for template wafers, such as fiducials, may be used in processes that require alignment (such as laser processing, screen printing, etc.). For example, if templates are marked with reference points on the back side, tool throughput can be improved by placing an alignment function such as a camera through the back of the wafer holder or chuck. It is also feasible and contributes to rapid orientation when the alignment targets are not immediately visible or embedded below the non-transparent layers (especially for any printing tool, lithography tool or laser tool).

As disclosed, templates can be sorted and binned for processing depending on template thickness and deposited residue. The location in the flow where alignment and binning is performed may depend on the use and extent of the wafer identification mark. In a simple embodiment, wafers are sorted and binned into batches according to dimensions (X / Y and / or thickness) prior to bevel grinding, which allows determination of the appropriate grinding wheel tool to be used for the entire batch.

Edge engineering and edge protection of the thin film layers during processing after removal from the template wafer can also improve and increase the number of reuse cycles per carrier wafer. When removing a semiconductor thin film (such as a single crystal silicon thin film from a single crystal silicon template through separation in a porous silicon release layer) from a template carrier wafer, (emitter junction, base window, back passivation, emitter and base contacts, and After completion of the major on-template processing steps for the exposed semiconductor thin film surface and prior to separation from the template wafer, such as completion of all major process steps for forming on-cell metallization for back junction / back contact solar cells. It may be advantageous or necessary to attach a support layer or layer structure (backplane) to the.

Prior to lamination or prior to delamination, a laser or other mechanical wear tool may be used to outline the peripheral area on the semiconductor thin film that is larger than the final active solar cell area but close to the area to be delaminated by performing a partial laser or wear cut. This cleavage creates weak areas and also creates desirable breakdown spots within the thin film but outside of the active area during or prior to the exfoliation process. In order to reduce the impact of cutting into the lower template and thus leave traces of laser cutting on the template to be reduced, such as shallow heating or cooling throughout the backplane reinforced film to template to be peeled off, etc. A combination of extended mechanical or thermal forces can be used, or the laser cutting depth can be adjusted to the thickness of the deposited layer, thus due to the known nonuniformity of the deposited layer around the boundary of the area to be stripped off. Cutting depth can also be adjusted during laser scribing and thus minimizing the effect of accidental cutting into a reusable template, or employing the introduction of thermal laser separation, i.e. a process introduced for semiconductor dicing, again In other words, pulsed or CW IR or CO ₂ levels followed by water spray or local coolant such as helium. Local heating of the area to be cleaved may be used using a laser such as Ezezer. Cleaving techniques such as those disclosed for silicon wafer dicing of U.S. Patent No. 8,110,777 to Zuehlke can be used.

In the present application, such a cleaving technique is applied to cleave through a silicon or other semiconductor film on a wafer where the silicon or semiconductor film is separated from a starting growth wafer called a template by a release layer or layer system such as porous silicon. It is not limited to the example of silicon. The present disclosure provides the cleaving technique with the effect of stopping the next cleave in the release layer, which, due to the mechanically weak structural properties of the cleave, will serve to terminate the propagation of the cleave into the underlying semiconductor template. Can be. Termination is also assisted by a release layer that functions as a thermally conductive barrier. 18 shows the thermal induced cleaves stationary on the release layer.

After exfoliation of the backplane reinforced semiconductor thin film (such as backplane laminated / reinforced monocrystalline thin film silicon solar cell), the final active region of the semiconductor thin film is subjected to laser cutting to prevent crack propagation from the edge through the active region of the device. Other low damage effects May be separated by cleavage. This is achieved by using a pulsed picosecond or pulsed nanosecond laser beam (for example, by forming a twirl through the entire thickness of the semiconductor thin film and stopping it on the backplane support using a laser), for example, the main active area of the cell. This can be done by creating a narrow semiconductor frame around it. Laser trenching is a laser ablation process (preferably with minimal edge damage) that performs frame boundary ablation on the exfoliated side of the backplane laminated semiconductor thin film (which eventually becomes the solar side of the back contact / back junction solar cell). It does not need to be a pulsed picosecond or nanosecond laser ablation process for zones without heating influence). The laser formed (or mechanically formed) trench boundary surrounds the main active area of the solar cell and separates the main solar cell area from the surrounding narrow width semiconductor thin film. The laser trenching process described above for the solar side of the cell is followed immediately after peeling the backplane laminated semiconductor thin film from the template (before or after the final front side passivation and antireflective coating layer) or after completion of the texture etching process. Can be performed. Simultaneously with the aforementioned inner boundary cut or after further processes such as texturing and cleaning, the edges of the large backplane reinforced structure can be trimmed, and the first out by cutting through some or all of the backplane and potentially through the thin film. Define the line dimensions.

This approach results in a slightly larger backplane laminated structure (such as a back contact / back junction solar cell) with a narrow passive semiconductor thin film frame surrounding the main active semiconductor region. For example, a representative structure for a back contact / back junction backplane laminated thin film solar cell is a square 156 mm x 156 mm active thin film solar cell (including, for example, a thin single crystal silicon solar cell having a silicon thickness of less than 50 μm). And an active region, which is surrounded by a square peripheral trench that penetrates some or the entire depth of the semiconductor thin film and the width of the trench in the range of several micrometers to more than 100 micrometers (thus the trench depth Thin film plus the total thickness of the backplane, in any case significantly thinner or equal to the thickness of the semiconductor thin film supported by the backplane). The width of the thin passive semiconductor frame surrounding the laser forming trench may be in the range of several tens of micrometers to several hundred micrometers. The peripheral frame protects the inner active cell area by preventing the propagation of microcracks from the edge to the main cell area, thereby allowing for more robust handling, processing, and packaging of these cells.

Such cutting may be performed using suitable cutting tools, such as, but not limited to, such tool examples: a) one laser or several lasers to best handle the different materials / thin film solar substrate compound of the backplane. b) a suitable stamping die or dies, c) one or more shear cutting devices, d) a dicing saw capable of dicing through synthetic materials, e) any combination of the aforementioned materials. Long lasting cutting surfaces of mechanical methods for such synthetic materials are silicon carbide and diamond coating tools.

This first outline dimension is intended to handle thin films reinforced through further backplane processing, such as various post-processing steps and metallization related steps, including texturing, cleaning, passivation and antireflective coating of silicon nitride or the like. Can be chosen to be slightly larger than the final solar cell product.

Towards the end of the battery manufacturing process (eg, prior to testing and sorting), optionally, the battery may be subjected to its own final cut before being assembled using the aforementioned first outer cut before being assembled into a multicell photovoltaic module. It can be trimmed back to size (preferably, leaving a narrow, thin silicon frame around the main active cell area, or alternatively removing the frame).

The enlargement supports the edges of the thin film that are brittle during handling, thus separating the edges from the active area. It also functions as an area for holding the cell for passivation or other film deposition, thereby avoiding optically disturbed nonuniformities in antireflective layer thickness. In addition, this allows the deposition of the passivation layer on and around the edges of the thin film, thus allowing good sidewall passivation and low recombination rates in the surface area and edges.

Note that the order of the cuts and the need for each cut can be determined by the holding force, the internal stress of the reinforced thin film layer structure and the overall process flow. The present disclosure is directed to implementing these various arbitrary processes for optimal performance and cost.

19 is a process flow diagram illustrating one embodiment of a structure for solar cell semiconductor thin film edge trimming. Those skilled in the art may consider additional process flows from this concept, including flows that omit some cuts or trimmings or change the order of the cut steps, but are not limited to these flow examples.

Hot baking and epitaxial deposition methods are also provided for increased template life and large area delamination. Highly efficient solar cell absorbing layers (such as thin film solar substrates) can be fabricated by applying a high temperature during reflow of the porous release layers and prior to epitaxial layer deposition, in particular template wafer temperatures above 1020 ° C. and between 1020 ° C. and 1250 ° C. Form. This, together with the use of high temperature atmospheric epitaxial deposition using trichlorosilane as the silane containing gas with hydrogen carrier and reducing gas, can significantly improve cell fabrication and template efficiency. In addition, epitaxial deposition may function in a template wafer temperature range of 1020 ° C to 1250 ° C. Along with the well-controlled anodic oxidation process and equipment for the formation of porous layer systems, this method can be employed for high productivity formation of highly uniform, high quality epitaxial silicon layers with long lifetime, low cost and high deposition rate. have. In addition, the disclosed method enables the peeling of cell substrates of a large area (area of at least 100 mm x 100 mm), where the large area is considered to be about 100 cm ² or more in size.

This method solves problems using known methods for the combination of porous silicon epitaxial growth and subsequent delamination at low temperature, where large area delamination is largely due to insufficient thermal expense to seal the porous layer. It may not be performed using a combination of porous silicon and high temperature silicon epitaxy that can be reliably and efficiently used in production. For throughput reasons, it may be advantageous to bake the porous silicon release layer at a temperature higher than the temperature employed for deposition, thereby accelerating release layer surface reconstruction to form an epitaxial seed layer. A quick start ramp heating batch epitaxial reaction device may be suitable for this process flow.

Large area high quality peelable layers can also be obtained on lower surface quality substrates (reusable templates) with similar process conditions, thus eliminating the need for mirror polishing start substrates, thus reducing the cost of repayment of reusable templates. Can be reduced. Examples of surfaces are those obtained from a lapping-etching sequence or even from a surface that has been crushed in a subsequent ablation damage removal etch sequence. Starting and conditioning surfaces can be obtained using an acidic silicon etching chemical, such as a mixture of nitric acid and hydrofluoric acid, with an alkaline or optional additive such as acetic acid or phosphoric acid (such as KOH and other hydrides). . This acidic etching can be followed by a relatively mild alkaline etch surface cleaning step. Acid etched surfaces do not provide a clean crystalline orientation, while alkaline etched surfaces provide this orientation. Thus, epitaxial growth characteristics for both sides are different.

Also provided herein are susceptors that can withstand high temperature deposition. There is only a limited selection of materials that can be used as susceptors that can withstand the high temperatures required for optimal deposition. For example, such materials include, but are not limited to, silicon carbide coated graphite and monolithic silicon carbide.

However, due to the emergence of many polycrystalline silicon ingots, in part due to the possibility of manufacturing large area susceptors from silicon, cast silicon may be used instead of susceptors. These cast silicon susceptors can sustain many depositions before flaking of the deposited films becomes a problem. Another advantage of using molded silicone susceptors is the final reuse of the material and direct / simplified wet or dry cleaning by using it as a feedstock for recasting. Regardless of the susceptor material selection, the use of HCl (or chlorine gas) or as ex situ (HCl or chlorine gas) in a low cost reaction device focused on susceptor etching using only HCl, chlorine, or other suitable gas. Dry cleaning can be achieved in situ.

Also provided herein is a thin film solar cell having a front field and an optional low thermal expense annealing. Solar cells may benefit from frontal fields with improved frontal passivation and reduced frontal recombination rates. If selected correctly, this front field helps to improve the short circuit current and the open circuit voltage of the device. As the battery becomes thinner, the sensitivity to frontal quality tends to increase.

The present disclosure also provides an in-situ front field with higher back doping. Using a thin cell that is stripped after the active absorbent layer is deposited on a high temperature capable carrier, it may have a frontal field formed as part of the absorber layer deposition, for example by epitaxial growth. This frontal field may be dimensioned after subsequent processing such as peeling and texturing, so that the most frontal portion (sun face) of the active absorbing layer still maintains a higher doping than the doping of the next layer which is considerably close to the emitter. It may also be advantageous to have a higher back doped region that can function to reduce depletion region widths around a contact located close to the back surface.

For high volume CVD or epitaxial CVD reaction apparatus, to support high gas utilization, depleting precursor silicon-containing gases such as trichlorosilane, dichlorosilane, monochlorosilina, silicon tetrachloride, silane, or disilane May be advantageous. Since this effect is typically associated with a reduced deposition rate from a gas source, it may be advantageous to divert the gas to reverse the flow direction of the gas in the process and thus compensate for the deposition rate reduction. As a result, a somewhat uniform layer thickness is obtained across the various wafers in each susceptor. If the cell design architecture requires regions with different doping levels as described above for different doping or front sides, the gas direction can be switched as many times as necessary.

One embodiment of such a transition in a three domain architecture may be described, for example, as follows. That is, the deposition region 1 flows in the direction A, switches, and the deposition region 1 and the deposition region 2 flow in the opposite direction of A, switches, and the deposition region 2 and the deposition region 3 flows in the A direction, switches, and the deposition region 3 flows in the opposite direction of A.

It also provides options for engineering the ex situ front field. For reinforced thin cells, the reinforcement material, along with potentially other materials such as existing metal lines or adhesives, can significantly reduce the thermal costs available for the front field process. The following disclosed embodiments avoid these limitations due to thermal expense.

In one embodiment, the additional dopant, which may be made of a-Si, SiN, SiO _x , SiO _x N _y , or a combination thereof, is preferably deposited in the passivation layer deposition process by adding a dopant containing gas in the deposition step. do. The dopant containing gases can be, for example, PH ₃ or PF ₅ , AsH ₃ or AsF _{5 for the} n-type front field and B ₂ H ₆ , BF ₃ or BCl _{3 for the} p-type front field. have. In another embodiment, additional dopants may be implanted before or after attachment of the passivation layer.

It also provides options for annealing the ex situ front field. In each embodiment for directing the desired dopant, there are several embodiments for activating the dopant, the first being laser annealing, preferably using a wavelength suitable for maintaining most of the heat close to the surface. . Examples may include, but are not limited to, frequency double or triple Nd-YAG lasers, or lasers having wavelengths generally in the green to UV range.

Alternatively, a full surface exposure may be performed with short wavelengths of light to facilitate free carrier absorption and to promote absorption close to the surface of the material even for long wavelength light sources.

The laser should not melt the surface, especially if a pyramidal texture is formed at some point prior to annealing. If the laser melts the surface, it should only be at the top of the surface to avoid adversely affecting the light trapping quality of the textured surface.

Microwave cavities may also be used to activate dopants at reduced temperatures. In this embodiment, the wafers are preferably placed in a suitable batch microwave cavity, and annealing is subsequently performed at the highest temperature at which the reinforced structure safely withstands.

Those skilled in the art will recognize that the disclosed embodiments relate to various fields in addition to the specific examples described above.

The foregoing description of the exemplary embodiments is provided to enable any person skilled in the art to make or practice the claimed subject matter. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without using innovative capabilities. Thus, the claimed subject matter is not intended to be limited to the embodiments illustrated herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

It is intended that all such additional systems, methods, features, and advantages be included herein within the scope of the claims.

Claims (31)

As a method of manufacturing a thin film crystalline semiconductor substrate,
Providing a reusable doped crystalline semiconductor template,
Forming a porous semiconductor sacrificial seed and an exfoliation layer in front of the reusable doped crystalline semiconductor template;
Epitaxially depositing a thin film semiconductor substrate conforming to the sacrificial seed and release layer;
Exfoliating the thin film semiconductor substrate from the reusable semiconductor template by separation in the porous semiconductor sacrificial seed and exfoliation layer;
Grinding the bevel of the reusable semiconductor substrate to remove residues of the exfoliated epitaxially deposited thin film semiconductor substrate. The method of claim 1, wherein the grinding step is performed after each reuse of the reusable doped crystalline semiconductor template. The method of claim 1, wherein the grinding step is performed only once after a plurality of reuse cycles of the reusable doped crystalline semiconductor template. The method of claim 1, wherein the reusable doped crystalline semiconductor template has an area in the range of 100 mm x 100 mm to about 300 mm x 300 mm. The method of claim 1, wherein the reusable doped crystalline semiconductor template and the epitaxially deposited thin film semiconductor substrate comprise the same semiconductor material. The method of claim 1, wherein the reusable doped crystalline semiconductor template and the epitaxially deposited thin film semiconductor substrate comprise different semiconductor materials. The method of claim 1, wherein one or more additional device processing steps are performed after the epitaxial deposition of the thin film semiconductor substrate and before the exfoliation process step. The method of claim 1, wherein one or more additional device processing steps are performed after the epitaxial deposition of the thin film semiconductor substrate and before the exfoliation process step. The method of claim 1, wherein epitaxially depositing the thick film layer of semiconductor material comprises only one time after epitaxially depositing the thin film semiconductor substrate a plurality of times and peeling the thin film semiconductor substrate in subsequent process cycles. Carried out, a method for producing a thin film crystalline semiconductor substrate. The method of manufacturing a thin film crystalline semiconductor substrate according to claim 1, wherein the thin film crystalline semiconductor substrate is used for manufacturing a solar cell. The manufacturing of a thin film crystalline semiconductor substrate according to claim 1, wherein a laser treatment is used before the step of peeling the thin film semiconductor substrate from the reusable semiconductor template to cut through the semiconductor substrate to form a peripheral shape of the semiconductor substrate. Way. The method of claim 1, wherein the crystalline semiconductor comprises crystalline silicon. The method of manufacturing a thin film crystalline semiconductor substrate according to claim 12, wherein the crystalline silicon comprises single crystal silicon. The method of claim 1, wherein the crystalline semiconductor comprises crystalline gallium arsenide. The method of claim 1, wherein the reusable doped crystalline semiconductor template has a custom edge bevel. The method of claim 1, wherein the reusable doped crystalline semiconductor template has an asymmetric bevel. The method of claim 1, wherein bevel grinding is performed on the plurality of reusable templates using a parallel bevel grinding process. The method of claim 1, wherein wear surface treatment, such as grinding, lapping, polishing, or chemical etching, including local chemical etching, is applied to the reusable template in addition to bevel grinding. The epitaxially deposited thin film semiconductor substrate of claim 1, wherein the epitaxially deposited thin film semiconductor substrate is adapted to contain a totally variable dopant concentration by using dopant mixing control for gas conversion and deposition gas, the dopant concentration being front field, back field, or A method of manufacturing a thin film crystalline semiconductor substrate, which is used to form beneficial layers such as regions having a suitable low base resistance. The method of claim 1, wherein the reusable templates are represented by identifiers used to track template reuse cycles and processing information. The method of manufacturing a thin film crystalline semiconductor substrate according to claim 1, wherein the substrate exfoliated after the epitaxial deposition is formed using a laser treatment. The fabrication of a thin film crystalline semiconductor substrate according to claim 21, wherein the laser treatment further comprises a laser ablation cutting process that at least partially cuts the layer to be peeled to weaken the bond to the outer region of the deposited layer. Way. The method of claim 22, wherein the partial cutting is subsequently extended to the designated porous semiconductor separation layer by mechanical means such as diamond scribing, water jet pressure, or a combination thereof. . The method of claim 21, wherein the laser treatment is systematically controlled during the laser process itself to accommodate thickness non-uniformity of the deposited layer. 22. The method of claim 21, wherein the laser treatment generates local laser induction heating immediately outside an edge of the deposited substrate layer to be exfoliated followed by a front cleave to form an inner region of the deposited layer of the deposited layer. A method of manufacturing a thin film crystalline semiconductor substrate, comprising a thermal laser separation step comprising local cooling to separate from the outer region and remain on the template during the main stripping process. The method of manufacturing a thin film crystalline semiconductor substrate according to claim 25, wherein the front cleave is stopped at the porous semiconductor exfoliation layer. 2. The method of claim 1, further comprising doping the epitaxially deposited thin film semiconductor substrate prior to exfoliation by applying a dopant source and then applying a low effective thermal expense annealing process to form an ex-situ frontal field. And manufacturing method of thin film crystalline semiconductor substrate. 28. The method of claim 27, wherein the dopant source is applied by a deposited film. 28. The method of claim 27, wherein the dopant is applied by ion implantation. 28. The method of claim 27, wherein the annealing process comprises laser treatment. 29. The method of claim 27, wherein the annealing process comprises microwave annealing.

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