KR101384872B1 - Method for reconstructing a semiconductor template - Google Patents

Abstract

The present invention as described above is generally epitaxial monocrystalline or similar-monocrystalline for use in the deposition of thin film or thin foil materials, more particularly in the manufacture of high efficiency solar cells. It relates to the deposition of quasi-monocrystalline silicon films (epi films). In operation, the present invention is directed to reducing the amortized cost and extending the reusable life of substrates or templates used in the above manufacturing process of silicon solar cells. In addition, the method shows that a low quality starting surface of a silicon wafer is provided for conversion to an improved quality starting surface.

Description

Method for reconstructing semiconductor template {METHOD FOR RECONSTRUCTING A SEMICONDUCTOR TEMPLATE}

Cross-reference to related application

This application claims priority to US Patent Provisional Application No. 61 / 429,033, filed December 31, 2010, which is hereby incorporated by reference in its entirety.

This application is also published as US Pub. No. 2008/0289684, filed October 6, 2007, both of which are incorporated herein by reference in their entirety. Continuation-in-part and in US Patent Application Series No. filed Aug. 13, 2011. Partial application for 13 / 209,390.

FIELD OF THE INVENTION The present invention relates generally to the field of solar photovoltaics, and more particularly to the field of repetitive fabrication of thin film solar substrates from semiconductor templates.

Crystalline silicon (including multi- and mono-crystalline silicon) is the most dominant absorber material for commercial photovoltaic applications. These relatively high efficiencies have been associated with mass-produced crystalline silicon solar cells, combined with abundant materials, and bring together appeals for continuous use and improvement. However, the relatively high cost of crystalline silicon materials by themselves limits the widespread use of these solar modules. Currently, "wafering" or silicon crystallization and wafer cutting costs range from about 40% to 60% of the final cell module manufacturing cost. If a more direct way to manufacture wafers is possible, great progress can be made in lowering the price of solar cells.

There are several ways to grow monocrystalline or quasi-monocrystalline semiconductors, such as silicon, and to release or move the grown wafers. Regardless of the above method, low cost epitaxial silicon, accompanied by a low cost method of forming a high-volume, production-worthy, release (sacrificial lift-off separation) layer Deposition processes are a prerequisite for the widespread use of silicon solar cells.

Yet another prerequisite is to repeatedly perform the sequence of emitting layer formation, thin film deposition, on-template processing, thin film layer release, recovery / reconditioning of the template, The usefulness of reusable templates.

The microelectronics industry increases the number of dies (or chips) per wafer, changes the wafer size, and produces chip functionality (or chips) with each successive new product. By enhancing the integration density, economies of scale are achieved through obtaining better yields. In the solar industry, economy has been achieved through the industrialization of solar cell and module manufacturing processes with low cost and high productivity devices. An additional economic factor is the reduction of materials used per watt output of the solar cell, through cost savings in raw materials (replacement with cheaper materials and elimination of the consumption of costly materials). Is achieved).

In order to achieve the necessary economic factors for the solar photovoltaics industry, process cost modeling has been studied to optimize and verify device performance. Several categories of costs form a total cost picture: Fixed Cost (FC), Recurring Cost (RC), and Yield Cost (YC). FC consists of items such as equipment purchase price, installation cost, and robotics or automation cost. RC consists of electricity, gas, chemicals, operator salaries and maintenance technician support. YC may be interpreted as the overall cost of component loss during production.

In order to achieve a cost reduction of Cost of Ownership (CoO) numbers required by the solar sector, all aspects of the cost situation must be optimized. The properties of the low cost process are (in order of preference) as follows: 1) high productivity, 2) high yield, 3) low RC, and 4) low FC.

Planning high productivity and economical methods and process equipment requires reflecting this need in the construction of the device and understanding the process equipment properly. High yield requires a robust process and reliable equipment and as equipment productivity increases, so too does yield cost. Low RC is a prerequisite for the overall low CoO. RC may be, for example, the impact of plant site selection based on the cost of local power or the effectiveness of the bulk chemical, but importantly, the effect is compromised by device productivity. site selection based on, for example, cost of local power or availability of bulk chemicals.FC, although important, is diluted by equipment productivity).

Thus, high productivity, reliable, efficient manufacturing process flows and apparatus are prerequisites for low cost solar cells.

summary

Thus, a need has arisen for the high productivity of thin film deposition methods and systems. In accordance with the subject matter presented above, a method for reconstruction of a reusable semiconductor template is described which provides a significant cost reduction in the production of thin film semiconductor substrates (TFSSs).

The above-mentioned topics are directed to the deposition of thin or thin foil materials in general for use in the manufacture of high efficiency solar cells, but more particularly epitaxial monocrystalline or for use in the manufacture of high efficiency solar cells. It relates to the deposition of quasi-monocrystalline silicon films (epi films). In operation, the method is shown to reduce the amortized cost of the substrate or template used in the manufacturing process of the silicon solar cell, and to extend the reusable life. In addition, the method shows that a low quality starting surface of the silicon wafer is provided for conversion to an improved quality starting surface.

These and other advantages as well as additional novel features of the presented subject matter will become apparent from the description provided herein. This summary is not intended to be a comprehensive description of the subject matter, but rather to provide a brief overview of some of the functionality of the subject. Other systems, methods, features and advantages provided herein will be apparent to those skilled in the art upon review of the following figures and detailed description. All such additional systems, methods, features and advantages are intended to be included within this description within the scope of the claims.

The features, properties and advantages of the indicated subject matter will be apparent from the above detailed description, which is set forth below when taken in conjunction with the drawings, wherein reference numerals represent like features.
1A-1C show one embodiment of the formation of surface features on a reusable semiconductor template;
2A shows a patterned semiconductor template, a porous semiconductor multilayer, and a TFSS;
FIG. 2B shows electron micrographs of a sacrificial layer and flat template with two different porosities;
3A shows a hexagonal patterned semiconductor template, a porous semiconductor multilayer, and a TFSS;
FIG. 3B is a photograph of the emitted hexagonal TFSS of FIG. 3A ;
4 shows an electron micrograph of the interface between the template and the TFSS;
5 shows the TFSS ready to be released from the template;
6A shows two templates with different amounts of TFSS overdeposition;
6B shows the TESS to be released from the template;
6C shows TFSS with overdeposition to be removed from the template;
6D shows the use of a grinding tape to remove residual TFSS material from the template;
6E illustrates the use of an edge grinder to remove residual TFSS material from the template;
FIG. 6F illustrates the use of lasers with various varying angles of incidence to remove residual TFSS material from the template;
6G shows removal of excess front-side TFSS material by grinding;
7A-C show the main processing steps of a three-dimensionally structured template, as reconstructed according to the subject matter presented above.
8a to b show the main processing steps of a three-dimensionally structured template, as reconstructed to mitigate a defective region; And
9A-C show key fabrication steps of reconditioning of a wafer in accordance with the subject matter presented above.

Although the subject matter has been described in connection with specific embodiments, those skilled in the art may apply the principles described herein to embodiments and / or other areas without undue experimentation.

In operation, and in particular in the field of photovoltaics, the indicated subject matter is low cost fabrication of thin film substrates that can be used in solar cells manufactured using templates that can be used repeatedly in the manufacture of thin film substrates. Enable). The field of this content is directed to processing the template used to produce thin film substrates and to treating the template used to produce thin film substrates, with the goal of retrieving the template to allow for an extended number of re-uses. It includes several apparatus and methods for generating the same.

Processes for producing thin or thin foil epitaxial solar cells include the use of suitable crystalline semiconductor material wafers or single crystal silicon as reusable templates. This content then includes process flow diagrams, methods, apparatuses, and variations thereof that allow for such repeated use of the plates used in the manufacture of thin film layers made of solar cells.

The subject matter of this disclosure may include starting crystalline semiconductor wafers (called templates) with correct resistivity, such that anodization forms porous semiconductor material on one or both sides. The semiconductor used may comprise crystalline silicon, in particular monocrystalline silicon. The template outline may be round (with or without notches or flats), square, or similar pseudo-square with rounded, cornerless, Or in any suitable form, including slightly chamfered corners; The template may be planar, substantially planar, or have a three-dimensional structure. The porous semiconductor material may be composed of several layers with discrete or graded porosity. At least one section of the porous semiconductor layer system serves as a designated weakened layer that allows separation of the TFSS from the template.

This includes the use of reusable templates for repeatedly producing thin crystalline solar cell substrates from the template while the solar cell substrate may be made on one side of the template or on both sides of the template. And, although in this context the figure specifically addresses the single sided processing, not all embodiments of the present disclosure, as well as the single sided substrate process, for producing a solar cell substrate, It can be envisaged that both sides of the substrate can be used to remain essentially in the case of double side substrate processing.

With respect to the starting wafer, several structural architecture options are described below; However, the wafer and the resulting template may be of any three-dimensional structure or of any form, planar, or textured. In the simplest embodiment, the template may be essentially flat, ie the surface is for example saw damage removed, lapped or ground, etched, It may be of any selected surface quality, as indicated by grinding, or even mirror polished. In another embodiment, the wafer may be textured prior to formation of the porous semiconductor layer system shown above, for example using alkaline random texturing. Then, by this means, the textured surface is moved directly onto the thin film solar cell substrate. As a third alternative, the template may be a three-dimensional structure created using a process such as patterned wet or dry etching. Such templates with three-dimensional patterns may be achieved through the use of patterning techniques such as but not exclusively, photolithography and wet or dry etching.

Representative processes are described in FIGS. 1A-C for the formation of three-dimensional templates. In FIG. 1A , a starting wafer 100 is provided. For the purpose of forming a three-dimensional structure, a hard mask is generally a material, for example, but not exclusively, thermal oxide or deposited silicon nitride or silicon dioxide. oxide) layer or other deposited etch resistant layer. The hard mask layer Si0 ₂ 102 shown is formed on the surface of the wafer 100 . Then, the desired pattern of the photoresist 104 is lithographically patterned on the hard mask layer 102 . In FIG. 1B , the wafer is placed in a holder / chamber 106 and seamed with a 0-ring 108 to protect everything but the front surface. Then, the hard mask layer 102 is etched to produce the desired pattern, removing all hard masks except those lying underneath the remaining photoresist.

In FIG. 1C , a semiconductor etch process is a dry etch, such as deep reactive ion etching (DRIE), or potassium hydroxide, sodium hydroxide, tetramethyl ammonium hydroxide (TMAH) or It is used through wet etching, such as using concentrated alkali wet etching, optionally heated with chemicals such as others. These produce a desired pattern on the surface of the wafer-as shown in the example of FIG . 1C- including the large inverted pyramid structure 112 and the small pyramid structure 110 defined by the ridge 113 . Finally, the photoresist and hard mask are stripped from the wafer and the wafer is cleaned. Then, a porous semiconductor is ready to be formed on the textured surface. Other similar processes are readily derived from these figures by those skilled in the art.

Three-dimensional template patterning is depicted in most diagrams of this content, as it includes embodiments of larger areas. However, unless otherwise indicated, the drawings, process flow diagrams, methods, and apparatus of this disclosure are equally applicable to flat or randomly textured templates.

Using either patterned or un-patterned template, the sequential process steps can be accomplished by wet bipolar etching in porous semiconductor formation [HF-based chemistry]. anodization, such as wet anodic etch, and then rinsing and drying if necessary. Porous semiconductors, such as porous silicon in crystalline silicon templates, are formed on the template on at least one side. In the case where the semiconductor is silicon, the process of forming porous silicon is described, for example, in US Patent Publication No. 2011/0030610, supra. As shown in FIG . 2A , the porous semiconductor formation has a lower porosity region 114 at the surface at at least one low current, and a higher porosity close to template 120 at at least one high current. May involve the manufacture of layer 116 . Importantly, a single porosity layer or graded porosity layer may also be used.

The template with the porous semiconductor layer formed may then be moved to an epitaxial deposition reactor in which an epitaxial layer is deposited on the template on at least one side. 2A shows the deposition of epitaxial layer 118 on top of the porous semiconductor layer system. FIG. 2B is a photograph of a porous semiconductor bi-layer structure in a flat template 122 having a lower porosity 124 above and a higher porosity 126 below.

FIG. 3A shows the deposition of the epitaxial silicon layer 134 on the porous silicon layer 132 formed on the three-dimensional hexagonal template 130 . FIG. 3B is a top view photograph of the released epitaxial thin film silicon layer, such as epitaxial silicon layer 134 in FIG. 3A after it is released from the hexagonal template.

Prior to the epitaxial deposition, during the ramp-up phase or the separate pre-deposition time, the template is heated in a hydrogen ambient that serves several purposes: the porosity The top layer of the semiconductor is reflowed to re-form the quasi-monocrystalline growth surface and ultrathin seed layer (QMS) of the semiconductor. The hydrogen bake also serves to reduce any oxidized surface semiconductor back to its elemental form. In addition, the highly porous semiconductor layer is coalesces to form a weak layer that can later serve as the release boundary between the grown layer and the template. ).

If the semiconductor is silicon, then at the initial stage of deposition or during the bake, the reflow is a lower flow rate of other silicon-containing gas, such as trichlorosilane (TCS). (very low flow quantities) or by small amounts of non-chlorine-containing species such as silanes. This is one option for the process component described below and provided to safely prevent a failure mechanism that may occur during imperfect reflow. Other problems and failure mechanisms that may occur during reflux are described in US Patent Application No. 1, filed Aug. 13, 2011, which is incorporated herein by reference. 13 / 209,390.

There is a potential failure mechanism that may occur during reflux. The solution to this failure mechanism is part of this disclosure: as the template is heated in the semiconductor deposition reactor, which may for example be an epitaxial reactor, the template is generally susceptor at multiple locations. It generally touches the susceptor. Such contact points may contribute to non-ideality at the above-described reflux of the porous semiconductor layer. This contact point may also contribute to local abrasion of the porous semiconductor layer. As a result, the porous semiconductor layer may include local areas unless this is sealed.

Examples of failure mechanisms are shown in the photograph of FIG. 4 , showing template 138 , QMS layer 140 (which generally includes some entrapped holes), and deposited epitaxial layer 142 . It is explained. As the deposition commences after the reflux, two phenomena may be observed: a) deposition of material directly on the template base and through the QMS layer 140 . Fused spot 144 is an example of this phenomenon. This area is free of weakened sub-layers and therefore resists the subsequent release process (described below). In a short time after the start of deposition, the non-hermetic region is sealed and there is a possibility that the deposition gas may be trapped under the top deposition layer. Such deposition gases may include etching components, such as chlorine-containing species, as a byproduct of the deposition reaction of silicon from TCS molecules. Such byproducts may contribute to subsequent etching of the template material. The etched and volatilized template material may be redeposited on the top layer, and thus the etched and volatized template material can redeposit on the top layer, thus re- releasing again the chlorine-containing species). In FIG. 4 , some re-deposited template material 146 may be seen. Thus, it can be observed that in a quasi-sealed local environment, the process can be continuous and template etching can be as severe as several microns. up to several microns). One option to avoid this etching and re-deposition mechanism is to start the deposition using reactants that do not have etching species as by-products. An example of such a reactant is silane in the case of silicon deposition. Another option to avoid both the deposition directly on the template and local etching of the template is the proper formation of the contact area that the template shares with a susceptor. Low contact areas with a large radius suitable for the contact area are preferred. This, together with a suitable heater, needs to enable a uniform thermal ramp and profile in and between the templates.

Regarding the epitaxial deposition process, the epitaxially deposited TFSS may include a in-situ emitter, which is deposited in situ in the semiconductor deposition chamber. The emitter may also be added later as an ex-situ emitter outside of the epitaxy chamber. The structure on the template may be above the emitter (emitter last during deposition) or below (emitter first during deposition). Epitaxial or non-epitaxial deposition may or may not include a suitable dopant gradient designed to assist with the desired flow of carriers generated through the device.

This so fabricated layer structure of deposited semiconductor on a weakened layer on a high temperature capable template is extremely valuable. It allows for carrying a thin film on a solid template and allows more flexibility for being in an on-template process, named below. is in the following called on-template processing).

In this on-template process, the template acts as a carrier to support and move the thin and fragile TFSS through several on-template process steps, including but not limited to: thermal oxidation thermal processes, such as oxidation or film deposition, including but not limited to oxidation; Other laser processes, such as nanosecond pulses (ns), picosecond pulses (ps) or scribing, doping, or ablation; Chemical vapor deposition (CVD) and physical vapor deposition (PVD); Lithography, screen printing, stencil printing, ink-jet printing, aerosol printing, spray coating or etching, ion implantation ion implantation, immersion or single side clean, etching or deposition (like plating), lamination, die attach or bonding, release, surface Dry texturing or wet chemical texturing, rinsing, cleaning and drying of the surface. The only property here is that the template is clean, solar-cell compatible, rigid and sturdy, high-temperature-enabled, and reworkable.

After a suitable on-template process, the TFSS may be released from the template carrier (optionally after its reinforcement with a laminated back sheet, optionally for other applications or to be coated or printed on the TFSS). its reinforcement with a backplane sheet laminated to, coated or printed on or otherwise applied to the TFSS)]. A conceptual diagram of the release of TFSS 154 from template 150 along sacrificial porous layer 152 is shown in FIG. 5 . The release may be performed with or without the use of a temporary or permanent reinforcement plate or sheet attached to the epi layer before the epi release. The reinforcing plate or sheet may or may not include later or at this point a structure, such as dielectrics or electrically conductive cell interconnect materials. If used, the reinforcing plate may be formed at a perforation or otherwise at a later point or to allow electrical contact of the TFSS through or around such perforation, which is present at the time of TFSS release, the reinforcing plate. If used, the reinforcement plate may contain perforations or otherwise a plurality of electrically conductive locations enabling the electrical contacting of the TFSS through or around the reinforcement plate, such perforations being present either at the time of TFSS release or formed at a later point). Suitable reinforcing materials include polymers such as silicone, glass, silicon-aluminum alloys, prepreg or other dielectric adhesives, or plastics, aluminum, ceramics or combinations thereof. It may also contain the same metal. At a suitable point in time before emission, a border cutting or definition of the TFSS region to be emitted can be achieved using, for example, a laser. 4 shows a border cut 156 near the TFSS 154 .

Such boundary cleavage may be performed before or after release of the TFSS. This may make it advantageous to cut both before release and after release, depending on the strengthening process and the material. The demarcation is also provided to weaken the thin TFSS, thus allowing easier release. Another potential method for facilitating easier release is the use of grinding or otherwise an abrasive method, preferably to be applied to the edge of the template. By doing so, the TFSS epitaxial layer region at the edge of the template can be provided as a weak point from which emission can be initiated. Such pre-release grinding can also promote the flow of air into the weakened area between the TFSS 154 and the template 150 , whereby pressure equalization is achieved. It becomes possible and the pressure-differential-induced resistance to release motion is eliminated. The release itself may be performed by utilizing the presence of local weak areas that serve as initial locations for the release.

Alternatively, a pulsed force may be applied, for example by pulsating the vacuum on either side of the template and substrate sandwich. In this way, the release process can be extended across location and time (not unlike opening), rather than overcoming the overall area binding force plus atmospheric pressure holding force on the template. a zipper), rather than having to overcome the whole area bond force plus the atmospheric pressure holding force on the template). In general, the release may commence at the corners or edges of the substrate and then in parallel, essentially to avoid a small radius of curvature, which may contribute to potential cracking and excessive stress of the effective TFSS layer. Alternately, the release can be initiated at an edge or a corner of a substrate and then proceed from there, while in the process keeping the template and the partially released TFSS essentially parallel, in order to avoid small curvature radii, which can contribute to excessive stresses and potential cracking of the active TFSS layer).

After release of the valid TFSS, there may be residual deposited thin film remaining outside of the valid area, especially if the template is somewhat larger for the valid TFSS. 6A shows two possibilities. Template 200 has a layer 202 of porous semiconductor, extending beyond the edge 204 of the TFSS. This does not indicate a problem with the release.

However, in a typical CVD deposition process, material may be deposited according to the design, not only on the front side, but also on the edge and back side of the template. The extent of the film range is shown in template 210 . Thick deposition of a semiconductor layer in the bevel area may be undesirable. Depending on the process, deposition on the backside may be detrimental for subsequent processing, or may be desired if the back deposition yields a comparable film for the frontside deposition in the case of a two-sided process. Some prevention means is a template (210) instead, to be taken to be the similar to the template and the template (200) (Several precautions may be taken in order to wind up with a template 200 like template instead of template 210). One mode to avoid or minimize backside and bevel deposition is to use a neutral gas, such as hydrogen, as a purge gas near the backside and edge of the template during the deposition step. Another mode to avoid or minimize backside and bevel deposition is to use a shadow mask where the deposition blocks unwanted areas from the deposition gas. A third mode for reducing backside and bevel deposition is to deposit material preferentially from the gas phase, thereby serving to reduce the deposition gas in areas where deposition is not desired, or large surface areas or else It is to use susceptor designs with optimized geometry. The deposition process may have desirable locations and directions when more or less material is deposited in unwanted areas. This may be advantageous to coordinate deposition of the unwanted material over some re-use of the same template. For that purpose, the template direction can be moved where needed, and provided changes in the direction or position can be programmed as part of the production flow.

In the template 210 , the porous silicon layer 212 partially surrounds the edge of the template, while the TFSS 214 further encloses it. Under circumstances where the TFSS extends beyond the edge of the porous semiconductor, other methods may be used to remove sections of the TFSS that directly contact the template.

Figure 6b, illustrates a TFSS emission in the case of template 200. The TFSS 204 is released such that it leaves away with little edge debris. After emission, the TFSS 204 may be cut to size by the laser 206 .

6C shows that when the TFSS extends beyond the edge of the porous semiconductor layer or when the porous semiconductor is not formed with thickness or porosity in the bevel region sufficient for easy release of the TFSS, FIG. Template 210 is shown. The TFSS 214 is cut to size by the laser 216 and then emitted from the template 210 . After release, the residual film must be removed sequentially. Section 218 , which is bonded to a porous semiconductor layer that is not directly to template 210 , is formed by a machining process, such as grinding or lapping residual film from the template, or By acoustic (ultra- or megasonic) energy, compressed air, high or elevated pressure water, or other suitable fluid, It may be removed by the use of a taping-detaping process. The grinding can be performed, for example, by a soft material that cuts out the excess thin film deposition, or by using a grinding material that is polished with the appropriate rigidity for that of the semiconductor. using a grinding material that is abrasive and has a suitable hardness with respect to that of the semiconductor or by a soft material, which shears off the excess thin film deposit). The latter makes use of the fact that the binding force of the excess material is low and depends on the weakened layer between the thin film and the template. Removal of excess thin film can also occur by appropriate chemical etching. Proper chemical etching can be selected to yield a composition based on good dopant concentration or selectivity between the deposited film and the template. . It may also take advantage of the use of direct, localized etch.

Removal of the remaining deposited thin film may be performed on a single wafer basis or in batch mode. The removal process described so far is designed to remove minimal material from the flat portion of the template that extends on the bevel of the template at the bevel edge and outside of the active area. Another method is to remove the residue 220 of the TFSS that binds directly to the template 210 due to local lacking or imperfect quality of the porous semiconductor layer. It can also be used to

Apart from the precautions mentioned above, it may be advantageous to remove excess deposited material from the bevel or the backside area. This removal of excess deposited material may be carried out after each re-use cycle or after several re-use cycles and may be repeated throughout the lifetime of the template. FIG. 6D illustrates the use of grinding tape 224 to remove residue 220 and local imperfection 222 , and FIG . 6E illustrates grinding, polishing, or It illustrates the use of a machine tool for an alternative abrading device. With this device, excess deposited material in the bevel or back region can be removed or completely removed. In the case of the tape based grinder, the template may be rotated in the presence of a tape, usually sandwiched with diamond or silicon carbide. For non-round template geometries, such as squares or similar-squares, the removal setup is for example to move left, right, rotate or if swiveled or oscillated, it shall be different; Or the tape holding / feeding mechanism may be moved, rotated or vibrated. The removal process can be adjusted to remove material preferentially in areas where excess material is deposited. Removal of the deposited material at different points in time around the elevated bevel or back region is performed by applying the tool, tape or sheet at different angles, pressures, or locations towards the template. Other removal implementations for the deposited material will be apparent to those skilled in the art. An alternative process for this type of mechanical removal of excess deposition from the template is the use of a suitable chemical applied locally with the goal of removing the excess deposition from the template. to be.

In FIG. 6E , a precision grinding wheel 226 (or polishing wheel or slurry) was used to remove the film around the edge of template 210 . However, this may leave backside residue 228 , which may be removed, for example, by the use of backside grinder 230 . It is also envisaged to combine the functions of the edge backside grinding wheel and the bevel grinding wheel into one tool.

Another alternative process for the tape, sheet or precision bevel grind / polish step is to take the bevel in a new form and to avoid excess deposition on the underside and the bevel of the template. To remove it is the use of a direct or water-jet-guided, laser. The effect of the laser based bevel material removal process is shown in FIG. 6F . This method may in particular have the advantage of enabling precise predimensional control. The combination of the above methods is also plausible. As shown, any template 210 is removed by the laser edge ablation used in FIG. 6F .

In some cases, the process shown above in conjunction with FIGS. 6C-6E will leave some unwanted additional TFSS material on the front as well as the back of the template. In such a case, as shown in FIG . 6G , grinding machine 232 may be used to remove such material. If this is not the case, the remaining front TFSS material may cause the next TFSS generated on template 210 to "lock" to such a point making release more difficult. is not done, the remaining front side TFSS material may cause the next TFSS produced on template 210 to "lock" to that point, making release more difficult). This concern may be alleviated by removing excess material prior to reusing the template.

After removal of the unwanted TFSS material by any method, the general flow may include re-use cleaning, which serves several purposes: first, continuous repeated re- Bringing the template into reusable conditions, which can be used; Second, to remove the remainder of the sacrificial release layer; Then to remove metallic contaminants that may be detrimental to the life of subsequent TFSSs to be deposited on the same template; Finally, to remove the detrimental remnants of any on-template processes, such as organic or metal-containing residues. Generally, after the re-use wash, the template repeats the porous semiconductor forming process again, thereby forming another sacrificial release layer. This then again deposits the thin film to be released. The next process as indicated above is continued.

Residual deposition extended on the backside of the template may be detrimental to further processing, and the template may be repeatedly subjected to the sacrificial layer formation / deposition process. It can also accumulate as it proceeds sequentially to further processing / release / post-release treatment processing. Residual deposition on the backside can cause local stress points and unsmooth template surfaces that are detrimental to handling and may increase the propensity of the template to break. . Therefore, removal or prevention (shown above) of back deposited material may be advantageous. This may be performed after several re-use cycles or after each re-use cycle, and may be repeated during the lifetime of the template. This method can be performed by removing material from the complete backside area or by only locally removing material from the wafer edge that is primarily deposited at the edge of the backside.

The template is a very valuable commodity in the overall process. Thus, any process provided to extend the potential number of deposition cycles (template reuse cycles) in which the template can be sustained may result in the value proposition (template replacement cost of template per cell). Is substantially reduced). Thus, in the event of defective processing on the template or incomplete release or removal of the TFSS film, the template may be subjected to a reconditioning process. This regeneration process may consist of grinding and / or smoke screening only of the problematic portions of the template or of the complete area of the template. After successful playback, the template can be reentered into the process loop and re-use can be resumed.

Softening and / or polishing can be accomplished using single or double side grinders / polishers. The softening / polishing process is selected according to the needs of the surface finish. The TFSS shown above, which later form the substrate for the solar cell, do not depend on the mirror polished surface finish of the substrate. Thus, it is important to point out that the porous semiconductor sacrificial layer may be formed on a template surface that does not start as a mirror polished semiconductor surface. If the thickness is known, if the thickness is known, it is not known in advance where the incomplete process of the substrate occurs and the HVM-compatible soft / smoke process wastes the least amount of material from the starting template. It is advantageous to inspect the templates in the release process after one step and classify them into thickness ranges so that they can proceed simultaneously in the grinding machine / smoker with a same target thickness. The classification of local residues from the thickness and the deposition can be performed simultaneously with a suitable device, such as optical, capacitive or gas back pressure based sensing.

The TFSS, which may be released from the template carrier and may already have some process of applying it in the template, may be further processed after the release. For sufficient layer thickness, there are several possible embodiments for the TFSS and its further processing: The TFSS is self-supporting and can be processed through additional processing as is. If the template used to deposit the TFSS material thereon is organized to form a three-dimensional structure, such as a number of pyramids, prisms or other three-dimensional geometry, and then the deposited TFSS material Although the amount of is very small, the TFSS may be able to stand on its own. This structural feature is a potential advantage of the three-dimensional template and TFSS. If the layer thickness is not sufficient for the TFSS to allow for self-supporting, the TFSS may be supported through additional processing through a suitable support plate, sheet or film.

Although not limited to the above, the following description and corresponding drawings are more directly related to the subject matter described in this application. The purpose of the method shown above is to extend the useful life cycle of such templates and to reduce the amortized cost of making and using such templates. This is at least appropriate doping, or similar doping, to form porous semiconductor / silicon by anodization (or bipolar etching) on this template with the aid of epitaxial deposition at an appropriate doping level. (like doping) may be achieved by adding similar materials, shown herein as "reconstructing materials." For example, if the starting template consists of p + doped silicon, the epitaxial film may also be in-situ doped with a p-type dopant such as boron (p +) ( in-situ-doped, and the added reconstitution material will be appropriately doped (p + doped) to form the porous layer using an anodization process.

This deposition process may be performed once the template thickness is lower than the desired value, or once per template reuse cycle, or preferably once per multiple template reuse cycles, to add thickness and material strength. It may be advantageous or used whenever necessary.

In general, such reconstituted materials may be: a) defective or too thin templates (with respect to the useful number of template reuse cycles) to extend useful life; b) provide a thicker template that enables the template to provide a longer useful life cycle and provides a lower cost of redemption template per cell; c) improving / planarizing the surface of the starting wafer to provide a smoothed surface for subsequent processing; And d) providing a better template thickness range than before, through the lifetime of the template, which may be caused by excessively different template thicknesses, such as but not limited to this variability associated with the heat capacity of the template. (process variabilities) may be minimized.

As indicated above, after the TFSS has been released from the template, the template may be subjected to the same porous silicon (including a removal process, a reconditioning process, attachment of a supporting backplane or optional application). In order to be able to repeat the PS) formation, the TFSS deposition, the on-template process, surface etching / cleaning and other processes can be used to further process steps. During this cycle, the template is reduced in thickness.

However, there is a practical limit to significant template thickness loss, and due to the loss of material thickness, template strength will be reduced, and the rate of template breakage may be excessive, resulting in substantial yield loss. .

In order to avoid this weakness of template thickness loss, the method shown above is to extend the life of the template by thickening a similar-epitaxial film, crystalline, preferably of another way of epitaxial or similar doping. extend the life of the template by thickening it up with a crystalline, preferably epitaxial or otherwise quasi-epitaxial film of like doping). Similar-epitaxial films are defined herein as films grown on templates, which are themselves similar-monocrystalline templates, such as from silicon wafers produced from quasi-monocrystalline ingots. This process is shown generally in FIGS. 7A-C , representing a three-dimensionally structured template and a planar, substantially planar, as an exemplary embodiment, and optionally a pre-textured template (pre- textured templates may also use the same method. As template 300 goes through the TFSS fabrication process, the thickness of the template, shown in FIG. 7A as the original thickness hA , is reduced to a smaller thickness hB , as shown in FIG. 7B . [For clarity of explanation, thickness reduction does not represent scale]. As shown in FIG . 7A , the ridge, inverted pyramid 302 of the three-dimensional structure is on an equivalent plane with the flat front template edge. However, FIG. 7B shows that the ridges of the three-dimensional structure are not equivalent planes to the flat template edges, after the template is thinned from anodizing and / or wet etching-they are Substantially lower. The thickness of the template may then be increased by epitaxially depositing a similar material 304 for the template that increases the template thickness, shown in FIG . 7C , as hC . As shown, the reconstructing semiconducting material 304 is of the same type and the doping concentration as the starting template shown in FIG . 7A . Also note that the ridge of the three-dimensional structure has been restored to an equivalent plane with the flat template edges. Thus, the template thickness and three-dimensional structure are recovered by the deposition of a layer of similar material on the template top surface (used for the formation of PS).

Importantly, the method provided may be applied to a template or wafer with any three-dimensional surface topography—generally three-dimensional surface topography is used to determine the appearance of the cavity on the surface of the template. A cavity defined by a ridge forming an opening of the cavities.

The thickening process may be performed for multiple times during the template life cycle. By doing so, especially if the epitaxial deposition process on a provided template can be carried out in a more cost-effective manner than producing the starting template by a wafering process, greater value for the template may be added. Periodic or otherwise regular thickening of the template, for example after a fixed number of re-uses or when the thickness drops to a certain threshold, produces During processes such as line sustaining and heat induced annealing, growth or deposition, printing or lithographic processes, lamination, and other processes that benefit from smaller range thicknesses Favorable for tight control.

As a difference, this starts with a lightly doped template and more through the epitaxial deposition of the thickened layer (shown in the figure as the top surface of the template) and the subsequent anodization cycle ( It is possible to dope only the area that has undergone subsequent anodization cycles. This may enable the use of a lower cost starting template, as the price of the semiconductor wafer is generally influenced by the amount of dopant. Also, through out an ingot, the doping level generally receives a prominent profile. Thus, the impact these doping variations have potential in the formation of the TFSS throughout the lifecycle of the template, and the formation of the numerous TFSSs may be anodized to form the porous layer. May be reduced by depositing reconstitution material only on the template surface layer. Other embodiments include starting with a higher doping concentration for the template and depositing a lower doping concentration on the surface. Potentially adding to the template cost, along with the arrangement, allows for very effective equalization of the electric field across the wafer during the anodization process used to form the porous semiconductor layer or layers. Let's do it.

Another benefit of depositing a relatively thick layer of epitaxial silicon over the template to thicken the template thickness includes smoothing process imperfections that may be encountered during the cycle of re-use of the template.

First, as part of the removal of the thin film (TFSS) of the template, a cutting process may be used, for example using exclusively lasers. This cutting process may be intentional or unintentional due to the difference in producing markings and cuts on the surface of the template (the cutting process may intentionally or unintentionally due to variations generate cuts and marks on the surface of the template). Such cleavage may be smoothed by subsequent etching to provide a crystalline growth surface. The thick epi deposition to thicken is used to planarize the new starting surface, thus preventing the subsequent negative effects of cut marks.

Second, the PS anodized layer is not perfect because there are generally zones / regions on the template, usually due to contact forces, handling or particulate contamination from the susceptor or carrier. not. Then, during the baking process prior to epitaxial TFSS deposition, the top layer does not completely reflow into the affected area. This may lead to zones on the template when a complete removal of the TFSS is no longer possible because part of the TFSS is fixed to the template. The template edge region is particularly prone to this occurrence. Since the TFSS generally does not have the right doping to enable subsequent PS formation, the surrounding areas can obtain an optimal current density during anodization, and As the silicon deposited on the fixed area will itself provide a holding force that resists the removal of nearby TFSS material, the fixed area tends to increase both height and width.

Depositing the thick epitaxial film of the right doping concentration again to form the PS may again create such defective spots / regions that are suitable for release. This process is shown in FIGS . 8A-B , where a three-dimensionally structured template is shown, but the same concept applies to a substantially flat or randomly pre-textured template. do. 8A shows template 310 after several TFSS fabrication and re-use cycles with residual epi layer 312 . The remaining epi layer 312 has an incorrect doping concentration for PS formation, and as a porous semiconductor or porous silicon may not be formed on this layer, this will be a continuous bond in the TFSS formation process.

In FIG. 8B , epitaxial growth layer 314 as well as residual epi layer 312 are formed on the remaining said template surface used for PS formation (top surface). The epitaxial growth layer 314 is suitably doped to form porous semiconductor / silicon (PS) and allows formation of PS on the entire template surface, thereby degrading the defective remaining epi layer 312 . Alleviate and enable effective and clean release of the TFSS from the template.

The epitaxial deposition of the thickened layer is optionally followed by treatment of the beveled edge of the template to remove the thickening layer on the beveled edge. You can also Such further processing may reduce the sharp facets at the edges that are part of the epitaxial growth properties and may be harmful for example, template strength.

Such edge treatment may be carried out in a number of ways, such as through edge bevel grinding / polishing, through a tape or laser edge bevel process, or chemical etching close to the template edge. In conjunction with zone softening / polishing, this same method may also be performed at the edge of the template back side to reduce the effect of any backside deposition at the edge of the template.

The cost of monocrystalline or similar-monocrystalline semiconductor wafer fabrication is typically performed by the latter, as a monocrystalline-seeded similar monocrystalline ingot, by chokolaski growth or by casting, and then on the wafer. Cropping, Squaring, Slicing, Bevel Grinding, Lapping, Etching, and Polishing—Monocrystalline or quasi-monocrystalline semiconductor wafer manufacturing cost is often determined by the process involved, such as starting material cost and ingot growth. governed by the processes associated with the manufacturing steps such as starting material cost, ingot growth-typically performed by Czochralski growth or by casting, the latter potentially as a monocrystalline-seeded quasimonocrystalline ingot-then cropping, and squaring, slicing, bevel grinding, lapping , etching and polishing of the wafer).

In order to use such wafers as templates for repeated semiconductor material deposition and effective removal / release process costs, it is necessary to keep the cost of these templates to a minimum. Since lapping, softening and / or polishing represents a substantial component of cost, it is desirable to replace them in a less expensive step or to avoid these steps altogether.

Additionally, thin film or thin foil solar electrical substrates may be produced using the starting substrate after slicing and optional bevel grinding have undergone a saw damage removal etch. However, such thin film solar cell substrates transfer away from the saw marks in the residual template topography through removal of associated sub-surface damage. saw marks even though associated sub-surface damage is removed). Such residual topography may or may not be desirable.

As part of the deposition process for thin film semiconductor solar cell substrates, high volume, low cost epitaxial reactors have been developed. This reactor enables the deposition of smooth films with planarizing characteristics at low cost.

Thus, in order to reduce the manufacturing cost of a relatively smooth wafer, a waiter cut after optional beveling, saw damage removal, and cleaning has an epitaxial layer deposition having a dopant level close to or similar to that of the starting wafer. In order to reduce the manufacturing costs of relatively smooth wafers, the process may be carried out such that-sliced wafers, after optional bevel treatment, saw damage removal, and cleaning receive an epitaxial layer deposition with a dopant level resembling or close to the level of the starting wafer). 9A-C illustrate some important manufacturing steps of this process. 9A shows a wafer 320 having slicing saw marks 322 and sub-surface damage 324 generated from cutting the wafer from an ingot. 9B shows wafer 320 after saw damage removal etching has been operated to remove sub-surface damage 324 except slicing top mark 322 . Figure 9c, the template (320 after wafer 320, as similar to the topping (like doping) the front / top surface epitaxial deposition of having layers (326) (front / top side epi deposition) and saw damage removal etch (saw damage removal etch) ). The planarization effect of epitaxial deposition of layer 326 provides smooth surface topography 328 on the slicing saw marks shown in FIGS . 9A-B , which further template processing. To make it possible. After such deposition canthen the wafer surface may be used to form and release a smooth thin film semiconductor solar cell substrate or may be processed to form a textured pattern or three-dimensional surface features. The epitaxial layer deposition is shown on the cross section of the wafer. However, for example, to form a porous semiconductor emission layer on both sides of the wafer or template, and then perform such deposition sequentially or simultaneously on both sides of the wafer to obtain solar cells from both sides of the template. It is also expected.

In contrast to wafer wrapping, softening or thinning, which consumes all of the silicon in the process and thins the wafer, as an additional benefit, the use of a deposited film substantially thickens the wafer, thereby allowing a greater number of ashes. It is made available by a larger number of re-use cycles.

From the foregoing, epitaxial and doped types and appropriate thicknesses for other applications such as the formation of templates for solar cell substrate production as well as the manufacture of micro-electro-mechanical structures (MEMS). Other advantages of depositing a tactic layer can be derived by those skilled in the art.

The above-mentioned topics generally relate to the deposition of thin or thin foil materials, but more particularly to the deposition of epitaxial monocrystalline or similar-monocrystalline silicon films (epifilm) for use in the manufacture of high efficiency solar cells. It is related. In operation, the method is shown to reduce the amortized cost of the substrate or template used in the manufacturing process of silicon solar cells and to extend the reusable life. Additionally, the method has been shown to provide a conversion of a low quality starting surface of a silicon wafer to an improved quality starting surface.

Those skilled in the art will appreciate that the embodiments shown above relate to a wide variety of areas in addition to these specific examples described above.

The above-described techniques of such representative embodiments are provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles set forth herein above may apply other embodiments without the use of breakthrough capabilities. Thus, the claimed subject matter is not intended to be limited to the embodiments shown herein but is to allow the widest scope consistent with the novel features and principles presented herein.

All such additional systems, methods, features and advantages that fall within this description are intended to be included within the scope of the claims.

Claims (20)

Preparing a reusable doped crystalline semiconductor template;
Forming a porous semiconductor sacrificial release layer on a front side of the reusable crystalline semiconductor template;
Epitaxially depositing a thin film semiconductor substrate conformally to the sacrificial emission layer;
Releasing the thin film semiconductor substrate from the reusable semiconductor template by separation in the porous semiconductor layer; And
Epitaxially depositing a thicking layer of semiconductor material on the front surface of the template, the thick layer being a like material and having a like polarity Phosphorus, step;
A method of manufacturing a thin film crystalline semiconductor substrate comprising a.
The method of claim 1,
And further device processing steps are performed after the epitaxial deposition of the thin film semiconductor substrate and before the emission process step.
The method of claim 1,
Epitaxially depositing a thick layer of semiconductor material is performed after epitaxially depositing the thin film semiconductor substrate and subsequently a plurality of process cycles of ejecting the thin film semiconductor substrate. of semiconductor material is performed once after a plurality of said epitaxially depositing a thin film semiconductor substrate and subsequently releasing said thin film semiconductor substrate process cycles).
The method of claim 1,
Wherein said thin film crystalline semiconductor substrate is used for the manufacture of a solar cell.
The method of claim 1,
A laser process is utilized prior to the step of releasing the thin film semiconductor substrate from the reusable semiconductor template by separation in the porous semiconductor layer. reusable semiconductor template by separation at said porous semiconductor layer), method.
The method of claim 1,
Wherein the crystalline semiconductor comprises crystalline silicon.
The method according to claim 6,
Wherein the crystalline silicon comprises monocrystalline silicon.
The method of claim 1,
And the reusable doped crystalline semiconductor template comprises a substantially planar surface for the formation of the thin film crystalline semiconductor substrate.
The method of claim 1,
And the reusable doped crystalline semiconductor template comprises a textured surface for formation of the thin film crystalline semiconductor substrate.
The method of claim 1,
And the reusable doped crystalline semiconductor template comprises three-dimensional surface topography for the formation of the thin film crystalline semiconductor substrate.
11. The method of claim 10,
Wherein the three-dimensional surface topography comprises ridges and a surface cavity defining an opening in the surface cavity.
12. The method of claim 11,
Epitaxially depositing a thick layer of semiconductor material on the front surface of the template to restore the ridge to a position that is substantially planar at the front edge of the template.
The method of claim 1,
Wherein the doped semiconductor template is lightly doped and the thick layer of semiconductor material is more highly doped to enable producing the porous semiconductor material.
The method of claim 1,
Further comprising using bevel grinding of the template comprising an epitaxially deposited thin film semiconductor substrate to define the boundaries of the thin film semiconductor substrate prior to the emitting step, thereby facilitating the release step. Let, how.
The method of claim 1,
Polishing or grinding the thick layer of semiconductor material from the beveled edge of the reusable semiconductor template, thereby strengthening the template.
The method of claim 1,
Epitaxially depositing a thick layer of semiconductor material on the front surface of the template, wherein the reusable doping? Wherein the thickness of the semiconductor template is measured after the determination of whether the thickness is below a predetermined threshold.
The method of claim 1,
Epitaxially depositing a thick layer of semiconductor material on the front side of the template may occur when an epitaxial layer is present on the front side of the reusable semiconductor template, with a dopant that is not suitable for forming a porous semiconductor layer. (Said step of epitaxially depositing a thickening layer of semiconductor material on said front side of said template is performed when there exists an epitaxial layer on said front side of said reusable semiconductor template with a dopant non-suitable for porous semiconductor layer formation).
The method of claim 1,
Wherein said step of releasing said thin film semiconductor substrate from said reusable semiconductor template by separation in said porous semiconductor layer further comprises using a laser process.
Performing a saw damage removal etch on the doped wafer cut from the ingot; And
Epitaxially depositing a planarizing layer of semiconductor material on the wafer, wherein the planarization layer is a material similar to the wafer and has a similar polarity;
Method for smoothing the wafer surface comprising a.
20. The method of claim 19,
Wherein the wafer is a monocrystalline silicon wafer.

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