KR101358491B1 - Led package and method for manufacturing the same - Google Patents

Abstract

Provided are a LED package and a method of manufacturing the LED package. The LED package comprises: a base substrate forming a first recess on the upper surface and a second recess on the lower surface; an upper surface insulating layer formed on the upper surface of the base substrate; a lower surface insulating layer formed on the lower surface of the base substrate; a first electrode and a second electrode passing through the base substrate and formed on the upper part of the upper surface insulating layer and the lower part of the lower surface insulating layer; a LED chip electrically connecting to the first electrode and the second electrode and formed on the first recess; and a mold sealing the first recess.

Description

LED package and LED package manufacturing method {LED PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a LED package and a LED package manufacturing method, and more particularly, to an LED package and a LED package manufacturing method for improving durability and heat dissipation efficiency.

A light emitting diode (LED) refers to a device capable of realizing various colors by forming a light emitting source using compound semiconductor materials such as GaAs, AlGaAs, GaN, InGaN, and AlGaInP. Recently, LEDs are widely used in various products, and their applications are gradually expanding.

In addition, electronic devices such as portable devices such as TVs, LCDs, cell-phones, and PCs (notebooks) or household appliances are rapidly progressing in performance, miniaturization, integration, and modularization. Higher performance requires more power consumption for LEDs mounted in electronics, while miniaturization and integration have limits on the size that can be commercialized.

While the market demands a direction in which the amount of power consumed by LEDs mounted in electronic products increases, the design margin of LED packages capable of extinguishing them is rapidly decreasing. In other words, modularization suggests that the problem of heat is no longer just a single LED product, but the entire system.

That is, the problem of efficiently managing the heat generated from the LED chip inside the LED package has become a factor that affects not only the electrical and optical characteristics of the product, but also the life of the product, the reliability of the product, and the manufacturing cost.

An LED package is a device manufactured to mount an LED inside, connect an LED to a lead, and attach the printed circuit board to a printed circuit board (PCB). With the trend towards lighter and shorter trends in telecommunications devices, LED packages are being made of Surface Mount Device (SMD) type mounted directly on a printed circuit board. Recently, a wafer level package (WLP) technology, which is a packaging technology that combines silicon semiconductor process technology and LED technology, has been introduced.

Wafer-level packaging differs from conventional LED packaging methods (ie, packaging by placing the LEDs in a package frame of a printed circuit board or packaging the LED chips with a lead frame and compounding the LEDs), and punching the LEDs in a silicon wafer. It is a technology that can package a large number of LEDs at the same time by eliminating the need for a lead frame by packaging with chips.

Wafer-level packages use silicon wafers with high thermal conductivity, which reduces heat generation, which is a structural problem of LEDs. However, heat generation problems in high-power LEDs are still unresolved.
[Related Technical Literature]
1. LED package using metal substrate and method of manufacturing the same (Registration No. 10-0616692)

Accordingly, an object of the present invention is to provide an LED package and an LED package manufacturing method that improve durability and heat dissipation efficiency as the LED package itself by utilizing a wafer-level package technology and a membrane stack structure.

Another problem to be solved by the present invention is to provide an LED package and an array of LED packages capable of light and short and high luminance.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The LED package according to an embodiment of the present invention for achieving the above object, the first substrate is formed on the top surface and the second recessed portion formed on the lower surface, the upper surface insulating layer formed on the upper surface of the base substrate And a lower surface insulating layer formed on the lower surface of the base substrate, first and second electrodes penetrating the base substrate and formed under the upper and lower surface insulating layers of the upper surface insulating layer, and the first and second electrodes. And an LED chip electrically connected to the second electrode and formed in the first recessed portion and sealing the first recessed portion.

Preferably, in the LED package according to another embodiment of the present invention, the first recessed portion and the second recessed portion are formed at the corresponding positions in the vertical direction, and the first electrode and the second electrode are the first recessed portion and the second recessed portion. Each penetrates through the base substrate between the depressions.

Preferably, in the LED package according to another embodiment of the present invention, the mold may include a phosphor.

Preferably, in the LED package according to another embodiment of the present invention, the base substrate may be a silicon substrate.

LED package manufacturing method according to an embodiment of the present invention for achieving the above object, and forming a first recessed portion on the upper surface of the base substrate and forming a second recessed portion on the lower surface of the base substrate, An insulating layer forming step of forming an upper insulating layer and a lower insulating layer on upper and lower surfaces of the base substrate, and a conductive layer forming step of forming a conductive layer under the upper and lower insulating layers of the upper insulating layer; And an electrode forming step of forming a conductive layer as a first electrode and a second electrode, and an LED chip encapsulation step of forming an LED chip in the first recessed portion and sealing the first recessed portion with a mold.

The details of other embodiments are included in the detailed description and drawings.

The embodiments of the present invention have at least the following effects.

That is, the LED package according to various embodiments of the present invention has an effect of improving durability and heat dissipation efficiency through its own structure.

In addition, since the LED package according to various embodiments of the present invention is manufactured using a semiconductor wafer, it is possible to quickly manufacture a large amount of LED package or LED package array.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a cross-sectional view illustrating an LED package according to an embodiment of the present invention.
2 is a cross-sectional view illustrating an LED package according to another embodiment of the present invention.
3 is a cross-sectional view illustrating a method of forming a depression in various embodiments of the present invention (one embodiment and another embodiment).
4 is a view for explaining the appearance of the LED package array using the LED package according to an embodiment of the present invention.
5 is a cross-sectional view illustrating a surface-mounted LED package according to an embodiment of the present invention on a printed circuit board.
6 is a cross-sectional view illustrating a surface-mounted LED package according to another embodiment of the present invention on a printed circuit board.
7 is a flowchart illustrating a method of manufacturing an LED package according to an embodiment of the present invention.
8 is a view for explaining a process of forming a depression of the LED package according to an embodiment of the present invention.
9 and 10 are views for explaining a process of forming the first and second electrodes of the LED package according to an embodiment of the present invention.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

It is to be understood that when an element is described as being "connected" or "in contact" with another element, it may be directly connected or contacted with another element, but it is understood that there may be another element in between something to do. In addition, when a component is described as being "directly connected" or "directly contacted" with another component, it may be understood that there is no other component in between. Other expressions that describe the relationship between components, for example, "between" and "directly between" or "adjacent to" and "directly adjacent to", and the like may also be interpreted.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprising," "comprising" or "having ", and the like, specify that there are performed features, numbers, steps, operations, elements, It should be understood that the foregoing does not preclude the presence or addition of other features, numbers, steps, operations, elements, parts, or combinations thereof. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application .

It is to be understood that elements or layers are referred to as being "on " other elements or layers, including both intervening layers or other elements directly on or in between. Like reference numerals refer to like elements throughout.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the technical scope of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating an LED package according to an embodiment of the present invention. As shown in FIG. 1, the LED package 10 according to the exemplary embodiment of the present invention may include a base substrate 100, an upper insulating layer 131, a lower insulating layer 132, and a first electrode 141. , A second electrode 142, an LED chip 900, and a mold 150.

The base substrate 100 is a part that becomes the body of the LED package 10 and may be formed of silicon (Si). However, the base substrate 100 is not limited to being formed of only silicon. The base substrate 100 performs a function of supporting the LED package 10 and at the same time, performs a heat radiation function of conducting heat generated from the LED chip 900 to be described later. In particular, the heat dissipation function described above will be described later, and the base substrate 100 may be formed of silicon (Si), and the base substrate may be covered with a metal material to maximize the heat dissipation effect.

In addition, the LED package 10 according to an embodiment of the present invention includes a first depression 121 and a second depression 122. The first recess 121 is formed on the upper surface of the base substrate 100, and the second recess 122 is formed on the lower surface of the base substrate 100.

Hereinafter, a method of forming the first recessed part 121 and the second recessed part 122 will be described with reference to FIG. 3.

3 is a cross-sectional view illustrating a method of forming a depression in various embodiments of the present invention (one embodiment and another embodiment). Herein, the method of forming the depressions in one embodiment of the present invention will be described with reference to FIG.

The first recess 121 is formed by etching the photoresist 501 on the upper surface of the base substrate 100. In particular, an embodiment of the present invention may use anisotropic etching. Anisotropic etching is an etching method having a large difference in the degree of etching in the depth and width directions, and etching a surface in a predetermined direction among the crystal surfaces of the etching target. therefore. The first depression 121 is formed after the completion of etching, beginning with the formation of the first depression 1121 at the start of etching. The first recess 121 formed by the anisotropic etching has the shape of the remaining portion except for the complete cone when the horizontal cut cone, that is, one cone is cut horizontally. It should be noted that the above description of the shape of the first recess 121 is merely exemplary, and the shape of the first recess 121 is not limited thereto.

Since the formation of the second depressions 122 is substantially the same as the formation of the first depressions 121, redundant description thereof will be omitted.

The first recess 121 and the second recess 122 may be formed with a time difference or may be simultaneously formed.

Referring back to FIG. 1, the upper insulating layer 131 and the lower insulating layer 132 are formed on the upper and lower surfaces of the base substrate 100, respectively.

In an embodiment of the present invention, the upper insulating layer 131 and the lower insulating layer 132 are formed by depositing a silicon dioxide (SiO 2) layer on the base substrate 100. The upper insulating layer 131 and the lower insulating layer 132 prevent the first electrode 141 and the second electrode 142, which will be described later, from being energized with the base substrate 100.

Next, the first electrode 141 and the second electrode 142 penetrate the base substrate 100 and are formed under the upper and lower insulating layers 132 of the upper insulating layer 131. The first electrode 141 and the second electrode 142 are not electrically connected to each other. That is, the first electrode 141 is formed on the upper surface insulating layer 131 through the first via hole 191 of the base substrate 100 and the lower surface insulating layer 132. The first electrode 141 formed under the) is integrally formed.

Similarly, the second electrode 142 is formed below the second electrode 142 and the lower surface insulating layer 132 formed on the upper surface insulating layer 132 through the second via hole 192 of the base substrate 100. The second electrode 142 formed at is integrally formed.

The first electrode 141 and the second electrode 142 should not be connected to each other. Therefore, the first electrode 141 and the second electrode 142 are not physically connected by the predetermined portion 181 on the upper surface insulating layer 131. In addition, the first electrode 141 and the second electrode 142 are physically connected in the lower surface insulating layer 132 because no conductive material is placed between the first via hole 191 and the second via hole 192. It doesn't work. Herein, the predetermined portion refers to a portion or region in which the first electrode 141 and the second electrode 142 formed on the upper surface insulating layer 131 are physically separated from each other so as not to be energized. It is not fixed but can be changed.

The first electrode 141 and the second electrode 142 are connected to a substrate electrode (see 601 and 602 of FIG. 5), which will be described later, respectively, and have the same polarity as that of the substrate electrode (see 601 and 602 of FIG. 5). Each of the 900 and the LED chip 900 is electrically supplied with power. That is, when the first electrode 141 is connected to the substrate electrode 601 of FIG. 5 and the second electrode 142 is connected to the substrate electrode 602 of FIG. 5, the first electrode 141 is a (−) pole. , The second electrode 142 represents a positive electrode.

The first electrode 141 and the second electrode 142 can be formed using a metal material having good electrical and thermal conductivity. In an embodiment of the present invention, the first electrode 141 and the second electrode 142 are formed using silver (Ag), but the material of the electrodes is not limited thereto.

Next, the LED chip 900 is formed on the first recess 121, specifically, formed on the first electrode 141 or the second electrode 142 formed on the upper surface insulating layer 131. do. In an embodiment of the present invention, the LED chip 900 is formed on the second electrode 142.

The LED chip 900 is connected to the first electrode 141 through the first bonding line 801 and is connected to the second electrode 142 through the second bonding line 802. As described above, the LED chip 900 is supplied with power through the first electrode 141 and the second electrode 142 to emit light. In one embodiment of the present invention, the LED chip 900 is wire-bonded with the first electrode 141 and the second electrode 142, but the LED chip 900 and the first electrode 141 and the second electrode 142 There is no limitation in the way of bonding with.

The mold 150 includes the LED chip 900 formed on the first recess 121 to seal the first recess 121 as a whole. Since the mold 150 covers and seals the LED chip 900, the first bonding line 801, and the second bonding line 802, the LED chip 900, the first bonding line 801, and the second bonding line are sealed. It protects the 802 from the external environment and at the same time serves as a lens for collecting the emitted light. In an embodiment of the present invention, the mold 150 may use an epoxy resin, which is usually a kind of plastic, but is not limited thereto.

In particular, in one embodiment of the present invention, the mold 150 preferably includes a phosphorescence material. Phosphorescent material is a substance having a phosphorescent effect, and electrons in the phosphorescent material do not go directly to the ground state in an excited state, but lose energy through a metastable state in the middle, and thus the emission duration can be increased compared to fluorescence.

As such, the LED package 10 according to an embodiment of the present invention can efficiently dissipate heat generated when the LED chip 900 emits light, which will be described in detail below.

High heat is generated when the LED chip 900 emits light, and the generated heat is first transmitted to the second electrode 142 which is in direct contact with the LED chip 900 and through the second bonding line 802. Of course, although not directly in contact with the LED chip 900, heat is also transferred to the first electrode 141 that supplies power to the LED chip 900 through the first bonding line 801.

Since the first electrode 141 and the second electrode 142 use a metal material having good thermal conductivity, the generated heat flows through the first electrode 141 and the second electrode 142. In particular, the first electrode 141 and the second electrode 142 cover the upper and lower surfaces of the base substrate 100 as a whole, and the first electrode (through the first via hole 191 and the second via hole 192). 141 is integrally formed, and the second electrode 142 is integrally formed, so that heat conduction occurs quickly and effectively.

In addition, since the base substrate 100 formed of silicon is used, the heat transferred to the first electrode 141 and the second electrode 142 formed on the upper surface insulating layer 131 through the silicon is quickly transferred to the base substrate 100. To the bottom of the

Next, heat transferred toward the lower side of the base substrate 100 is radiated to the air through the second depression 122. Since the second recess 122 is generally formed as an empty space, the second recess 122 absorbs heat drawn by the first electrode 141 and the second electrode 142. In some cases, in order to more effectively achieve heat dissipation of the LED chip 900, it is also possible to form a separate heat dissipation mechanism or heat dissipation material in the second recess 122.

2 is a cross-sectional view illustrating an LED package according to another embodiment of the present invention. As shown in FIG. 2, the LED package 20 according to another embodiment of the present invention includes a base substrate 100, an upper insulating layer 131, a lower insulating layer 132, and a first electrode 141. , A second electrode 142, an LED chip 900, and a mold 150. All of these elements have been described in the description of one embodiment of the present invention, and thus redundant descriptions are omitted. However, since there is a difference between the first recessed part 121 and the second recessed part 122 formed in the base substrate 100, the present invention will be described in detail.

The first recess 121 is formed on the upper surface of the base substrate 100, and the second recess 122 is formed on the lower surface of the base substrate 100. Hereinafter, a method of forming the first recessed part 121 and the second recessed part 122 will be described with reference to FIG. 3.

3 is a cross-sectional view illustrating a method of forming a depression in various embodiments of the present invention (one embodiment and another embodiment). Here, the method of forming the depressions in another embodiment of the present invention will be described with reference to FIG. 3 (b).

The first recess 121 is formed by etching the photoresist 501 on the upper surface of the base substrate 100. In particular, another embodiment of the present invention uses isotropic etching. Isotropic etching means that the amount etched in the depth direction and the amount etched in the width direction are substantially the same. Accordingly, the first recess 121 is formed after the etching is finished, beginning with forming the first recess 1121 at the start of etching. The first depressions 121 formed by the isotropic etching may have a shape of a hemisphere, that is, a shape formed by dividing one sphere into two parts, or a shape of a semi-ellipse, that is, cut by dividing one ellipse into two parts. It may have a shape. Description of the shape of the first recess 121 described above is merely illustrative, it is not limited thereto.

Since the formation of the second depressions 122 is substantially the same as the formation of the first depressions 121, redundant description thereof will be omitted.

The first recess 121 and the second recess 122 may be formed with a time difference or may be simultaneously formed.

Hereinafter, the formation of the LED package array will be described with reference to FIG. 4.

4 is a view for explaining the appearance of the LED package array using the LED package according to an embodiment of the present invention.

As shown in FIG. 4, the LED package 10 may form an array, that is, the semiconductor wafer 300 may be processed to form an array of the LED packages 10. Here, the semiconductor wafer 300 is preferably a silicon wafer, but does not mean that the material constituting the semiconductor wafer 300 is limited to silicon.

The LED package array according to an embodiment of the present invention uses a wafer level package. That is, the wafer is etched and the upper insulating layer (see 131 of FIG. 1), the lower insulating layer (see 132 of FIG. 1), the first electrode (see 141 of FIG. 1), and the second electrode (see 142 of FIG. 1). ) Is laminated to form the LED package 10. In this way, a large amount of the LED package 10 can be simultaneously formed for a portion or the entire region of the wafer.

The LED package array according to an embodiment of the present invention also includes a structure in which the LED package is surface mounted on a printed circuit board, which will be described below with reference to FIGS. 5 and 6.

5 is a cross-sectional view illustrating a surface-mounted LED package according to an embodiment of the present invention on a printed circuit board. 6 is a cross-sectional view illustrating a surface-mounted LED package according to another embodiment of the present invention on a printed circuit board.

Referring to FIG. 5, the LED package 10 according to the exemplary embodiment of the present invention is electrically connected to the substrate electrodes 601 and 602 formed on the printed circuit board 600. The substrate electrodes 601 and 602 have opposite polarities. In FIG. 5, the substrate electrode 601 is formed as a negative electrode, and the substrate electrode 602 is formed as a positive electrode. Each of the substrate electrodes 601 and 602 is electrically connected to the first electrode 141 and the second electrode 142 of the LED package 10, and power is supplied to the LED chip 900.

Referring to FIG. 6, the LED package 20 according to another embodiment of the present invention is electrically connected to the substrate electrodes 601 and 602 formed on the printed circuit board 600. The substrate electrodes 601 and 602 have opposite polarities. In FIG. 6, the substrate electrode 601 is formed as a negative electrode, and the substrate electrode 602 is formed as a positive electrode. Each of the substrate electrodes 601 and 602 is electrically connected to the first electrode 141 and the second electrode 142 of the LED package 10, and power is supplied to the LED chip 900.

The specific method of surface-mounting the LED package 10 on a printed circuit board can use any known technique freely, and it will be obvious to those skilled in the art, so detailed description thereof will be omitted.

Hereinafter, a method of manufacturing an LED package according to various embodiments of the present disclosure will be described in detail with reference to FIGS. 7 to 10.

7 is a flowchart illustrating a method of manufacturing an LED package according to an embodiment of the present invention. 8 is a view for explaining a process of forming a depression of the LED package according to an embodiment of the present invention. 9 and 10 are views for explaining a process of forming the first and second electrodes of the LED package according to an embodiment of the present invention.

As shown in Figure 7, the LED package manufacturing method, the depression forming step (S100), insulating layer forming step (S200), conductive layer forming step (S300), electrode forming step (S400) and LED chip encapsulation step ( S500).

The depression forming step S100 is a step of forming the first depression 121 on the upper surface of the base substrate 100 and forming the second depression 122 on the lower surface of the base substrate 100. Depression forming step (S100) will be described in detail with reference to FIG.

First, as shown in FIG. 8A, upper and lower insulating layers 131 and 132 are formed on upper and lower surfaces of the base substrate 100, respectively. The base substrate 100 is preferably a silicon substrate as described above, and a silicon wafer may be used to fabricate the LED package array. However, the material of the base substrate 100 is not limited to silicon alone. In example embodiments, the upper insulating layer 131 and the lower insulating layer 132 may deposit silicon dioxide (SiO 2).

Subsequently, as illustrated in FIG. 8B, the upper and lower surfaces of the upper insulating layer 131 are insulated except for portions to be etched to form the first recess 121 and the second recess 122, which will be described later. A photoresist is formed under the layer 132.

Subsequently, as shown in FIG. 8C, when the etching is performed, the upper surface insulating layer 131 and the lower surface insulating layer 132 of the portion where the photoresist is not formed are etched. Next, as shown in FIG. 8 (d), the base substrate 100 is etched by continuous etching to form the first recess 121 and the second recess 122.

In FIG. 8 (d), although the first recess 121 and the second recess 122 are formed by anisotropic etching as described in the exemplary embodiment of the present invention, the isotropic etching is performed to determine the present invention. It is also possible to form the first recessed portion 121 and the second recessed portion 122 having the same shape as described in another embodiment. Here, the first recess 121 and the second recess 122 may be formed at positions corresponding to each other in a direction perpendicular to each other with the base substrate 100 interposed therebetween.

Next, the insulating layer forming step S200, the conductive layer forming step S300, the electrode forming step S400, and the LED chip encapsulating step S500 will be described with reference to FIGS. 9 and 10.

As shown in FIG. 9 (a), the insulating layer forming step (S200) is a step of forming an upper insulating layer 131 and a lower insulating layer 132 on the upper and lower surfaces of the base substrate 100. to be.

By etching, the insulating layer is formed on the upper and lower surfaces of the base substrate 100 on which the first recess 121 and the second recess 122 are formed. That is, as shown in FIG. 8D, the photoresist 501 and 502 and the insulating layers 131 and 132 remaining after the first recess 121 and the second recess 122 are formed are removed. Next, the upper and lower insulating layers 131 and 132 are newly deposited on the entire upper and lower surfaces of the base substrate 100. The upper surface insulating layer 131 and the lower surface insulating layer 132 may be formed of silicon dioxide.

Subsequently, the conductive layer forming step (S300) is a step of forming a conductive layer on the upper surface insulating layer 131 and the lower surface insulating layer 132 described above. The material of the conductive layers 1141 and 1142 is not particularly limited, but silver (Ag) having excellent thermal conductivity is preferably used.

Subsequently, the electrode forming step S400 is a step of forming the above-described conductive layer as the first electrode 141 and the second electrode 142. As shown in FIG. 9B, the upper surface insulating layer 131 and the conductive layer 1141 are formed on the upper surface of the base substrate 100, and the lower surface insulation is formed on the lower surface of the base substrate 100. Layer 132 and conductive layer 1142 are formed. In order to form these conductive layers 1141 and 1142 as the first electrode 141 and the second electrode 142, as shown in FIG. 9C, the photoresist 501 and 502 is formed as the conductive layers 1141 and 1142. To form).

Subsequently, as shown in FIG. 9D, a portion of the photoresist 502, a portion of the conductive layer 1142, a portion of the lower surface insulating layer 132, a portion of the base substrate 100, and an upper surface insulation are shown. A portion of the layer 131 is etched to form two via holes, namely a first via hole 191 and a second via hole 192.

Subsequently, as shown in FIG. 10E, the first via hole 191 and the second via hole 192 are filled with a metal material to electrically connect the conductive layers formed on the upper and lower portions of the base substrate 100. To help. The material filled in the first via hole 191 and the second via hole 192 is not limited, but is preferably formed of silver (Ag) having excellent thermal conductivity. A method of filling silver (Ag) in the first via hole 191 and the second via hole 192 may be freely selected by those skilled in the art.

Subsequently, as shown in FIG. 10F, the predetermined region 181 of the conductive layer 1141 formed on the upper surface insulating layer 131 is etched so that the conductive layer 1141 is not physically connected. Form an area. At the same time or in time difference, the conductive layer 1142 is not physically connected by removing the photoresist 502 and the conductive layer 1142 formed between the first via hole 191 and the first via hole 192. A non-region 182 is formed. In this manner, the first electrode 141 and the second electrode 142 which are physically separated from each other and are not energized with each other are formed.

Subsequently, the photoresists 501 and 502 are removed as shown in FIG. 10 (g). Next, as shown in FIG. 10 (h), the LED chip 900 is attached to the upper portion of the second electrode 142, and the first bonding line 801 is connected to the first electrode 141, and the second The bonding line 802 is connected to the second electrode 142. Here, the LED chip 900 is attached to the upper portion of the second electrode 142, but it is also possible to attach the LED chip 900 to the upper portion of the first electrode 141, or the predetermined region 181 described above is It is also possible to accommodate the LED chip 900 inside the predetermined region 181 by being formed wide enough to accommodate the LED chip 900.

Subsequently, the first bonding line 801, the second bonding line 802, and the LED chip 900 may be sealed with the mold 150 to protect the external environment from the external environment to form the LED package 10. If necessary, the LED package 10 manufactured as described above may be surface-mounted on a printed circuit board, and the method will be described with reference to the description of the LED package 10 and the description thereof will not be repeated. .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: Base substrate
121: first depression
122: second depression
131: top insulating layer
132: bottom insulating layer
141: first electrode
142: second electrode
150: mold
191: first via hole
192: second via hole
801: first bonding line
802: second bonding line
900: LED

Claims (5)

A base substrate having a first recessed portion formed on an upper surface thereof and a second recessed portion formed on a lower surface thereof;
An upper insulating layer formed on an upper surface of the base substrate;
A bottom insulating layer formed on the bottom surface of the base substrate;
First and second electrodes penetrating the base substrate and formed on the upper and lower insulating layers;
An LED chip electrically connected to the first electrode and the second electrode and formed in the first recessed portion; And
LED package including a mold for sealing the first depression. The method of claim 1,
The first recessed portion and the second recessed portion are formed at corresponding positions in the vertical direction, and the first electrode and the second electrode pass through the base substrate between the first recessed portion and the second recessed portion, respectively. LED package. The method of claim 1,
Wherein the mold comprises a phosphor. 4. The method according to any one of claims 1 to 3,
The base substrate is a silicon substrate LED package. A depression forming step of forming a first depression on an upper surface of the base substrate and forming a second depression on the lower surface of the base substrate;
An insulating layer forming step of forming an upper insulating layer and a lower insulating layer on each of an upper surface of the base substrate and a lower surface of the base substrate;
A conductive layer forming step of forming a conductive layer on the upper insulating layer and the lower insulating layer;
An electrode forming step of forming the conductive layer as a first electrode and a second electrode; And
The LED package manufacturing method comprising the step of forming an LED chip in the first recessed portion and sealing the first recessed portion with a mold.

Images