KR101341292B1 - Memory cells, and methods of forming memory cells - Google Patents

Abstract

Some embodiments include memory cells that include floats and diodes. The diodes may be gated diodes having portions doped with the same conductivity type as the floats, and these portions of the gated diodes may be electrically connected to the floats. The floats may be adjacent channel regions and are spaced apart from the channel regions by the dielectric structure. The dielectric structure of the memory cell may have a first portion between the float and the diode, and may have a second portion between the float and the channel region. The first portion may be more leaky to the charge carriers than the second portion. The diodes may be formed of a semiconductor material different from the semiconductor material in which the channel regions are inside. Floating bodies may have bulbous lower regions. Some embodiments include methods of masking memory cells.

Description

MEMORY CELLS, AND METHODS OF FORMING MEMORY CELLS}

Memory cells and methods of forming memory cells.

Dynamic random access memory (DRAM) is commonly used as quick access memory of computer systems. DRAMs have commonly used unit cells that include a capacitor in combination with a transistor. In these conventional designs, the charge state of the capacitor is used to store and sense the memory bit.

Higher performance, lower cost, increased miniaturization of components and greater packaging density of integrated circuits are ongoing objectives of the computer industry. To achieve miniaturization, capacitor / transistor combinations of conventional DRAM memory cells are constantly being redesigned to achieve an increasingly higher degree of integration. However, it has become increasingly difficult to reduce the dimensions of DRAM capacitors while still maintaining sufficient capacitance to reliably store memory bits.

Difficulties in reducing the dimensions of DRAM capacitors have led to the development of so-called capacitor-less memory devices. These memory devices store charge on components rather than capacitors. For example, non-capacitor memory devices may use a float to store memory bits (the term "floating" means that this body is not directly resistively connected to a source of potential or in other words the body is surrounded by electrically insulating material). To be used).

Although non-capacitor memory devices ultimately present some potential to replace conventional DRAM memory cells, there are currently a number of difficulties in attempting to use non-capacitor memory devices. One of the difficulties is that non-capacitor memory devices tend to leak much more than conventional capacitor / transistor memory cells, which means that non-capacitor memory devices need to be refreshed at a higher rate than conventional memory cells. . Higher refresh rates result in higher power consumption, which can discharge the batteries and / or cause undesirable heating. Another difficulty associated with non-capacitor memory devices is that the charge storage components of these devices tend to be more difficult to charge than capacitors in conventional DRAM, which is due to excessive power consumption, extreme reliability issues, and / or inadequate device performance. May result.

It is desirable to develop improved non-capacitor memory cells.

1 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of an example embodiment.
2 and 3 are schematic cross-sectional views of portions of semiconductor configurations showing exemplary embodiment structures that may alternatively be used in the structure shown in FIG. 1.
4 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
5 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
6 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
7 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
8 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
9 is a schematic cross-sectional view of a portion of a semiconductor configuration illustrating a memory cell of another example embodiment.
10-15 are schematic cross-sectional views of a portion of a semiconductor configuration illustrating an example process that may be used to form the memory cell of the example embodiment of FIG. 9.

New non-capacitor memory devices are described herein. Such devices may have various improvements over prior art floating non-capacitor memory devices. For example, the new non-capacitor memory devices described herein may have improved retention time and / or other data storage characteristics compared to prior art non-capacitor memory devices. Additionally or alternatively, the new non-capacitor memory devices described herein may have improved programming characteristics compared to prior art non-capacitor memory devices. Additionally or alternatively, the new non-capacitor memory devices described herein can have improved response time and / or reliability compared to prior art non-capacitor memory devices.

1 shows a portion of a semiconductor configuration 3 and illustrates a memory cell 5 of an exemplary embodiment. The memory cell 5 comprises a non-capacitor storage device 6 and a programming device 8. The programming device is configured to be used for programming the non-capacitor storage device 6.

The devices 6 and 8 are supported by the semiconductor base 12. The semiconductor base may comprise, as an example, single crystal silicon lightly doped with a suitable dopant. In the embodiment shown, base 12 is predominantly doped with a p-type dopant and is doped at a "p-" concentration.

"p-" concentration is a relative term. Specifically, the p-type dopant concentration of the semiconductor material mainly doped with the p-type dopant may be expressed as "p-", "p" or "p +" in order of increasing dopant concentration. The specific amount of dopant corresponding to the "p-", "p" and "p +" concentration levels may vary depending on the application. In an exemplary application, the "p-" level may correspond to a concentration of about 1x10 ¹⁸ atoms / cm ³ or less, and the "p" level may be a dopant concentration of about 1x10 ¹⁸ atoms / cm ³ to about 1x10 ²⁰ atoms / cm ³ And a “p +” level may correspond to a dopant concentration of at least about 1 × ^{10 20} atoms / cm ³ . Similarly, when the semiconductor material is mainly doped with an n-type dopant, the n-type dopant concentration may be expressed as "n-", "n" or "n +" in order of increasing dopant concentration. The specific amount of dopant corresponding to the "n-", "n" and "n +" concentration levels is, for example, at a concentration of about 1x10 ¹⁸ atoms / cm ³ or less for the "n-" level, at an "n" level. A dopant concentration of about 1 × 10 ¹⁸ atoms / cm ³ to about 1 × 10 ²² atoms / cm ³ , and a concentration greater than about 1 × 10 ²² atoms / cm ³ with respect to the “n +” level.

Base 12 may be considered a semiconductor substrate, wherein the term “semiconductor substrate” refers to a semiconductive wafer (alone or in assemblies comprising other materials thereon) and semiconducting material layers (alone or otherwise). By means of any configuration including semiconducting materials, including but not limited to bulk semiconducting materials, such as assemblies comprising materials. In some embodiments, the base 12 may correspond to a single crystal silicon wafer, and thus the semiconductor material of the base 12 may be composed of single crystal silicon, or may be configured as the main component. In other embodiments, the semiconductor material of the base 12 includes, consists of, or consists of other known or undeveloped semiconductor materials such as, for example, germanium, gallium arsenide, and the like. Can be configured.

The non-capacitor storage device 6 includes a float 14 over the base 12 and a dielectric structure 16 between the float and the base.

The float may comprise a doped semiconductor material. For example, the float can include silicon and / or germanium and can be doped with either p-type or n-type. In the illustrated embodiment, the float is p-type doped and doped to a "p +" concentration. In some embodiments, the float may be p-type doped germanium due to the advantage of the higher boron activity of germanium over other semiconductor materials.

The float is illustrated as a planar body formed over the base 12. In other embodiments, the float may be at least partially recessed into the base 12, similar to the structures described below with reference to FIGS. 4-9.

Dielectric structure 16 may comprise any suitable composition or combination of compositions, and in some embodiments may comprise silicon dioxide, consist primarily of silicon dioxide, or consist of silicon dioxide. . Dielectric structure 16 may comprise any suitable thickness, and in some embodiments, may have a thickness of about 50 mm 3 or less.

The non-capacitor storage device 6 includes conductive doped regions 18 and 20 extending into the semiconductor base 12, which in the illustrated embodiment are mainly doped n with a " n + " concentration. Brother. These regions 18 and 20 may be referred to as source / drain regions in that these regions may correspond to the source and drain of the transistor device. In some embodiments, one or both of regions 18 and 20 may be referred to as an electrical node.

Channel region 22 extends between conductive doped regions 18 and 20 and is directly below float 14. The channel region may be doped with a threshold voltage implant.

The sense gate (or control gate) 24 is above the float 14 and is spaced apart from the float by the dielectric structure 26. The dielectric structures 16 and 26 may in some embodiments be referred to as first and second dielectric structures, respectively, to distinguish the dielectric structures from each other. In some embodiments, float 14 may correspond to a floating gate, dielectric structure 16 may be referred to as a gate dielectric, and dielectric structure 26 may be an intergate dielectric. It may be referred to as.

The sense gate is electrically conductive and may include any suitable composition or combination of compositions. For example, the sensing gate can be a variety of metals (eg, platinum, titanium, tungsten, etc.), metal containing compositions (eg, metal nitrides, metal silicides, etc.) and conductive doped semiconductor materials (eg, For example, conductive doped silicon, conductive doped germanium, and the like.

Dielectric structure 26 may comprise any suitable composition or combination of compositions, for example, silicon dioxide and various high k materials (the term “high-k” is less than the dielectric constant of silicon oxide. High dielectric constant, specifically, indicating a dielectric constant greater than 3.9).

The sense gate along with the source / drain regions 18 and 20 may be considered to be a sense circuit adjacent to the float 14 and may be configured to detect the state of charge of the float. The term "charge state" refers to the concentration of charge carriers in the float. In the illustrated embodiment, the float is p-type doped, so the term "charge state" refers to the concentration of holes in the float. In embodiments in which the float is n-type doped (not shown), the term “charge state” refers to the concentration of electrons in the float.

The sense gate may be part of an access line (such as a wordline) extending into the ground and out of the ground relative to the cross section of FIG. 1. The state of charge of the float 14 will change the electrical coupling between the access line and the channel region 22. Specifically, when the float 14 is in a suitable state of charge, the electrical characteristics (eg, current or voltage) of the access line may be such that the channel region to electrically couple the source / drain regions 18 and 20 to each other. It is possible to introduce a current flow within, and when the float 14 is in a different state of charge, the electrical properties of the access line do not induce current in the channel region.

The state of charge of the float is controlled by the programming device 8. The programming device includes doped regions 28, 30, and 32 in the semiconductor base 12, a gate 34 over the base 12, and a dielectric structure 36 between the gate 34 and the base 12. do.

Region 28 is mainly doped with p-type (and specifically doped with "p +" concentration), and regions 30 and 32 are mainly doped with n-type (and specifically with "n" concentration and " each doped to a concentration of n + ").

Regions 28 and 30 together form a diode, and gate 34 may control the flow of carriers (ie holes or electrons) through this diode. In particular, the voltage (or current) of gate 34 may induce an electric field across the diode that controls the flow of carriers through the diode. Diodes having carrier flows controlled by adjacent gates therein may be referred to as "gated diodes". Regions 28 and 30 may be referred to as first and second sections of the gate diode, respectively. Region 28 has the same conductivity type (p-type in the illustrated embodiment) as floating body 14 of non-capacitor storage device 6, while region 30 has a conductivity opposite to that of floating body. Type (n type in the illustrated embodiment).

Gate 34 includes an electrically conductive material and may include any suitable composition or combination of adjustments. For example, gate 34 may comprise various metals (eg, platinum, titanium, tungsten, etc.), metal containing compositions (eg, metal nitrides, metal silicides, etc.) and conductive doped semiconductor materials ( For example, conductive doped silicon, conductive doped germanium, and the like. Gate 34 may be referred to as a programming gate in that it is used (described below) to program non-capacitor storage 6. Gate 24 may be part of a conductive line extending into the ground and out of the ground relative to the cross section of FIG. 1.

The dielectric structure 36 may comprise any suitable composition or combination of compositions, and in some embodiments includes silicon dioxide, consists primarily of silicon dioxide, or consists of silicon dioxide. The dielectric structure 36 may be of the same composition as the dielectric structure 16 in some embodiments, and may be of a different composition than the dielectric structure 16 in other embodiments.

In the embodiment shown, the storage device 6 and the programming device 8 are laterally spaced apart from each other, and the isolation area 38 is provided in the space between the storage device and the programming device. The isolation region includes an electrically insulating material 39 formed in the opening extending into the semiconductor base 12. The electrically insulating material may comprise any suitable composition or combination of compositions, for example, may comprise one or both of silicon dioxide and silicon nitride. The isolation region may correspond to a conventional shallow trench isolation region. In the embodiment shown, insulating material 39 extends to a level above the top surface of base 12. In other embodiments, the top surface of material 39 may extend in co-space with the top surface of base 12 or may be indented below the top surface of base 12.

The region 28 of the gated diode of the programming device 8 is electrically connected to the float 14 of the non-capacitor storage device 6 via an electrical connection 40. Such electrical connections may use any suitable configuration, for example various metals (eg, platinum, titanium, tungsten, etc.), metal containing compositions (eg, metal nitrides, metal silicides, etc.) And wires made of one or more of conductive doped semiconductor materials (eg, conductive doped silicon, conductive doped germanium, and the like).

In operation, regions 28 and 30 comprise gated pn diodes used to change the memory state of storage device 6. The storage device can be considered to have two memory states. One of these states corresponds to the concentration of high holes retained by the float 14, and the other of the states corresponds to the concentration of low holes retained by the float. The terms "high concentration of holes" and "low concentration of holes" are not absolute and are relative to each other. Thus, the storage device is in a memory state corresponding to “high concentration of holes” on the float when there are more holes retained on the float than the memory state corresponding to “low concentration of holes”. In some embodiments, an input current or voltage is provided to the sense gate 24 and the state of charge of the float is a deviation of the drive current through the storage device 6 depending on whether the float is in a charged or non-charged state. Is detected by.

The storage device 6 is moved from one of the memory states to another through the flow of holes between the float 14 and the region 28 of the pn diode. When holes are flowed onto the float, the storage device can be converted to a memory state that includes a high concentration of holes held by the float, and when holes are flowed from the float, the storage device is moved by the float. It can be converted to a memory state that includes the concentration of low holes retained.

In some embodiments, “n” region 30 may be considered to be used to isolate “p +” region 28 from the bulk material of base 12. In such embodiments, it may be desirable for region 30 to be very thick, and preferably include a thickness of about one half of the depth of isolation region 38. For example, if the isolation region 38 extends into the substrate 12 to a depth of about 2000 microns, the region 30 may have a thickness of about 1000 microns.

The orientation of regions 28 and 30 of the pn diode can be customized for specific applications to enable large scale integration of the memory cell 5. Base 12 is shown having an upper surface 13. The horizontal direction 15 can be defined as extending along this top surface. At this time, the vertical direction 17 may be defined as extending perpendicular to the horizontal direction 15. In the embodiment shown, the region 30 of the pn diode extends both vertically and horizontally relative to the region 28. In other embodiments, region 30 may extend primarily horizontally relative to region 28, or may extend mainly vertically relative to region 28. For example, programming device 8 may be formed over an insulating material as part of a silicon on insulator (SOI) configuration. In such applications, the semiconductor material of base 12 is a layer over the insulator, which may be used to electrically isolate the bottom of region 28. Thus, the " p + " region 28 and the " n " region 30 of the pn diode may be horizontally offset relative to each other and not vertically offset relative to each other.

In some embodiments, the volume of the diode is designed to achieve the desired amount of electron / hole pairs in the diode. A larger number of electron / hole pairs in the gated diode of FIG. 1 may result in a lower programming voltage for providing charge to the float that may be desirable in some embodiments.

The embodiment of FIG. 1 shows a float 14 that is mainly doped with an n-type dopant. In other embodiments, the float may be doped predominantly with an n-type dopant, and the dopant types in all of the regions 18, 20, 28, 30, and 32 may be opposite to the embodiment shown, The background of the doping of the base 12 may be "n-" rather than "p-" of the illustrated embodiment (or an n-well may be formed in the base to create an n-type doped region of the base). .

Although not shown, one typically surrounds the exposed surfaces of the devices 6 and 8 to electrically insulate such devices from other circuits (not shown) that may be adjacent to the devices in the integrated circuit configuration. The above insulating materials exist.

The configuration of FIG. 1 is an exemplary embodiment in which a gated diode can be used to program a float in a non-capacitor memory cell. The use of gated diodes can overcome various problems associated with prior art methods of programming non-capacitor memory cells. For example, gated diodes may enable tighter control of the flow of carriers into and out of the float than can be achieved in prior art methods. In addition, prior art methods for programming floats frequently use impact ionization to form holes in the floating p-type region, which may cause leakage mechanisms (eg, negatively affecting the retention of carriers on the float). Hole induced drain leakage), which can be a problem. The use of the gated diode of FIG. 1 is preferred by allowing the float to be programmed by mechanisms other than impact ionization. In addition, the use of the gated diode of FIG. 1 allows the float to be programmed at lower operating voltages than is used in prior art methods.

The sense gate 24 of the configuration of FIG. 1 is a planar gate provided over a planar float. In some embodiments, it may be desirable for the sense gate to be partially wound around the float to improve coupling between the sense gate and the float. 2 and 3 illustrate alternative embodiments of the storage device 6 of FIG. 1, which have sense gates partially wound around the floating gate. The same reference numerals are used to describe the memory cells of FIG. 1 to describe FIGS. 2 and 3.

The floats 14 of FIGS. 2 and 3 are shown to include top surfaces 41 and side surfaces 43 extending downward from the top surfaces. The dielectric structure 26 extends along and in direct contact with the top surfaces and side surfaces. The sensing gate 24 of FIG. 2 is shown extending along the top surface 41 of the float 14 and along the side surfaces 43 of the float as a whole. In contrast, the sense gate 24 of FIG. 3 is shown to extend along the top surface 41 of the float, but only partially along the side surface of the float.

The embodiment of Figure 1 uses a gated diode during the programming of a memory cell. 4-9 illustrate embodiments in which non-gate diodes are used during programming of memory cells. Where appropriate, the same reference numerals as used to describe the embodiment of FIG. 1 are used to describe FIGS. 4 to 9.

Referring to FIG. 4, a portion of a semiconductor configuration 48 is illustrated, which portion includes a semiconductor base 12 supporting a memory cell 50. The memory cell includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 54 that separates the float from the semiconductor base and the diode. The memory cell further includes a sense gate 24 over the float and a dielectric structure 26 between the float and the sense gate.

Semiconductor base 12 and float 14 may include any of the materials described above with respect to base 12 and float 14 in FIG. 1. In some embodiments, semiconductor base 12 and float 14 each comprise a semiconductor material (eg, silicon, germanium, etc.). In such embodiments, to help distinguish the base and floating semiconductor materials from each other, the semiconductor material of base 12 may be referred to as a first semiconductor material, and the semiconductor material of float 14 may be referred to as a second material. It may be referred to as a semiconductor material. The floating semiconductor material may in some embodiments be the same compositions as the base semiconductor material, and in other embodiments may be compositionally different from the base semiconductor material.

Diode 52 has a first diode region 28 doped predominantly of the same conductivity type as the float 14 (p type in the illustrated embodiment), and a conductivity type opposite to the first diode region (in the illustrated embodiment). n-type) and a second diode region 30 which is mainly doped. In some embodiments, the conductivity type of the first diode region and the float may be referred to as the first conductivity type, and the conductivity type of the second diode region may be referred to as the second conductivity type. Although, in the illustrated embodiment, the first conductivity type is p type and the second conductivity type is n type, in other embodiments, the conductivity type of the float and the first diode region is n type, and the second diode The conductivity type of the region may be p-type. However, memory cells with p-type floats may be easier to charge and have less leakage than memory cells with n-type floats, and thus would be more suitable for many applications than memory cells with n-type floats. Can be.

Memory cell 50 has n-type doped region 46 in base 12 on the opposite side of float 14 from n-type doped second diode region 30. In some embodiments, n-type doped regions 30 and 56 are used as source / drain regions (in addition to using region 30 as the second region of diode 52). Channel 22 extends within base 12 and between n-type doped regions 30 and 56. Indentation of the float 14 in the base 12 allows longer channels to be formed across the area of the semiconductor asset than is formed along the planar float (eg, float in FIG. 1). The use of longer channels can avoid "short channel effects" which is problematic in some embodiments.

The dielectric structure 54 may include any of the compositions described above with respect to the dielectric structure 16 of FIG. 1. The dielectric structure 54 may be considered to include two portions, wherein the first portion 55 is between the float 14 and the channel region 22, and the second portion 57 is suspended. And between the first region 28 of the diode 52. The second portion 57 is more leaky with respect to the carriers than the first portion 55 and the stipple of the portion 57 to illustrate that the portion 57 of the dielectric structure 54 is different from the portion 55. (stippling) is used in FIG. 4.

The portion 57 may be treated such that the portion 57 is more leaky than the portion 55 or may be formed compositionally different from the portion 55. If portion 57 is to be treated, such treatment involves the use of ionizing radiation to create damage in portion 57 and / or one or more dopants (eg, phosphorus, boron) in portion 57 And the like).

The first diode region 28 is electrically connected to a circuit 58 configured to bias the diode 52 in either the forward or reverse direction. In operation, the float 14 is programmed by flowing holes on or floating holes from the float.

If it is desirable to flow the holes onto the float, these holes will flow from the first diode region 28, through the leaky portion 57 of the dielectric structure 54, and onto the float 14. Can be. The leaky portion 57 is so-called because it accumulates holes in the first region 28 of the diode that allows the holes to easily penetrate the leaky portion 57 and accumulate on the float 14. May have a "soft breakdown". However, once the concentration of the holes on the first region 28 decreases as the holes traverse through the leaky portion 57 to accumulate on the float, the “soft yield” of the portion 57 is calmed down so that the holes Can be trapped on the float. Thus, under some conditions, the leaky portion 57 allows holes to flow from the region 28 of the diode onto the float more easily than holes flow back from the float to the region 28 of the diode. It can function as a one-way valve. This may help retain charge on the float such that memory cell 50 can function with less frequent refresh than prior art non-capacitor memory devices.

When it is desirable to flow holes from the float to the outside, it is pulled into one or both of the regions 20 and 30 of the diode across the dielectric structure and / or the holes are drawn from the float 14 with the diode 52. Circuitry 58 may be used to induce sufficient electrostatic force to induce hard breakdown of the dielectric material of structure 54 to facilitate delivery to any of the adjacent materials of base 12.

Float 14 is shown partially indented into base 12 in the embodiment of FIG. 4 such that a portion of the float extends above base 12. In other embodiments, the float may cause the top surface of the float to extend in the same space as the top surface of the base 12 or to allow the top surface of the float to be indented to a level below the top surface of the base 12. Can be indented into the level.

Referring to FIG. 5, a portion of a semiconductor configuration 60 is illustrated, which portion includes a semiconductor base 12 supporting a memory cell 62. The memory cell includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 64 separating the float from the diode and the semiconductor base. Memory cell 62 further includes a dielectric structure 26 between the float and the sense gate, and a sense gate 24 over the float.

Diode 52 has a first diode region 28 doped predominantly of the same conductivity type as the float 14 (p type in the illustrated embodiment), and a conductivity type opposite to the first diode region (in the illustrated embodiment). n-type) and a second diode region 30 doped predominantly.

Memory cell 62 has n-type doped region 56 in base 12 on the opposite side of float 14 from n-type doped second diode region 30 as described above with respect to FIG. Have Channel 22 extends between n-type doped regions 30 and 56 and into base 12.

The dielectric structure 64 may include any of the compositions described above with respect to the dielectric structure 16 of FIG. 1. The dielectric structure 64 may be considered to include two portions, the first portion 65 being between the float 14 and the channel region 22, the second partial region 67 being a diode It is present between the first region 28 of 52 and the float. The second portion 67 is thinner than the first portion 65 such that the second portion is more leaky with respect to the carriers than the first portion.

The first diode region 28 is electrically connected to a circuit 58 configured to bias the diode 52 in either the forward or reverse direction. In operation, the float 14 is programmed by flowing holes onto the float or by flowing holes out from the float as described above with respect to the memory cell of FIG. 4. Thin portion 67 of dielectric structure 64 may function similarly to chemically modified portion 57 of dielectric structure 54 of FIG. 4 during programming of memory cell 62.

4 and 5 illustrate applications in which deformation of a portion of the dielectric structure adjacent to the region of the diode may be used to render this portion of the dielectric structure "leakage" relative to the remainder of the dielectric structure. The leaky portion of the dielectric structure can be used to improve the programming of non-capacitor memory cells. 4 illustrates an example embodiment where chemical modifications are used to increase the leakage of a portion of the dielectric structure, and FIG. 5 illustrates an example embodiment where structural modifications are used to increase the leakage of a portion of the dielectric structure. To illustrate. In other embodiments, chemical and structural modifications may be combined.

In some embodiments, the dielectric structure provided between the float and the channel region of the non-capacitor memory cell may include high k dielectric. 6 and 7 are similar to those of FIGS. 4 and 5, but illustrate specific applications for use with dielectric structures comprising high k materials.

Referring to FIG. 6, a portion of a semiconductor configuration 70 is illustrated, which portion includes a semiconductor base 12 supporting a memory cell 72. The memory cell includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 74 that separates the float from the semiconductor base and diode. Memory cell 72 further includes a sense gate 24 over the float and a dielectric structure 26 between the float and the sense gate.

Diode 52 has a first diode region 28 doped predominantly of the same conductivity type as the float 14 (p type in the illustrated embodiment) and a conductivity type opposite to the first diode region (the embodiment shown) In the n-type).

Memory cell 72 has n-type doped region 56 in base 12 on the opposite side of float 14 from n-type doped second diode region 30 as described above with respect to FIG. 4. . Channel 22 extends between n-type doped regions 30 and 56 and within base 12.

Dielectric structure 74 is similar to dielectric structure 54 of FIG. 4, but includes two separate layers. Specifically, the dielectric structure 74 includes a layer 76 along the base 12 and another layer 78 along the float 14.

Layer 76 may comprise silicon dioxide, consist primarily of silicon dioxide, or consist of silicon dioxide, and in some embodiments is dielectric material within and after openings are formed into the base. Prior to providing layer 78 and float 14, it may correspond to a so-called "native oxide" formed along the exposed surface of silicon-containing base 12. If layer 76 corresponds to a "native oxide", the layer may be composed of silicon dioxide and may have a thickness of about 10 GPa or less (in some applications, about 5 GPa or less). In some embodiments, layer 76 may be thin enough to enable direct tunneling of holes and / or electrons through the layer. Carriers (holes and / or electrons) tunneling into the dielectric layer change the surface potential, which can be used while sensing the state of charge of the non-capacitor memory cell.

Layer 78 may comprise a high k dielectric material (eg, zirconium oxide, hafnium oxide, aluminum oxide, and the like), or may consist of or consist of as a major component thereof. In some embodiments, layer 78 may be formed to a thickness at least three times thicker than the thickness of layer 76, for example, to a thickness of at least about 30 mm 3. Although dielectric structure 74 is shown to include two layers, in other embodiments, dielectric structure may include more than two layers. When dielectric structure 74 includes more than two layers, at least one of the layers may be silicon dioxide and at least one of the layers may be a high k dielectric.

Dielectric structure 74 includes two portions 75 and 77 similar to portions 55 and 57 of dielectric structure 54 of FIG. 4. However, in contrast to the dielectric structure of FIG. 4, the modified region 77 (shown at a point angle in FIG. 6) only includes a modification to one of the two layers of the dielectric structure 74 (specifically, high k layer corresponding to dielectric 78). In that the deformation of the region 77 includes the formation of damage within the dielectric structure 74, it may be advantageous that the damage region does not directly contact the semiconductor material of the diode 52 (otherwise, the semiconductor of the diode). The interface between the material and the damaged dielectric may be too leaky). Thus, the undeformed thin dielectric layer 76 may function as a barrier between the semiconductor material of the diode 52 and the strained region 77.

The damaged region may be formed during or after the deposition of such material, through chemical modification of the material of layer 78 and / or through carefully controlled ionization of the dielectric material of layer 78. May be specifically introduced into the high k dielectric layer 78. Although the damage region shown is limited to only one of the layers of the dielectric structure 74, in other embodiments, the damage region may extend through multiple layers of the dielectric structure. In addition, in embodiments where it is not a problem for the damaged area to be in direct contact with the semiconductor material of the diode 52, the damaged area may extend through all of the layers of the dielectric structure 74.

The first diode region 28 is electrically connected to a circuit 58 configured to bias the diode 52 in either the forward or reverse direction. In operation, the float 14 is programmed by flowing holes into or from the float as described above with respect to the memory cell of FIG. 4. The modified portion 77 of the dielectric structure 74 may function similar to the modified portion 57 of the dielectric structure 54 of FIG. 4 during programming of the memory cell 72.

Referring to FIG. 7, a portion of a semiconductor configuration 80 is illustrated, which portion includes a semiconductor base 12 supporting a memory cell 82. The memory cell includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 84 separating the float from the semiconductor base and the diode. The memory cell further includes a sense gate 24 over the float and a dielectric structure 26 between the float and the sense gate.

Dielectric structure 84 is similar to dielectric structure 64 of FIG. 5, but includes two separate layers. Specifically, the dielectric structure 84 includes a layer 86 along the base 12 and another layer 88 along the float 14. Layer 86 may comprise, consist of, or consist of silicon dioxide as a major component, and in some embodiments, after openings are formed into the base, and within the openings 14 And prior to providing the dielectric layer 88, may correspond to native oxide formed along the exposed surface of the silicon-containing base 12. Layer 88 may comprise a high k dielectric material (eg, zirconium oxide, hafnium oxide, aluminum oxide, etc.), or may be configured as the main component, or as such. In some embodiments, layer 88 may be formed to be at least three times thicker than the thickness of layer 86, for example, to a thickness of at least about 30 mm 3. Although dielectric structure 84 is shown to include two layers, in other embodiments, dielectric structure 84 may include more than two layers, at least one of the layers being silicon dioxide At least one of the layers is a high k dielectric.

Dielectric structure 84 includes two portions 85 and 87 similar to portions 65 and 67 of dielectric structure 64 of FIG. 5. However, in contrast to the dielectric structure 64 of FIG. 5, only one of the two layers of the dielectric structure 84 is thinned. Thinning less than all of the layers of dielectric structure 84 provides a parameter that allows the leakiness of dielectric structure 84 to be customized for particular applications.

Diode 52 has a first diode region 28 doped predominantly of the same conductivity type as that of float 14 (p type in the illustrated embodiment), and a conductivity type opposite to the first diode region (shown implementation An example includes a second diode region 30 doped predominantly n-type).

Memory cell 82 has n-type doped region 56 in base 12 on the opposite side of float 14 from n-type doped diode region 30 as described above with respect to FIG. 5. Channel 22 extends between n-type doped regions 30 and 56 and within base 12.

The first diode region 28 is electrically connected to a circuit 58 configured to bias the diode 52 in either the forward or reverse direction. In operation, the float 14 is programmed by flowing holes either on or off the float as described above with respect to the memory cell of FIG. 5.

In many applications, it may be desirable to customize the charge retention characteristics of non-capacitor memory cells. 8 shows a semiconductor configuration 90 including a memory cell 92 illustrating an embodiment for customizing the charge retention characteristics of a non-capacitor memory cell. Where appropriate, reference numerals similar to those used above to describe the configuration of FIG. 4 will be used to describe the configuration of FIG. 8.

The memory cell 92 includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 54 that separates the float from the semiconductor base and the diode. The memory cell further includes a sense gate 24 over the float and a dielectric structure 26 between the float and the sense gate. Diode 52 has a first diode region 28 doped predominantly of the same conductivity type as the floating body 14 (p type in the illustrated embodiment), and a conductivity type opposite to the first diode region (the embodiment shown). In the n-type). In addition, memory cell 92 includes n-type doped region 56 and n-type doped regions on opposite sides of floating body 14 from n-type doped second diode region 30 and in base 12. Have a channel 22 extending between the regions 30 and 56. Dielectric structure 54 of FIG. 8 includes first and second portions 55 and 57 described above with reference to FIG. 4. In addition, memory cell 92 includes circuitry 58 for programming memory cells.

The difference between the memory cell 92 of FIG. 8 and the memory cell 50 of FIG. 4 has the shape of the illustrated cross section of the wide bulbous region 93 under the narrow stem region 91. This shape initially creates an opening in the base 12 with a wide bulbous lower region and a narrow stem upper region, deposits the dielectric material of the structure 54 in this opening, and then floats to fill the opening. It can be formed by depositing the material of 14. Openings with broad bulbous lower regions and narrow stem upper regions can be formed using a combination of isotropic and anisotropic etchings, using a process similar to that described in Wang et al. (US Patent Publication 2006/0292787).

The volume of the float 14 can be customized by customizing the size and shape of the opening in which the float is formed, which may be characterized by the retention properties of the float (eg, the amount of charge retained by the float and / or Or the retention time of the charge on the float).

Although the particular float shape of FIG. 8 is illustrated in a memory cell with a dielectric structure 54 having a modified region of the type described above with reference to FIG. 4, in other embodiments, the float of FIG. The shape may be used in combination with any of the other configurations described in the present invention, for example, memory cell 5 of FIG. 1, memory cell 62 of FIG. 5, memory cell 72 of FIG. 6. And the memory cell 82 of FIG.

1 through 8 disclose memory cells in which a diode is formed of the same semiconductor material as used for the channel region. In other embodiments, the diode may be formed in a semiconductor material other than that commonly used for the channel region, which may provide additional control over the retention characteristics and / or programming characteristics of the non-capacitor memory cell.

9 shows a semiconductor configuration 100 including a memory cell 102 illustrating an embodiment having a diode formed in a semiconductor material different from the channel region of a non-capacitor memory cell. Where appropriate, reference numerals similar to those used above to describe the configuration of FIG. 4 are used to describe the configuration of FIG. 9.

The memory cell 102 includes a float 14 indented into the semiconductor base 12, a diode 52 adjacent to the float and a dielectric structure 54 separating the float from the diode 52 and the semiconductor base 12. It includes. The memory cell further includes a sense gate 24 over the float and a dielectric structure 26 between the float and the sense gate. In the embodiment of FIG. 4, only dielectric structure 26 extends over doped region 56. In contrast, in addition to dielectric structure 26 extending over doped region 56, dielectric structure 54 extending over doped region 56 is shown. This illustrates that in various embodiments either or both of the dielectric structures 26 and 54 can extend over the doped region 56.

The diode 52 is of the same conductivity type as the float 14 (p type in the illustrated embodiment) and is doped primarily with the first diode region 28 and the conductivity type opposite to the first diode region (in the illustrated embodiment). n-type) and a second diode region 30 doped predominantly. The memory cell 102 also has an n-type doped region 56 on the opposite side of the float 14 and in the base 12 from an n-type doped second diode region 30 and an n-type doped. Have a channel 22 extending between the regions 30 and 56. Dielectric structure 54 of FIG. 9 includes first and second portions 55 and 57 described above with reference to FIG. 4.

The difference between the memory cell 102 of FIG. 9 and the memory cell 50 of FIG. 4 is that a semiconductor material 104 is formed over the semiconductor base 12 of the embodiment of FIG. 9, and a diode is formed inside the semiconductor base 12. Rather, it is formed within the semiconductor material 104. In some embodiments, the semiconductor material of base 12 may be referred to as a first semiconductor material, and semiconductor material 104 may be referred to as a second semiconductor material different from the first semiconductor material, The semiconductor material of 14 may be referred to as a third semiconductor material, which may be the same as one of the first and second semiconductor materials or different from both the first and second semiconductor materials. In some embodiments, material 104 may be considered to form a diode section of the memory cell 102 configuration, and the semiconductor material of base 12 may be considered to form a channel region section of the memory cell. have.

The use of the second semiconductor material for the diode allows the band gap characteristics in the diode to be customized to achieve the desired performance parameters. For example, in the embodiments of FIGS. 1-8 where the diode is formed of the same semiconductor material as the channel region of the memory cell, both the diode and the channel region may be formed of silicon. The maximum band gap in silicon is about 1.1 eV (electron volts, at about 300K), which limits the programming voltage that can be applied to the diode. In contrast, when the diode is formed of silicon carbide, the band gap is increased above about 2.8 eV (at about 300K), which can extend the useful range of programming voltages that can be used. Thus, in some embodiments, the configuration 102 of FIG. 9 has a base 12 composed of silicon as the main component or composed of silicon, and a mixture of silicon and carbon (eg, Si _x C _y , eg, x and y are numbers greater than zero) and has a second semiconductor material 104 constructed as or composed of a major component. In addition, when a diode is formed in a semiconductor material containing two or more elements (eg, silicon and carbon), the band gap can be controlled by adjusting the proportions of the elements (eg, the amount of carbon present in the silicon carbide). By adjusting).

In the illustrated embodiment, the "p-" region 106 is provided in the material 104 under the diode 52 as a transition region between the "p-" background doped semiconductor material of the base 12 and the diode. This places the pn junction at the bottom of the diode 52 in the material 104 rather than at the interface of the material 104 and the base 12, which avoids problematic junction leakage, which can be done in other ways.

The sensing gate 24 of FIG. 9 is shown extending along the sidewalls and top of the float 14. In other embodiments, the sense gate may extend only along the top or only along the side.

Although the embodiment of FIG. 9 is illustrated with a dielectric structure 54 having a modified region of the type described above with reference to FIG. 4, in other applications, the embodiment of FIG. 9 may have other configurations described herein. It can be used in combination with any of the configuration, for example, memory cell 5 of FIG. 1, memory cell 62 of FIG. 5, memory cell 72 of FIG. 6, memory cell 82 of FIG. And the memory cell 92 of FIG. 8.

The various structures of FIGS. 1-9 can be manufactured using any suitable method, existing or not yet developed. 10-15 illustrate an example method for forming the memory cell of FIG.

With reference to FIG. 10, configuration 100 is shown in a processing stage after a second semiconductor material 104 is formed over the first semiconductor material of base 12. In some embodiments, the semiconductor material of base 12 may comprise silicon (eg, single crystal silicon), or may consist of, or consist of as a main component, semiconductor material 104. May comprise a mixture of silicon and carbon (and in some embodiments, may correspond to silicon carbide), or may consist of or consist of a major component thereof. In such embodiments, the second semiconductor material may be formed by epitaxial growth from the first semiconductor material (by carbon doping during or after the epitaxial growth of the silicon). For example, Si _x C _y (x and y are values greater than zero) can be epitaxially grown by a treatment using a temperature of at least about 1000 ° C. If a high temperature treatment is used to form the material 104, it may be desirable to perform this high temperature treatment early in the treatment flow. In particular, some materials and structures of the final integrated circuit design may be negatively affected by the high temperature treatment, and therefore, it is desirable to perform the high temperature treatment before these materials and structures are formed.

Referring to FIG. 11, material 104 is patterned to form pedestal 105 over base 12. Such patterning involves, for example, using a photolithographic patterned mask to form the location of the pedestal 105 during etching of the material 104 and then removing the mask to leave the configuration of FIG. 11. It may include.

Referring to FIG. 12, the opening 110 is etched into the substrate 12 adjacent to the pedestal 105. Formation of the apertures may then, for example, use a photolithographic patterned mask to form the position of the apertures 110 during etching into the base 12 and remove the mask to leave the configuration of FIG. 12. It may include doing.

Referring to FIG. 13, dielectric structure 54 is formed in opening 110, doped regions 106, 30, and 28 are formed in pedestal 105, and doped region 56 is a base 12. Is formed within. Doped regions may be formed using various photolithographic patterned masks to form positions of the doped regions, and the masks may be removed subsequent to the formation of the doped regions. The dielectric material of structure 54 may initially be formed to extend across regions 28 and 56, and then photolithography to form the desired location of dielectric structure 54 while removing excess dielectric material by etching. By using a patterned mask it can be patterned to only extend into opening 110.

A dielectric structure 54 is shown that includes an unmodified portion 55 and a modified portion 57. The deformation of the portion 57 is during deposition of the dielectric material of the structure 54 by forming the portion 57 to have a different composition than the portion 55 while protecting the portion of the undeformed dielectric material using a mask. Or after the deposition of the dielectric material of the structure 54. If deformation occurs after deposition of the dielectric material of structure 54, such deformation may include implantation of dopants and / or impact ionization to create a damaged area.

Referring to FIG. 14, a float 14 is formed in the opening 110, and subsequently a dielectric structure 26 is formed over the float. The float can be formed by depositing a suitable material, subsequently etching excess material using a mask to protect the material in opening 110, and subsequently removing the mask.

Referring to FIG. 15, a sense gate 24 is formed, patterned over the dielectric structure 26, and an electrical connection to the circuit 58 is made.

Embodiments described herein can provide a number of advantages over prior art non-capacitor memory cells. Some of the embodiments described herein can improve the retention time of non-capacitor memory cells. Some of the embodiments described herein provide better electrostatic control than is available in prior art non-capacitor memory cells, and provide higher sensing margins than are available in prior art non-capacitor memory cells. While increasing the bit density of small features (eg, non-planar shapes may result in higher bit densities). In addition, some embodiments may improve read and / or write efficiency over prior art non-capacitor memory cells. Some embodiments may provide additional design margins beyond those available in the prior art (eg, changing the shape of the float shown in FIG. 8 allows the volume of the float to be adjusted, thus, Allows the amount of float effect to be adjusted Some embodiments provide improved programming methods over prior art impact ionization techniques, and some embodiments reduce the problems of the prior art associated with interband tunneling.

The memory cells described above may be used in any electronic systems in which cells are appropriately placed, for example, such as computers, vehicles, aircrafts, watches, mobile phones, and the like.

Claims (35)

A float comprising a doped semiconductor material,
A gated diode having a portion doped with the same conductivity as the floating body, wherein the portion of the gated diode is electrically connected to the floating body through an electrical connection extending from the portion of the gated diode to the floating body. Connected to the gate type diode,
A gate configured to gate the gated diode,
The float and the gated diode are further supported by a semiconductor base, and laterally spaced apart from each other, further comprising an isolation region extending into the base in a space between the float and the gated diode,
The semiconductor base has a planar top surface,
There is a layer of dielectric material on the planar top surface, the layer of dielectric material has a planar top surface,
The isolation region comprises an electrically insulating material extending through the layer of dielectric material,
The float is in direct contact with and on the planar top surface of the layer of dielectric material,
The gate is in direct contact with and on the planar top surface of the dielectric material,
And the electrical connection is formed by a wire extending over the electrically insulating material of the isolation region across the planar top surface of the dielectric material. The method according to claim 1,
Further comprising a sensing gate over the float;
The float has a top surface and has sidewall surfaces extending from the planar top surface of the dielectric material to the top surface of the float,
And the sense gate extends along the sidewalls and is in direct contact with the planar top surface of the dielectric material. The method according to claim 1,
Further comprising a sensing gate over the float;
The float has a top surface and has sidewall surfaces extending from the planar top surface of the dielectric material to the top surface of the float,
And the sense gate extends partially along the sidewalls but does not directly contact the planar top surface of the dielectric material. The method according to claim 1,
And the doped semiconductor material of the float comprises germanium. A float supported by a semiconductor substrate, said float comprising a doped semiconductor material;
An isolation region extending into the substrate,
A gated diode on an opposite side of the isolation region from the float, having a portion doped with the same conductivity type as the float, wherein the portion of the gated diode is suspended from the portion of the gated diode The gate type diode electrically connected to the float through an electrical connection extending into a sieve;
A gate configured to gate the gate type diode,
A sensing circuit adjacent the float and configured to detect a state of charge of the float,
The semiconductor substrate has a planar top surface,
A layer of dielectric material is present on the planar top surface, the layer of dielectric material having a planar top surface and comprising silicon dioxide,
The isolation region comprises an electrically insulating material extending through the layer of dielectric material,
The float is in direct contact with and on the upper surface of the layer of dielectric material,
The gate is in direct contact with and on the planar top surface of the dielectric material,
And the electrical connection is comprised of a wire extending over the electrically insulating material of the isolation region across the planar top surface of the dielectric material. The method according to claim 5,
The portion of the gated diode is a first diode portion, further comprising a second diode portion directly adjacent to the first diode portion, the second diode portion being opposite to the conductivity type of the first diode portion A memory cell doped into a mold. The method of claim 6,
Wherein the conductivity type of the first diode portion is p-type and the conductivity type of the second diode portion is n-type. The method of claim 6,
Wherein the conductivity type of the first diode portion is n-type and the conductivity type of the second diode portion is p-type. The method according to claim 5,
The sensing circuit includes an access line on the float and a pair of diffusion regions in the substrate on opposite sides of the float, the diffusion regions being within the substrate just below the float. Memory cells that are connected to each other through. The method of claim 9,
And the float has a top surface, and has sidewalls extending downwardly from the top surface, wherein the access line extends at least partially along the sidewalls across the top surface. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

Images