JPS6320024B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a V
- Relating to MOS field effect transistors, and more particularly to such devices having a homogeneous channel without graded dopant concentration and increased capacitance.

A MOS field effect transistor consists of a source and drain region diffused into a crystalline substrate, an insulating layer covering the substrate, and a conductive gate electrode material placed on top of the insulating layer between the source and drain regions. It is formed by When a suitable voltage is applied to the gate electrode, the electric field generated creates a channel for charge carriers between the source and drain regions. Hence the name field effect transistor. V-MOS field effect transistor is
It is so called because the transistor is formed along the walls of a V-shaped groove or recess, unlike previous planar field effect transistors. In conventional V-MOS technology, the source of the transistor is formed below the drain region, thereby reducing the amount of space required for each transistor on the surface of the crystalline substrate. Such a V-MOS structure is, for example,
No. 3,924,265 to Rodgers and US Pat. No. 4,003,036 to Jenne.

Because the drain region is located above the source region in conventional V-MOS technology, additional processing steps are generally required compared to the planar MOS technology described above. In the conventional V-MOS structure,
An N-type source region is first formed by diffusion into a P-type crystalline silicon substrate, and then another layer of lightly P-doped silicon material is epitaxially grown over the source region. An N-type drain region is formed in an epitaxial layer covered with oxide or other insulator, a notch or recess in the V is etched, a gate insulator is grown or formed, and then a gate electrode layer is deposited on the V. It is formed. These extra steps require very difficult processing operations and additional time, thereby increasing the cost of the wafers from which integrated circuit chips are formed. However, when the device to be fabricated is a dynamic memory cell such as that disclosed in the above-mentioned U.S. Pat. allow to form.

Therefore, an object of the present invention is to provide an improved V-
An object of the present invention is to provide a MOS field effect transistor.

Another object of the invention is to provide an improved V-MOS field effect transistor with fewer difficult steps for fabrication.

Yet another object of the invention is to provide an improved dynamic memory cell using V-MOS field effect transistors.

In order to achieve the above-mentioned object, the present invention has the following features:
V− with increased source capacitance to provide a dynamic memory cell of
Found in MOS field effect transistors. Formation of the source region masks the silicon substrate and
By drilling a hole in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that it provides a shield for subsequent source region ion implantation. achieved. P and N type dopants were increased for the device
They can be implanted separately at different energy levels to form a PN junction capacitor. Such a field effect transistor can be achieved without the formation of a graded dopant concentration in the channel between the source and drain regions of the transistor.

Accordingly, a feature of the invention is to provide a V-shaped substrate having a V-shaped notch or recess etched therein and a source region formed around the lower portion of the V by ion implantation of P or N type dopants. - Found in MOS field effect transistors.

The above objects and other objects, advantages and features of the invention will become more apparent from the following description taken in conjunction with the drawings.

A typical V-MOS field effect transistor structure is illustrated in FIG. This is a structure of the type disclosed in US Pat. No. 4,003,036 referred to above. The particular device illustrated is formed from a crystalline silicon substrate, which is doped with a P-type dopant, in this case boron, such that the device is formed as an N-channel device. ing. An N ⁺ buried layer 12 is formed in the substrate 11 and an epitaxial layer 13 is grown thereon, the epitaxial layer 13 being lightly doped with P-type material. The intermediate layer 14 is P ⁺ substrate 11
The intermediate layer 14 is of the P type with a graded dopant concentration distribution, formed in the lower part of the epitaxial layer 13 by out-diffusion of P type dopants. This tilted concentration distribution region is
Since it exists in the channel of the MOS transistor,
It controls the threshold voltage of the transistor and gives it asymmetric electrical characteristics. Epitaxial layer 1 is formed such that a relatively thin N ⁺ material 15 is present above N ⁺ layer 12.
The epitaxial layer 13 is formed on the upper surface of the epitaxial layer 13.
is also passive, such as silicon dioxide.
Covered with layer 16. A V-shaped recess 17 is further etched into the structure, which extends into the implanted volume or N ⁺ layer 12. A thin gate oxide layer 18 covers the surface of this recess, and the oxide layer and the recess are further covered with a conductive material 19 to form the gate of the field effect transistor. N ⁺ layer 1
5 contains the drain of the V-MOS device, the buried layer 12 contains the source of the device, and the channel 20 between the source and drain is epitaxial P material 13 containing the intermediate layer 14. In this way, field effect transistors and storage capacitors 12 are formed, which require less substrate surface area than would be required by a corresponding planar field effect transistor with storage capacitance.

As indicated above, a difficulty with such prior art structures is that they require an epitaxial silicon layer. This is because it is difficult to grow such layers with sufficient control over resistivity. Additionally, lattice defects in epitaxial layers are generally much higher in density than in bulk silicon, thereby degrading transistor and capacitor performance.

The present invention is directed to a method and resultant structure for implant doping the bottom of a V-groove etched in silicon without doping the sidewalls of the groove. The method resulting in one embodiment of the invention can be best explained by reference to FIGS. 2A-2E. <100>
A shallow N ⁺ diffusion region 25 is provided in the P-type silicon wafer with orientation, and then SiO ₂ or SiO ₂
and a mask layer 2 which is Si ₃ N ₄ or similar material
Covered by 4. The resulting structure is illustrated in Figure 2A. A small rectangular region 23 is photolithographically formed over the N ⁺ region in which the transistor is to be placed, and a mask layer is applied to expose the underlying silicon, as illustrated in FIG. 2B. A rectangle is etched through 24. The exposed silicon is then etched with an anisotropic silicon etch (a thin
(like KOH). That sex is
The width of the V depression or groove 27 at the SiO ₂ -silicon interface is the same as the original rectangular opening 23 in SiO ₂
This continues until it becomes wider than Preferably, the recess or groove of the V is two to three times as wide as the opening. The resulting structure is illustrated in Figure 2C.

At this point, N-type dopants are implanted into the wafer, with the ion beam perpendicular to the plane of the wafer. The energy used is selected to ensure that the implant does not penetrate mask layer 24.
Must be small enough. As a result, due to the shielding effect of the protruding edges of the mask layer 24,
Only the bottom portion 22 of the V depression or trench is implant doped. The resulting structure is illustrated in Figure 2D.

Mask layer 24 is then removed and the wafer is subjected to a thermal cycle to drive-in the implanted N ⁺ junctions.
A gate oxide 26 is grown and polysilicon or other gate electrode material 28 is formed over the V trench. The gate electrode pattern is defined photolithographically and the device structure is completed. The final structure is illustrated in FIG. 2E. A typical V-MOS circuit is also a planar N-MOS circuit.
Since it includes a MOS device, several additional processing steps follow, which do not directly affect the structure of this V-MOS device.

The method as described above and the resulting V
- Variations can also be made to both the structure of the MOS device. For example, a relatively low dose P-type implant is performed after the V recess 27 is etched wider than the protruding mask edge, and the P-type dopant is implanted and thermally driven in before the N-type dopant is implanted and thermally driven in. 2 to thermally drive in the injection.
Two additional steps are performed. This is the third
Illustrated in FIGS. 3A-3C, a P-type implant results in region 29. The result of these additional steps is to increase the P-type doping level 29 around the N ⁺ source 22 junction, thereby increasing the capacitance of that junction.

From the examples in Figures 3A to 3C, P ⁺
It will be noted that region 29 completely surrounds N ⁺ source 22 in the crystalline substrate, so that a sloped channel 30 is formed between source 22 and drain 25. Although this provides more capacitance to the source PN junction, it is disadvantageous in some applications because it increases the threshold voltage of the channel and makes it more difficult to control the threshold voltage. It is from. The graded channel also provides asymmetric electrical characteristics to the V-MOS transistor.

To overcome such disadvantages, other embodiments are provided, which are illustrated in FIGS. 4A-4C. In this embodiment, the V groove or recess 3
7 is opened in the same manner as described for the previous embodiment. However, P ⁺ dopant39
(which may be boron) is first implanted using a relatively high implant energy such that it is implanted to a depth, typically from 0.4
It is believed to be 0.9 microns. Then N ⁺ dopant 32
The P ⁺ dopant 39 (which may be phosphorus) is implanted at a shallow depth of approximately 0.1 to 0.3 microns at approximately the same concentration but lower energy. The structure is then annealed, with N-type region 32 and P-type region 3
The thermal drive-in is not long enough to cause wide diffusion of 9. The structure is then annealed, but not thermally driven in long enough to cause stronger diffusion of each of the N-type regions 32 and P-type regions 39. Gate oxide 36 and conductive gate material 38 are then formed to complete the device. In the embodiment of FIGS. 4A-4C, a smaller PN junction area is obtained, but a higher capacitance is achieved due to the higher dopant concentration in the PN junction between implanted regions 39 and 32. . Furthermore, the channel region does not have a graded concentration distribution and therefore has symmetrical electrical properties.

A particular advantage of all three embodiments is that N ⁺
The oxide layer 38 on region 32 is much thicker than on channel 40 because the oxide grows more easily on the heavily N ⁺ doped region. be. In the embodiment of FIGS. 4A to 4C, the N ⁺ region 32 of the shallow implant can be removed by simply switching between the two implant operations without changing the resulting structure.
is formed before the deep implant P ⁺ region 39.

As illustrated in the embodiment of FIGS. 4A-4C, oxide regions 50 are grown during the fabrication process to provide oxide isolation between active devices that are placed in close proximity to each other. Such additional elements may be other V-MOS devices or planar N-MOS transistors formed with source region 51, drain region 52 and gate region 53. The purpose of the oxide isolation regions is to prevent conductive channels from forming between such active devices. A heavily doped P region directly below field oxide region 50 to provide additional isolation between adjacent devices if necessary.
A mold region is formed.

Although the area occupied by the source capacitance of the embodiment of FIGS. 4A-4C has been reduced, the magnitude of such capacitance is greatly increased due to the increased dopant concentrations of N region 32 and P region 39. can be done. As indicated above, this provides advantages over the embodiment of FIGS. 3A-3C. In that embodiment, P region 29 completely surrounds N region 22, resulting in a graded dopant concentration along channel 30. When an attempt is made to increase the capacity of the device of this embodiment by increasing the dopant concentration of P region 29, the threshold voltage of channel 30 is correspondingly increased. This problem is not encountered in the embodiment of FIGS. 4A-4C. In this way, the capacitance of the embodiment of FIGS. 4A-4C can be increased as needed, the only constraint being that as the capacitance increases, the breakdown voltage of the corresponding PN junction is correspondingly reduced. That's true. Relatively speaking, the embodiment of FIGS. 4A-4C can be made to have several times higher capacity than the embodiment of FIGS. 3A-3C and still be suitable for many applications. Totally acceptable for 6~
Has a breakdown voltage in the 12 volt range.

As previously indicated, a particular feature of the present invention is that during the etching of the silicon substrate, to provide adequate shielding during the ion implantation operation.
Undercutting the silicon dioxide/silicon nitride mask. Some characteristics of certain such etching techniques will now be described. <100>
Silicon substrate with crystal orientation and 3000
Silicon nitride is etched in a plasma etcher, silicon dioxide is etched in hydrofluoric acid, and the silicon substrate is etched in a mixture of KOH and water, assuming a mask of SiO ₂ of 1500 Å and Si ₃ N ₄ of 1500 Å. being fucked with Here, etching is performed at a temperature of approximately 75°C. After approximately 8 minutes, the mask is undercut by approximately 0.7 microns on each side of the V recess. After approximately 12 minutes, the undercut is approximately 0.96 microns. twenty four
After minutes, the undercut is approximately 1.49 microns. After 64 minutes, the undercut is approximately 3.2 microns. The undercut rate under the conditions described above is approximately 0.055 microns per minute during etching times longer than 20-30 minutes.
The undercut appears quite uniform and provides good undercut edge definition. 3rd A
For the embodiments of Figures 3C and 4A-4C, the masking layer of SiO ₂ and Si ₃ N ₄ is a layer of phosphosilicate glass or similar material approximately 1-1.5 μm thick. It is replaced accordingly.

The operation of the various embodiments is essentially the same, and the embodiment of FIG. 2E will now be described. To write binary data to a cell, one bit of data is applied to the drain region 25, the N ⁺ bit line. This is typically 0 volts for a "0" data bit and 5-12 volts for a "1". The word line, conductor 28, is then raised to a voltage from below the threshold voltage of the device, typically 0.5 volts to 1.5 volts, to well above its threshold voltage, ranging from 5 to 12 volts. This turns the device "on" and allows current to flow between source region 22 and drain region 25. At this time, that bit of data present on the bit line is transferred to the source region 22 and the PN junction storage capacity of the substrate 21. A data bit of ``0'' does not cause any change in the source junction, whereas a ``1'' charges that junction to a given ``1'' voltage, thereby expanding the depletion region around the N ⁺ source junction. do. This "charged" or "uncharged" state at the N ⁺ source junction represents the difference between a "1" or a "0" written to that memory cell. Word line 28 is now brought back to a voltage below the threshold voltage, thereby cutting off the channel between source 22 and drain 25 and placing the storage capacitance of its source junction in its proper data bit state.

To read the data output of the cell, the word line 28 is raised from below the threshold voltage to well above the threshold voltage;
This turns on the device. “Charging” or “non-charging” of the storage capacity of the N ⁺ source junction
The state of the bit line, 25, causes a change or no change in the voltage on the bit line, 25, which indicates whether the storage capacity is charged or not. Any change in voltage on the bit line is detected by a suitable sense amplifier elsewhere in the circuit, thereby establishing whether the memory cell contained a ``1'' or ``0'' data bit.

A V-MOS field effect transistor is described above, which does not require an extra step of epitaxial growth to form the source region of the transistor. Additionally, such transistors can provide increased source capacitance to provide a one transistor dynamic memory cell. Formation of the source region is performed by masking the silicon substrate, drilling holes in the mask, and undercutting the mask such that the mask blocks subsequent ion implantation of the source region. This is accomplished by etching the substrate.
Both P and N type dopants are used to form an increased PN junction capacitance for the device.
Can be implanted separately at different energy levels.
Such field effect transistors are achieved without the need for channel graded dopant concentrations between the source and drain regions of the transistor, thereby preserving electrical symmetry.

Although several embodiments of the invention have been described, it will be apparent to those skilled in the art that variations and modifications can be made without departing from the spirit and scope of the invention as claimed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a prior art field effect transistor memory cell. Figures 2A-2E are cross-sectional views illustrating the steps used in forming one embodiment of the present invention. Figures 3A to 3C
The figure is a sectional view showing the steps involved in forming a second embodiment of the invention. Figures 4A to 4C
The figure is a sectional view showing the steps involved in forming a third embodiment of the invention. In the figure, 21 is the substrate, 22, 2
3 is the N ⁺ source region, 24 is the mask, 25 is the N ⁺ diffusion region, 26, 36 is the gate oxide, 27, 37
28 and 38 are gate electrode materials, 29 and 39 are P ⁺ regions, and 30 and 40 are channels.

Claims (1)

Claims: 1. A field effect transistor, the transistor comprising a crystalline substrate of a first conductivity type, the substrate having a surface, and the transistor further comprising: a region of electrical conductivity of a second conductivity type disposed adjacent to the surface; a V-shaped recess in the substrate extending from the surface through the region of the second conductivity type; , a second region of the second conductivity type in the crystalline substrate, the second region being formed around the bottom of the V-shaped recess; A field effect transistor characterized in that it comprises a third region of said first conductivity type provided in said crystalline substrate at the bottom portion of said V-shaped recess and below said second region. . 2. The field effect transistor according to claim 1, wherein the third region is larger than and surrounds the second region. 3 the second region is doped with phosphorus;
2. The field effect transistor according to claim 1, wherein the third region is doped with boron. 4 further comprising an oxide layer covering the surface of the V-shaped recess, the oxide layer covering the V-shaped recess on the second region;
2. The field effect transistor according to claim 1, wherein the field effect transistor has a thickness greater than other areas on the surface of the mold depression. 5 the third region is provided with a dopant concentration such that it has a conductivity of the first conductivity type greater than the crystalline substrate, and the second region is provided with a dopant concentration similar to the dopant concentration in the third region. 2. A dopant concentration of said second conductivity type, thereby providing increased capacitance at the junction between said second and third regions. field effect transistor.