KR101337134B1 - thin film transistor, flat panel display device having it and method of fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor, a flat panel display device including the same, and a manufacturing method of a flat panel display device.

The thin film transistor of the flat panel display according to the present invention is formed on a gate electrode, an insulating film formed on the gate electrode, and an insulating film formed at the gate electrode position from a gate wiring, and a source region and a drain region on both sides of the channel region and the channel region. The defined first semiconductor layer, an insulating pattern formed in a channel region on the first semiconductor layer, a second semiconductor layer covering the portion of the insulating pattern and a source region and a drain region of the first semiconductor layer and the second semiconductor layer. And a source electrode contacting each other with the insulating pattern interposed therebetween and a drain electrode spaced apart from the source electrode.

The flat panel display device according to the present invention can ensure the stability of the low-resistance wiring process and the stability of the device and can lower the defects, thereby improving reliability.

Copper, Channel Length, Insulation Pattern

Description

Thin film transistor, flat panel display device having it and method of fabricating the same}

1 is a plan view showing one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1. FIG.

3A to 3J are cross-sectional views illustrating a process of manufacturing an array substrate of a flat panel display device according to the present invention.

Description of the Related Art [0002]

110: first substrate 121: gate wiring

121a: gate lower pad 122: gate electrode

127: gate upper pad 130: gate insulating film

141: first semiconductor layer 151, 152: second semiconductor layer

160: data wiring forming metal layer 161: data wiring

162: source electrode 163: drain electrode

165 capacitor electrode 169 barrier pattern

169a: barrier film 170: protective film

181: pixel electrode 191: photoresist pattern

The present invention relates to a thin film transistor, a flat panel display device including the same, and a manufacturing method of a flat panel display device.

 A flat panel display using a thin film transistor includes a liquid crystal display (TFT-LCD) or an organic electroluminescent display (OLED).

Liquid crystal display device (Liquid Crystal Display device) is one of the most widely used flat panel display device, currently composed of two substrates on which the electrode is formed and the liquid crystal layer inserted between the liquid crystal layer by applying a voltage to the electrode A display device for controlling the amount of light transmitted by rearranging the liquid crystal molecules.

The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transferring a voltage to be applied to the pixel electrode. Is formed on the display panel.

The thin film transistor serves as a switching element that transfers / blocks or blocks an image signal transmitted through a data line according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element for individually controlling each light emitting element in an active organic light emitting diode (AM-OLED) which is a self-luminous element.

In such a thin film transistor, chromium (Cr), molybdenum (Mo), or the like is generally used as a material of the wiring.

However, as the area of the liquid crystal display device becomes larger and larger, the length of the wiring becomes longer and longer. Accordingly, when a conventional metal wiring is used, a problem such as signal delay occurs due to a relatively high resistance.

In order to overcome this problem, although copper (Cu) having a low specific resistance is known as a suitable metal to be applied to a large area liquid crystal display device, copper (Cu), which has low corrosion resistance, has a problem that the etching process is difficult and the reliability is weak.

The present invention has a first object to provide a thin film transistor having uniform device characteristics.

Disclosure of Invention The present invention provides a flat panel display device and a method for manufacturing the same, which ensure the stability of a process so that thin film transistors may have a uniform channel length in the manufacturing process of a flat panel display device in which data wires are formed of copper metal wires. There is this.

According to an aspect of the present invention, a thin film transistor includes: a first electrode formed on a substrate; An insulating film formed on the first electrode; A first semiconductor layer formed on the insulating layer at the first electrode position and having first and second regions defined on both sides of a channel region and the channel region; An insulation pattern formed in a channel region on the first semiconductor layer; A second semiconductor layer covering a portion of the insulating pattern and the first and second regions of the first semiconductor layer; And a second electrode and a third electrode contacted with the second semiconductor layer and the insulating pattern interposed therebetween.

According to another aspect of the present invention, there is provided a flat panel display including: a gate wiring formed on a substrate; A data line crossing the gate line; A thin film transistor connected to the gate line and the data line; And a pixel electrode connected to the thin film transistor, wherein the thin film transistor is formed on a gate electrode, an insulating film formed on the gate electrode from the gate wiring, and an insulating film formed at the gate electrode position, and both sides of the channel region and the channel region. A first semiconductor layer having a source region and a drain region defined therein, an insulation pattern formed in a channel region on the first semiconductor layer, a portion of the insulation pattern and a second semiconductor layer covering the source region and the drain region of the first semiconductor layer And a source electrode contacting the second semiconductor layer with the insulating pattern therebetween and connected to the data line, and a drain electrode spaced apart from the source electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a flat panel display, including: forming a gate wiring including a gate electrode on a substrate; Forming a gate insulating film on the gate wiring; Forming a first semiconductor layer having a source region and a drain region defined on both sides of the channel region and the channel region on the gate insulating layer at the gate electrode location; Forming an insulating pattern in a channel region on the first semiconductor layer; Forming a second semiconductor layer on an entire surface of the substrate on which the insulating pattern is formed; Forming a metal layer including copper on the second semiconductor layer; Patterning the metal layer to form the source electrode and the drain electrode to expose a portion of the second semiconductor layer; Etching the exposed second semiconductor layer; And forming a pixel electrode connected to the drain electrode.

The flat panel display device according to the present invention can ensure the stability of the low-resistance wiring process and the stability of the device and can lower the defects, thereby improving reliability.

Hereinafter, a thin film transistor and a flat panel display device including the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating one pixel of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 2, an array substrate of a flat panel display device includes a gate wiring 121 formed on a first substrate 110 and a gate wiring 121 formed on the first substrate 110. A data line 161 crossing each other to define the pixel region P, at least one thin film transistor TFT formed at least in the pixel region P and having a barrier pattern 169 on the channel region, and the thin film transistor ( And a pixel electrode 181 connected to the TFT.

Among the flat panel display devices, the liquid crystal display includes a thin film transistor TFT to switch a voltage applied to the pixel electrode 181, and the thin film transistor TFT includes a scan signal transmitted through the gate line 121. As a result, the image signal transmitted through the data line 161 may be transmitted to or blocked from the pixel electrode 181. The thin film transistor TFT serves as a switching element that individually controls each light emitting element even in an active organic light emitting display element AM-OLED which is a self-light emitting element.

In the present exemplary embodiment, a passivation layer 170 is further formed to cover the thin film transistor TFT, and the passivation layer 170 exposes a portion of the drain electrode 163 of the thin film transistor TFT. Has 171.

A data pad part is formed at one end of the data line 161, and the data pad part exposes a data lower pad 161 a from which the data line 161 extends and a predetermined area of the data lower pad 161 a. An island-shaped data upper pad 167 connected to the data lower pad 161a through the passivation layer 170 having the contact hole 172 and the second contact hole 172 on the passivation layer 170. It includes.

A gate pad portion is formed at one end of the gate wiring 121, and the gate pad portion is configured to expose a gate lower pad 121 a from which the gate wiring 121 extends and a predetermined region of the gate lower pad 121 a. A gate insulating layer 130 having a contact hole 173, a passivation layer 170, and a gate upper pad 127 connected to the gate lower pad 121a through the third contact hole 173 are included.

The capacitor electrode 165 is formed on a portion of the gate line 121 with the gate insulating layer 130 interposed therebetween. A part of the capacitor electrode 165 is exposed by the fourth contact hole 174 of the passivation layer 170, and the pixel electrode 181 is connected to the capacitor electrode 165 through the fourth contact hole 174. Connected with.

The thin film transistor TFT may include a gate electrode 122 receiving a signal from the gate line 121, a gate insulating layer 130 covering the gate electrode 122, and the gate electrode 122 at a position of the gate electrode 122. A first semiconductor layer 141 formed on the gate insulating layer 130 and defining a source region S, a drain region D, and a channel region C, and a channel region of the first semiconductor layer 141. A second semiconductor layer 151 covering the barrier pattern 169 formed on C) and a portion of the barrier pattern 169 and the source region S and the drain region D of the first semiconductor layer 141. , 152, and source and drain electrodes 162 and 163 contacting the source region S and the drain region D of the second semiconductor layers 151 and 152, respectively, and spaced apart from each other. .

The first semiconductor layer 141 may be an amorphous silicon layer, and the second semiconductor layers 151 and 152 may be an amorphous silicon layer implanted with impurities.

The barrier pattern 169 is a pattern for maintaining a uniform channel length (L) of the thin film transistors regardless of process conditions, and is preferably an insulation pattern.

The barrier pattern 169 may be a single insulation pattern or a multilayer insulation pattern in which a first insulation pattern and a second insulation pattern are stacked.

The barrier pattern 169 may be an organic insulating layer pattern, and may be formed of, for example, an acrylic-based material such as photo acryl.

The barrier pattern 169 may be an inorganic insulating layer pattern, and may be formed of, for example, a silicon-based insulating material such as silicon nitride (SiNx).

In addition, the first insulating pattern of the barrier pattern 169 may be an inorganic insulating film pattern, and the second insulating pattern of the barrier pattern 169 may be an organic insulating film pattern, and the order of the first insulating pattern and the second insulating pattern may be different. Although not limited, the first insulating pattern, that is, the inorganic insulating pattern may be in contact with the first semiconductor layer 141.

Since the first semiconductor layer 141 is made of an amorphous silicon layer, the silicon-based insulating material having a bonding structure similar to that of the amorphous silicon layer is brought into contact with the channel region C, thereby not affecting the channel characteristics. To ensure the stability of the.

Here, the source electrode 162 is connected to the data line 161 to receive a data signal.

The shape of the source electrode 162 and the drain electrode 163 is not limited to the illustrated embodiment, and the shape of the source electrode 162 and the drain electrode 163 may vary depending on the design of the channel length ℓ and width. The channel length ℓ and the width may be controlled by the barrier pattern 169.

That is, the planar shape of the contact surface of the barrier pattern 169 that contacts the first semiconductor layer 141 determines the channel length (l).

Here, the channel length ℓ refers to a length of a path in which electrons move between the source region S of the first semiconductor layer 141 and the drain region D of the first semiconductor layer 141.

A first semiconductor layer 141 or a second semiconductor layer pattern may be further formed under the data line 161, the data lower pad 161a, and the capacitor electrode 165.

A pixel electrode 181 may be formed to be connected to the drain electrode 163 of the thin film transistor to receive a pixel signal.

A gate insulating layer 130 is formed as a dielectric between the capacitor electrode 165 receiving the pixel signal from the pixel electrode 181 and the gate wiring 121 to form a storage capacitor.

There may be various methods of forming the storage capacitor.

The material forming the pixel electrode 181 is at least one selected from a group of transparent conductive metals consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). It may include.

The gate wiring 121 is formed of copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten ( MoW) may comprise at least one selected from the group consisting of.

The data line 161, the source electrode 162, and the drain electrode 163 are made of a low resistance metal material including copper (Cu), and include aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), and molybdenum ( Mo, at least chromium (Cr), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), nickel (Ni), cobalt (Co) and molybdenum-tungsten (MoW) It may further include one.

Since the data line 161, the source electrode 162, and the drain electrode 163 include copper, it is difficult to obtain a desired CD (Critical Dimension) pattern in an etching process, and thus a nonuniform channel length may be obtained in a thin film transistor process. According to the present invention, the barrier pattern 169 secures the channel length prior to the etching process of the source electrode 162 and the drain electrode 163, thereby ensuring stable and uniform channel characteristics.

Although not shown, the second substrate facing the first substrate 110 may include a black matrix layer for blocking light of portions except the pixel region, and red and green colors for expressing color colors. Green) and a blue color filter layer are formed.

The first substrate and the second substrate are bonded by a sealant, and a liquid crystal layer is formed between the first substrate and the second substrate.

The thin film transistor according to the present invention has a first effect of having uniform device characteristics due to a constant channel length (l) even if the CD pattern is non-uniform when forming the source and drain electrodes.

The present invention has the second effect of ensuring the stability of the process so that the thin film transistors can have a uniform channel length in the manufacturing process of the flat panel display device to form the data wiring by copper metal wiring.

The present invention can not only use a source electrode and a drain electrode made of a low-resistance metal including copper, but also have a second effect having excellent device characteristics because it can ensure stable and uniform channel characteristics.

An array substrate of a flat panel display device having a thin film transistor according to the present invention, for example, a liquid crystal display device and an organic light emitting display device has a third effect of lowering wiring resistance and improving image quality.

The present invention has the fourth effect of ensuring the stability of the low resistance wiring process and the stability of the device, and reducing the defects, thereby improving reliability.

Hereinafter, a method of manufacturing a liquid crystal display according to the present invention will be described in detail with reference to FIG. 3.

3A to 3J are cross-sectional views illustrating a process of manufacturing an array substrate of a flat panel display device according to the present invention, and are cross-sectional views taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 3A, a gate line 121 is formed in one direction on the first substrate 110, and the gate electrode 122 is formed by protruding from a portion of the gate line 121. It is.

The gate electrode 122 is not necessarily protruded from the gate line 121, and may be a portion or an area capable of receiving a gate signal from the gate line 121.

The material forming the gate wiring 121 and the gate electrode 122 is copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), It may include at least one selected from the group consisting of tantalum (Ta), gold (Au), silver (Ag), nickel (Ni), cobalt (Co), and molybdenum-tungsten (MoW).

The gate wiring 121 may not only be formed of a single layer of metal wiring, but also may be formed of double, triple, or more multilayer metal wiring.

As shown in FIG. 3B, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the first substrate 110 by, for example, a plasma enhanced chemical vapor deposition (PECVD) method. The gate insulating layer 130 is formed.

An amorphous silicon layer is deposited and patterned on the gate insulating layer 130 to form one semiconductor layer 141 covering the upper portion of the gate electrode 122.

1 and 3C, a barrier film 169a is formed on the entire surface of the first substrate 110 on which the first semiconductor layer 141 is formed.

The barrier layer 169a may be an organic insulating layer, and may be formed of, for example, an acrylic material such as photo acryl.

The barrier layer 169a may be an inorganic insulating layer, and may be formed of, for example, a silicon-based insulating material such as silicon nitride layer (SiNx).

The barrier layer 169a may include a first insulating layer and a second insulating layer stacked on the first insulating layer, the first insulating layer may be an inorganic insulating layer, and the second insulating layer may be an organic insulating layer. The order of the first insulating film and the second insulating film is not limited, but the first insulating film, that is, the inorganic insulating film, is preferably in contact with the first semiconductor layer 141.

Since the first semiconductor layer 141 is formed of an amorphous silicon layer, a silicon-based insulating material having a bonding structure similar to that of the amorphous silicon layer is brought into contact with the channel region, thereby improving stability of the device without affecting channel characteristics. It is to secure.

Thereafter, as shown in FIG. 3D, the barrier layer 169a is patterned to form a barrier pattern 169 in the channel region C on the first semiconductor layer 141.

When the barrier layer 169a is formed of a photoacrylic photosensitive organic insulating layer, the barrier layer 169a may form the barrier pattern 169 only through an exposure and development process.

The first semiconductor layer 141 defines a channel region C, a source region S, and a drain region D, and the barrier pattern 169 defines a channel region C of the first semiconductor layer 141. Is formed.

Accordingly, the source region S and the drain region D are exposed at both sides of the barrier pattern 169, and the width a of the barrier pattern 169 is a drain region in the source region S. Refers to the distance to (D), and may coincide with the channel length (l).

In the barrier pattern 169, a contact surface contacting the first semiconductor layer 141 determines a channel length ℓ, and a variety of uniform channel lengths may be designed.

The barrier pattern 169 has a thickness h of 0.5 to 3.5 μm measured in a direction perpendicular to the first semiconductor layer 141.

As another example of the method of forming the barrier pattern 169, the barrier layer 169a may be formed of an organic insulating material, for example, an acryl-based insulating layer as a single layer film, and before forming the insulating layer. The semiconductor layer 141 may be treated with nitrogen or oxygen plasma.

Specifically, after the nitrogen plasma treatment to form a channel protective film on the surface of the first semiconductor layer 141, the barrier film 169a is formed, and the barrier film 169a is patterned to form the channel region C. The barrier pattern 169 is formed on the substrate. Thereafter, the channel passivation layer formed on the source region S and the drain region D of the first semiconductor layer 141 may be removed by etching the barrier pattern 169 as a mask. As a result, a channel passivation layer (eg, a silicon nitride layer) formed by nitrogen plasma processing may be formed on the channel region C of the first semiconductor layer 141, and a barrier pattern 169 may be formed on the channel passivation layer. have.

1 and 3E, an amorphous silicon layer 150 in which impurities are ion-implanted is formed on the entire surface of the first substrate 110 on which the first semiconductor layer 141 and the barrier pattern 169 are formed. do.

The amorphous silicon layer 150 implanted with the impurities is a side surface of the barrier pattern 169 formed on the source region S, the drain region D, and the channel region C of the first semiconductor layer 141. And an upper surface.

3F, a data wiring forming metal layer 160 is formed on the entire surface of the first substrate 110, and a photoresist pattern 191 is formed on the data wiring forming metal layer 160.

The data line forming metal layer 160 is made of a low resistance metal material including copper (Cu), and includes aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), and titanium ( It may further comprise at least one selected from the group consisting of Ti), tantalum (Ta), gold (Au), silver (Ag), nickel (Ni), cobalt (Co) and molybdenum-tungsten (MoW).

The data line forming metal layer 160 forms the data line 161, the data lower pad 161a, the source electrode 162, and the drain electrode 163 after the patterning process.

The photoresist material constituting the photoresist pattern 191 may be selectively used among a positive photoresist material or a negative photoresist material.

The positive photoresist material is a material in which a cross link of a light receiving portion is broken and removed by a developing solution. The negative photoresist material is a material in which a cross link is generated in a light receiving portion, It is a substance that is removed by developer.

In order to form the photoresist pattern 191, a photoresist film is formed on the first substrate 110, and a mask is disposed on the photoresist film.

And light, for example, an ultraviolet-ray etc., is irradiated on the said photo mask.

The mask has a light blocking part and a light transmitting part pattern formed to transmit or block the irradiated light to adjust the amount of light.

The light blocking part of the mask is formed of a material capable of blocking the light irradiated by the mask, and the light transmitting part is formed by forming or opening a transparent material capable of transmitting all the light irradiated by the mask.

The mask formed as described above is disposed on the entire surface of the first substrate, and when light is irradiated onto the mask, the light transmitted through the mask is transferred onto the photoresist film.

Subsequently, when the photoresist film is developed by immersing or spraying a developer, the photoresist pattern is formed, and the photoresist pattern remains in a region corresponding to the light blocking part without being developed and in a region corresponding to the light transmitting part. Silver is removed by the development to expose the data line forming metal layer.

In this case, the distance b between the photoresist pattern 191 formed on the source region S and the photoresist pattern 191 formed on the drain region D is greater than that of the barrier pattern 169. It may be smaller than the width a.

Thereafter, as illustrated in FIG. 3G, the data line forming metal layer 160 of the portion where the photoresist pattern 169 is exposed as a mask is etched to expose the amorphous silicon layer 150 implanted with impurities.

The data line forming metal layer 160 may be removed by wet etching, and dry etching may also be performed.

The data line forming metal layer 160 pattern is formed under the photoresist pattern 191, and an amorphous silicon layer 150 in which impurities are ion implanted is formed under the data line forming metal layer 160 pattern. The wiring forming metal layer 160 pattern forms a data wiring 161, a data lower pad 161a, a source electrode 162, a drain electrode 163, and a capacitor electrode 165.

Since the data line forming metal layer 160 is made of a metal layer including copper, corrosion resistance is poor, and thus the data wiring forming metal layer 160 is etched under the side surface of the photoresist pattern 191.

An etchant penetrates into a space between the photoresist pattern 191 formed on the source region S and the photoresist pattern 191 formed on the drain region D to form the data line forming metal layer 160. Etch it.

In this case, when the path is underetched under the photoresist pattern 191, first, a data line forming metal layer on the barrier pattern 169 in a horizontal direction with respect to the substrate under the side of the photoresist pattern 191 ( 160 is etched and underetched along the side of the barrier pattern 169 in a direction perpendicular to the substrate.

Since the thickness of the barrier pattern 169 (the length of the barrier pattern measured in the direction perpendicular to the first semiconductor layer, h) is sufficiently secured, the first semiconductor layer 141 is formed by the underetch path as described above. Alternatively, the second semiconductor layers 151 and 152 are not exposed. Therefore, a uniform channel length can be ensured by the barrier pattern 169.

According to the present invention, since the data line forming metal layer 160 includes copper, it is difficult to obtain a desired CD (Critical Dimension) pattern in an etching process, thereby obtaining a non-uniform channel length in a thin film transistor process. Since the barrier pattern 169 is formed on the channel length to secure the channel length, it is possible to secure stable and uniform channel characteristics.

As shown in FIG. 3H, the amorphous silicon layer 150 implanted with the impurities is etched using the photoresist pattern 191 as an etching mask to form second semiconductor layers 151 and 152 in the thin film transistor.

In this case, it is preferable to use dry etching as a method of etching the amorphous silicon layer 150 implanted with the impurities. The dry etching has anisotropic etching characteristics.

Accordingly, the data line forming metal layer pattern 160 is underetched from the side, but the amorphous silicon layer 150 implanted with the impurities is not underetched by anisotropic etching, so the data line forming metal layer 160 ) May protrude from the lower side of the pattern. This is well illustrated in the area K indicated in FIG. 3H.

The second semiconductor layer pattern 150a may also be formed under the data line 161, the data lower pad 161a, and the capacitor electrode 165.

As shown in FIGS. 1 and 3I, the photoresist pattern 191 is removed.

A barrier pattern 169 is formed on the channel region C on the first semiconductor layer 141, and an upper portion of the barrier pattern 169, a portion of a side surface of the barrier pattern 169, and the first semiconductor layer are formed. Second semiconductor layers 151 and 152 covering the source region S and the drain region D of 141 are formed.

More specifically, the second semiconductor layers 151 and 152 are formed on both ends of the barrier pattern 169, and the second semiconductor layers 151 and 152 are separated on the barrier pattern 169 and both ends thereof. It is formed over.

The second semiconductor layers 151 and 152 are formed to extend from one end of the barrier pattern 169 to the source region S of the first semiconductor layer 141 along one side of the barrier pattern 169. have.

The second semiconductor layers 151 and 152 are formed at the other end of the barrier pattern 169 to the drain region D of the first semiconductor layer 141 along the other side of the barrier pattern 169. .

The one side and the other side of the barrier pattern 169 may be opposite to each other.

The second semiconductor layers 151 and 152 formed on the source region S and the drain region D of the first semiconductor layer 141 are naturally separated by the barrier pattern 169.

The second semiconductor layers 151 and 152 formed on the source region S and the drain region D of the first semiconductor layer 141 are in contact with the source electrode 162 and the drain electrode 163, respectively. It serves as an ohmic contact layer.

Since the source electrode 162 and the drain electrode 163 are made of a metal including copper, the source electrode 162 and the drain electrode 163 may be difficult to obtain a desired CD pattern by being underetched in an etching process, and the source electrode 162 and the drain electrode 163 may be opposed to each other. CD deviation may occur in the sidewalls of the channel, but since the barrier pattern 169 secures the channel length ℓ, the channel may be caused by the non-uniform CD pattern and the CD deviation of the source electrode 162 and the drain electrode 163. Does not affect the length

Accordingly, the thin film transistor according to the present invention can not only use the source electrode 162 and the drain electrode 163 made of a low resistance metal including copper, but also ensure stable and uniform channel characteristics, thereby providing excellent device characteristics. It has its advantages.

In addition, an array substrate of a flat panel display device having a thin film transistor according to the present invention, for example, a liquid crystal display device and an organic electroluminescent display device can secure process stability and device stability while reducing wiring resistance and reduce defects. The reliability can also be improved.

As shown in FIGS. 1 and 3J, the passivation layer 170 is formed on the entire surface of the first substrate 110 on which the thin film transistor is formed.

The passivation layer 170 may be formed of an organic insulating layer, and may be made of, for example, an acrylic-based material such as photoacrylic.

The photo acryl is a photosensitive insulating material, and there is no need to perform a separate photolithography process to pattern the passivation layer 170.

The passivation layer 170 may be formed of an inorganic insulating layer, for example, may be made of a silicon-based insulating material such as a silicon nitride film.

The passivation layer 170 may be formed by stacking the inorganic insulating layer and the organic insulating layer.

The passivation layer 170 may include a first contact hole 171 exposing a predetermined region of the drain electrode 163, a second contact hole 172 exposing a predetermined region of the data lower pad 161a, and And a third contact hole 173 exposing a predetermined region of the gate lower pad 121a and a fourth contact hole 174 exposing a predetermined region of the capacitor electrode 165.

Thereafter, a transparent conductive metal is deposited and patterned on the passivation layer 170 to form a pixel electrode 181 connected to the drain electrode 163 and the first contact hole 171 of the thin film transistor.

The material constituting the pixel electrode 181 is at least one selected from a group of transparent conductive metals consisting of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO). It may include.

The pixel electrode 181 may be connected to the capacitor electrode 165 through the fourth contact hole 174 of the passivation layer 170 to form a storage capacitor.

The transparent conductive metal may be patterned to form a data upper pad 167 of the data pad, and the data upper pad 167 is connected to the data lower pad 161a through the second contact hole 172. do.

The transparent conductive metal may be patterned to form a gate upper pad 127 of the gate pad, and the gate upper pad 127 is connected to the gate lower pad 121a through the third contact hole 173. do.

As mentioned above, although the present invention has been described in detail through specific embodiments, the present invention has been described in detail, and the thin film transistor according to the present invention, a flat panel display including the same, and a manufacturing method of the flat panel display are not limited thereto. It is apparent that modifications and improvements are possible to those skilled in the art within the technical idea of the present invention.

The thin film transistor according to the present invention has a first effect of having uniform device characteristics due to a constant channel length even if the CD pattern is non-uniform when forming the source and drain electrodes.

The present invention has the second effect of ensuring the stability of the process so that the thin film transistors can have a uniform channel length in the manufacturing process of the flat panel display device to form the data wiring by copper metal wiring.

The present invention can not only use a source electrode and a drain electrode made of a low-resistance metal including copper, but also have a second effect having excellent device characteristics because it can ensure stable and uniform channel characteristics.

An array substrate of a flat panel display device having a thin film transistor according to the present invention, for example, a liquid crystal display device and an organic light emitting display device has a third effect of lowering wiring resistance and improving image quality.

The present invention has the fourth effect of ensuring the stability of the low resistance wiring process and the stability of the device, and reducing the defects, thereby improving reliability.

Claims (20)

A first electrode formed on the substrate; An insulating film formed on the first electrode; A first semiconductor layer formed on the insulating layer at the first electrode position and having first and second regions defined on both sides of a channel region and the channel region; An insulation pattern formed in a channel region on the first semiconductor layer; A second semiconductor layer covering a portion of the insulating pattern and the first and second regions of the first semiconductor layer; And A second electrode and a third electrode contacted with the second semiconductor layer and the insulating pattern interposed therebetween, The insulating pattern includes a thin film transistor comprising an organic insulating pattern. The method according to claim 1, The second electrode and the third electrode is a thin film transistor, characterized in that containing copper (Cu). The method according to claim 1, The thickness of the insulating pattern is a thin film transistor, characterized in that 0.5 to 3.5㎛ from the first semiconductor layer. delete The method according to claim 1, The insulating pattern is a thin film transistor comprising a photo acryl-based insulating pattern. The method according to claim 1, The first semiconductor layer may include amorphous silicon, and the second semiconductor layer may include amorphous silicon implanted with impurities. A gate wiring formed on the substrate; A data line crossing the gate line; A thin film transistor connected to the gate line and the data line; And A pixel electrode connected to the thin film transistor, The thin film transistor may include a first semiconductor formed from a gate electrode, an insulating film formed on the gate electrode, and an insulating film formed at the gate electrode position, and having a source region and a drain region defined on both sides of the channel region and the channel region. A layer, an insulating pattern formed in a channel region on the first semiconductor layer, a second semiconductor layer covering a portion of the insulating pattern and a source region and a drain region of the first semiconductor layer, and between the second semiconductor layer and the insulating pattern. A source electrode connected to the data line and spaced apart from the source electrode, the source electrode being in contact with the data line; The insulating pattern includes an organic insulating pattern. 8. The method of claim 7, And the data line, the source electrode, and the drain electrode include copper (Cu). 8. The method of claim 7, The thickness of the insulating pattern is 0.5 to 3.5㎛ flat panel display device from the first semiconductor layer. delete 8. The method of claim 7, The insulating pattern includes a photo acrylic-based insulating pattern. 8. The method of claim 7, And the second semiconductor layer pattern is further formed under the data line. 8. The method of claim 7, And the first semiconductor layer includes amorphous silicon, and the second semiconductor layer includes amorphous silicon implanted with impurities. Forming a gate wiring including a gate electrode on the substrate; Forming a gate insulating film on the gate wiring; Forming a first semiconductor layer having a source region and a drain region defined on both sides of the channel region and the channel region on the gate insulating layer at the gate electrode location; Forming an insulating pattern in a channel region on the first semiconductor layer; Forming a second semiconductor layer on an entire surface of the substrate on which the insulating pattern is formed; Forming a metal layer including copper on the second semiconductor layer; Patterning the metal layer to form a source electrode and a drain electrode to expose a portion of the second semiconductor layer; Etching the exposed second semiconductor layer; And Forming a pixel electrode connected to the drain electrode; And the insulating pattern includes an organic insulating pattern. 15. The method of claim 14, Patterning the metal layer to form the source electrode and the drain electrode to expose a portion of the second semiconductor layer, Forming a photoresist pattern covering the source region and the drain region on the metal layer; And Forming a data line including a source electrode for connecting the source region by etching the metal layer using the photoresist pattern as a mask, and forming a drain electrode spaced apart from the source electrode and for connecting with the drain region; The manufacturing method of a flat panel display device. 16. The method of claim 15, In etching the exposed second semiconductor layer, Etching the exposed second semiconductor layer to separate the second semiconductor layer from the insulating pattern; And And removing the photoresist pattern. 15. The method of claim 14, In the forming of the insulating pattern on the channel region of the first semiconductor layer, Forming a photosensitive organic insulating film on the substrate; And Selectively exposing and developing the photosensitive organic insulating layer. 15. The method of claim 14, In the step of separating the second semiconductor layer, And the second semiconductor layer covers a portion of the insulating pattern and a source region and a drain region of the first semiconductor layer. 15. The method of claim 14, The thickness of the insulating pattern is 0.5 to 2.5㎛ from the first semiconductor layer manufacturing method of the flat panel display device. 16. The method of claim 15, The spaced distance between the photoresist pattern formed on the source region and the photoresist pattern formed on the drain region is smaller than the width of the insulating pattern in a channel length direction.

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