KR101308445B1 - Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a liquid crystal display device in which the ground potential is stably applied to the entire liquid crystal panel by adjusting the ground wiring position and providing the conductive seal pattern. A first substrate and a second substrate facing each other, having a non-display region, a conductive seal pattern formed in the non-display region between the first and second substrates, and a pixel region crossing each other on the first substrate to define A plurality of gate wirings and data wirings, a gate driver that is formed in a non-display area of the first substrate, and applies a signal to each of the gate wirings, and a non-display area of the first substrate, A data driver for applying a signal to a wiring and a non-display area on the first substrate are electrically connected to the conductive seal pattern. From one side of the driver, including a ground interconnection formed to be connected to one side of the gate driver it is characterized by including the yirueojim made.

Ground wiring, common wiring, conductive seal pattern

Description

Liquid crystal display device

1 is a plan view showing a conventional liquid crystal display device

FIG. 2 is a three-dimensional perspective view of a portion corresponding to portion 'A' of FIG. 1.

3 is a plan view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

4 is a three-dimensional perspective view of a portion corresponding to portion 'B' of FIG.

FIG. 5 is a cross-sectional view illustrating a portion corresponding to one pixel and a portion B in a display area of the liquid crystal display of the first exemplary embodiment of FIG. 4. FIG.

6 is a plan view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a portion corresponding to one pixel and a portion B in a display area of the liquid crystal display of the second exemplary embodiment of FIG. 6.

8A and 8B are plan views illustrating common wires and first and second connection wires for applying a common voltage according to a third embodiment of the present invention.

9 is a plan view illustrating a connection relationship between common wirings and first and second connection wirings and a conductive seal pattern in a liquid crystal display according to a third exemplary embodiment of the present invention.

10 is a plan view illustrating a liquid crystal display according to a fourth exemplary embodiment of the present invention.

11 is a circuit diagram schematically illustrating the upper and lower plate resistors of the present invention and a parallel configuration thereof.

Description of the Related Art [0002]

100: first substrate 110: gate drive IC

120: data drive IC 150: display area

200: second substrate 201: black matrix layer

202 black matrix layer 203 common electrode

210: seal pattern 211: insulating film

212: transparent electrode pattern 213: semiconductor layer

214a: source electrode 214b: drain electrode

222: pixel electrode 220, 320: ground wiring

221 gate insulating film 231 protective film

241: gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device in which ground potential is stably applied to the entire liquid crystal panel by adjusting a ground wiring position and providing a conductive seal pattern.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in various ways such as a television and a computer monitor for receiving and displaying broadcast signals.

In order to use such a liquid crystal display as a general screen display device in various parts, it is a matter of how high quality images such as high definition, high brightness and large area can be realized while maintaining the characteristics of light weight, thinness and low power consumption. Can be.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second glass substrates bonded to each other with a predetermined space; It consists of a liquid crystal layer injected between the said 1st, 2nd glass substrate.

The first glass substrate (TFT array substrate) may include a plurality of gate wires arranged in one direction at a predetermined interval, a plurality of data wires arranged at regular intervals in a direction perpendicular to the respective gate wires, A plurality of pixel electrodes formed in a matrix form in each pixel region defined by crossing gate lines and data lines, and a plurality of thin film transistors switched by signals of the gate lines to transfer signals of the data lines to each pixel electrode. Is formed.

The second glass substrate (color filter substrate) includes a light shielding layer for blocking light in portions other than the pixel region, an R, G, and B color filter layers for expressing color colors, and a common electrode for implementing an image. Is formed.

The driving principle of the general liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Such a liquid crystal display includes a process of manufacturing a lower array substrate on which thin film transistors and pixel electrodes are arranged, a process of manufacturing an upper color filter substrate including a color filter and a common electrode, an arrangement of the two substrates manufactured, and a liquid crystal material It is formed by a liquid crystal cell process consisting of injection, encapsulation, and polarizer attachment.

A general liquid crystal display device includes a liquid crystal display module, a system for applying power required for driving the liquid crystal display module and generating a control signal for driving the liquid crystal display module and the liquid crystal display module and the system to protect from the outside. It consists of an external case.

The outer case is a material for protecting the liquid crystal display module and the system, and is a component having a buffering effect against impact, and casings the liquid crystal display module and the system under conditions that do not reduce the efficiency of the display area.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating a conventional liquid crystal display, and FIG. 2 is a three-dimensional perspective view of a portion corresponding to portion 'A' of FIG. 1.

As shown in FIG. 1, a conventional liquid crystal display device includes a first substrate 10 and a second substrate 20 facing each other in which a display region 15 is defined at a center and a remaining region is defined as a non-display region. And a liquid crystal layer (not shown) filled between the first and second substrates 10 and 20. Here, a seal pattern 50 is formed in the non-display area, which is responsible for bonding between the first and second substrates 10 and 20.

In this case, the first substrate 10 is relatively wider than the second substrate 20 so that portions corresponding to one side or two sides adjacent to each other are formed to have a wider width. ), A predetermined portion of the first substrate 10 is exposed. In this case, a gate portion that functions as a pad portion where the first substrate 10 is exposed and applies a signal such as a gate wiring (not shown) and a data wiring (not shown) formed in the display area 15. The drive IC 30 and the data drive IC 40 are formed.

In order to form the ground of the first substrate 10, the gate and the data drive ICs 30 and 40 are formed around the seal pattern 50 where the gate and the data drive ICs 30 and 40 are not formed. Here, the ground line 60 is in a ground state through the data drive IC 40, thereby discharging static electricity and the like, and stabilizing the potential of the first substrate 10.

However, the ground wiring 60 is connected to only one side of the data drive IC 40 and has a predetermined distance from the gate drive IC 30 (see 'A' in FIG. 1). On the 30 side, a separate wiring (not shown) connected to the ground wiring 60 should be provided for ground processing. In this case, if the resistance of the ground wiring 60 and the separate wiring is not sufficiently low, it is impossible to apply a uniform ground voltage from the gate drive IC 30 to the first substrate 10.

That is, noise peaks in the panel cause a logic error of the data drive IC 40 when the ground wire 60 is connected to the gate drive IC 30, and thus the boundary between the adjacent data drive ICs 40. Failures such as blocky shut down occur.

As described above, in the case of the single bank structure in which the gate drive IC 30 is formed only on one side of the first substrate 10, the gate drive IC 30 may be bypassed from the data drive IC 40 to apply ground. If the resistance of (60) itself is not low enough, it is impossible to apply the ground voltage from the gate drive IC.

In the conventional liquid crystal display, as shown in FIG. 2, the seal pattern 50 includes glass fiber and a light or thermosetting resin, and is made of a non-conductive material. The insulating layer 16 is electrically insulated from the ground wiring 60 via the insulating film 16.

The conventional liquid crystal display device has the following problems.

First, in the case of a single bank structure in which the gate drive IC is formed only on one side of the first substrate, the gate drive IC can be bypassed from the data drive IC and applied to ground, but if the resistance of the ground wiring itself is not sufficiently low, It is not possible to apply ground voltage. That is, noise peaks in the panel may cause a defect such as a shut-off due to a drive IC logic error when the ground wiring is connected to the gate drive IC.

Second, due to the design constraints of the TFT, the ground wiring cannot be formed sufficiently wide, so that the ground potential in the panel is not stable.

An object of the present invention is to provide a liquid crystal display device in which a ground potential is stably applied to the entire liquid crystal panel by adjusting ground wiring positions and providing a conductive seal pattern. .

The liquid crystal display device of the present invention for achieving the above object comprises a first substrate and a second substrate facing each other, each having a display area in the center and a non-display area at the outside thereof; A conductive seal pattern formed in a non-display area between the substrates, a plurality of gate wirings and data wires defining a pixel area crossing each other on the first substrate, and a non-display area of the first substrate, wherein the respective gates A gate driver for applying a signal to a wiring, a data driver for applying a signal to each of the data wirings, and a non-display region on the first substrate, the gate driver for applying a signal to the wiring and the conductive seal pattern And a ground line formed to be connected from one side of the data driver to one side of the gate driver. It has that feature.

The ground line is formed to pass through the conductive seal pattern formed to correspond to sides on which the gate driver and the data driver are not formed.

An insulating film having a hole is formed between the ground wire and the conductive seal pattern, and a transparent electrode pattern is formed on the hole to further form a contact portion electrically connecting the ground wire and the conductive seal pattern.

The conductive seal pattern includes a conductive ball, and the conductive ball is made of Au (gold) or Pt (platinum), for example.

The ground line passing through the conductive seal pattern has a width smaller than that of the seal pattern.

In addition, a common electrode and a pixel electrode having an alternating shape are further formed in each pixel area on the first substrate. Alternatively, a pixel electrode may be formed in each pixel area on the first substrate, and a common electrode may be further formed on the front surface of the second substrate.

The ground line may further include a feedback line that enters an end portion of the data driver on one side thereof.

The ground wiring is formed on the same layer as the gate wiring or data wiring.

In addition, the liquid crystal display device of the present invention for achieving the same object, the first substrate and the second substrate facing each other, each having a display area in the center and a non-display area on the outside thereof, and the first and second substrates A conductive seal pattern formed in a non-display area between the plurality of gate lines, a plurality of gate lines and data lines defining a pixel area crossing each other on the first substrate, a pixel electrode formed in each pixel area on the first substrate, A common electrode formed over the entire substrate, a gate driver formed in a non-display area of the first substrate to apply a signal to the gate lines, and a non-display area of the first substrate, the data lines A data driver for applying a signal to the data driver; And a common wiring electrically connected to the common electrode through the conductive seal pattern, and configured to connect one side of the gate driver and one side of the data driver to a non-display area on the first substrate. have.

The common wiring is formed in a shape passing through the conductive seal pattern.

The common wiring further includes a feedback wiring that enters an end of the data driver on one side thereof.

The common wiring is made of the same metal as the gate wiring.

The electronic device may further include a first connection line connected to the common line adjacent to the gate driver. The first connection line may be formed in plural. The first connection line is a metal formed on the same layer as the gate line.

Transparent electrode patterns are formed between intersections of the conductive seal pattern and the common wiring and intersections of the conductive seal pattern and the first connection wiring, respectively, and transparent electrode patterns are formed between the common wiring and the first connection wiring. The first contact portion may be further formed to electrically connect to the conductive seal pattern.

And a second connection line electrically connected to the first connection line and the common line from the data driver and passing through an adjacent seal pattern. At this time, it is preferable that the second connection wiring is a metal formed on the same layer as the data wiring, and the intersection portion of the first connection wiring and the second connection wiring is located at the first contact portion.

In addition, the conductive seal pattern includes a conductive ball, the conductive ball includes Au (gold) or Pt (platinum).

The common wire passing through the conductive seal pattern is formed to have a smaller width than the seal pattern.

Hereinafter, the liquid crystal display of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

3 is a plan view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a three-dimensional perspective view of a portion corresponding to part 'B' of FIG. 3.

3 and 4, the liquid crystal display according to the first exemplary embodiment of the present invention includes a first substrate 100 and a first substrate 100 facing each other having a display area 150 at the center and a non-display area at the outside thereof. A pixel region is defined by crossing the second substrate 200, the conductive seal pattern 210 formed in the non-display area between the first and second substrates 100 and 200, and the first substrate 100. A plurality of gate wires (not shown, formed in a horizontal direction on the first substrate of FIG. 3) and data wires (not shown, formed in a vertical direction on the first substrate of FIG. 3), and the first substrate 100. A plurality of gate drive ICs 110 formed in a non-display area of the substrate to apply a signal to the gate wirings, and a plurality of gate drive ICs 110 formed in the non-display region of the first substrate 100 to apply a signal to the data wirings; The conductive seal patterns 210 on the two data drive ICs 120 and the first substrate 100. A passing seat comprises a ground wire 220 is formed to be connected to a side of the gate drive IC (110) from one side of the data drive IC (120).

Here, the plurality of gate drive ICs 110 are collectively referred to as gate drivers, and the plurality of data drive ICs 120 are referred to as data drivers.

In addition, as shown in FIG. 4, the conductive seal pattern 210 has an electrical connection with the ground wiring 220. In other words, an insulating film 211 having holes is formed between the ground wire 220 and the conductive seal pattern 210, and a transparent electrode pattern 212 is formed on the hole to form the ground wire 220. A contact portion (see 'B' portion of FIG. 3) electrically connected to the conductive seal pattern 210 is formed.

The ground line 220 is formed to pass through the conductive seal pattern 210 formed to correspond to sides on which the gate drive IC 110 and the data drive IC 120 are not formed. Therefore, the ground line 220 will be formed along the conductive seal pattern 210 of the letter '' ', as described with reference to FIG. 3. The ground wiring 220 passing through the conductive seal pattern is formed to be connected to an end of the data drive IC 120 and an end of the gate drive IC 110. Accordingly, the ground wiring 220 allows the ground voltage applied to the data drive IC 120 to be connected to the gate drive IC 110, and thus the first substrate 100 and the gate drive IC 110. The same level ground is formed in the data drive IC 120.

Here, the conductive seal pattern 210 includes conductive balls. The conductive ball is made to contain Au (gold) or Pt (platinum). In addition, the conductive seal pattern 210 is formed to surround the outer surface of the first substrate 100 to form a uniform ground voltage on the entire first substrate 100.

Here, the ground wire 220 passing through the conductive seal pattern 210 is formed to have a smaller width than the seal pattern 210. For example, the width of the seal pattern 210 is formed in about 2mm, and the width of the ground wiring 220 is formed in about 1mm. Here, since the conductive seal pattern 210 should include an epoxy resin or glass fiber in addition to the conductive balls therein, the conductivity will be lower than that of the ground wiring 220, but it has a relatively wide width and therein. Increase the conductivity of the conductive ball included. Accordingly, a ground voltage similar to that of the ground wiring 220 may be transmitted to the conductive seal pattern 210, thereby forming a shape of the conductive seal pattern 210 surrounding the edge of the first substrate 100. The ground voltage of the same level will be applied to the first substrate 100 as a whole.

In addition, the ground line 220 may further include a feedback line (not shown) that enters an end portion of the data driver 120 on one side thereof.

In the liquid crystal display according to the first exemplary embodiment of the present invention, the ground line 220 and the seal pattern 210 function as the ground together. The function of the ground wiring 220 is to discharge the static electricity remaining in the first substrate 100 to the outside, thereby making the first substrate 100 in a stable ground state. In addition, the mode to which the structure is applied is preferably an in-plane switching (IPS) mode together with a thin film transistor (TFT) in which both the pixel electrode and the common electrode are formed at the intersection of the gate line and the data line. It is formed on the first substrate 100.

Hereinafter, the structure of the liquid crystal display of the first exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a cross-sectional view illustrating a portion corresponding to one pixel and a portion B in the display area of the liquid crystal display according to the first embodiment of FIG. 4.

As shown in FIG. 5, a thin film transistor is formed at an intersection portion of the gate line (not shown) and the data line (not shown), and pixels having a shape in which the gate line and the data line intersect with each other are alternately formed in the pixel area defined. The electrode 222 and the common electrode 223 are further formed.

The thin film transistor may include a gate electrode 241 protruding from the gate line, a gate insulating layer 221 formed on the first substrate 100 including the gate electrode 241, and the gate electrode 241. A semiconductor layer 233 is formed on the gate insulating layer 221, and a source electrode 214a and a drain electrode 214b formed on both sides of the semiconductor layer 233 are formed on the gate insulating layer 221. In this case, the semiconductor layer 233 includes an impurity layer 216 below the amorphous silicon layer 213 and the source / drain electrodes 214a and 214b from below.

In addition, a passivation layer 231 having a first hole having a portion exposing the drain electrode 214b is formed on the entire surface of the first substrate 100, and is in contact with the drain electrode 214b to form the passivation layer 231. And a common electrode 223 formed in the pixel area alternately with the pixel electrode 222.

In addition, a gate insulating film 221 and a protective film 231 are formed on an upper portion of the ground wiring 220, and the insulating film 211 including the protective film 231 and the gate insulating film 221 is selectively removed. The second hole corresponds to the transparent electrode pattern 212 formed on the same layer as the pixel electrode 222 and the common electrode 223 by providing a second hole having a shape in which the ground wiring 220 is exposed. It is formed to pass through the upper portion of the ground wiring 220. The ground wiring 220 and the transparent electrode pattern 212 are electrically connected to each other, and a conductive seal pattern 210 is formed thereon.

Here, the conductive seal pattern 210 may be formed on the first substrate 100 including the second substrate 200 or the transparent electrode pattern 212, preferably, the flat second substrate 200. It is good to form on the surface.

On the second substrate 200 corresponding to the display area, a gate line and a data line, a black matrix layer 201 covering the thin film transistor forming region, and at least a color filter layer 202 formed corresponding to the pixel area are formed. It is made to include.

Although not shown, the ground line may further include a feedback line that enters an end portion of the data driver on one side thereof. This is to compensate for the ground voltage being different between the regions due to the resistance of the wiring when it is formed on the first substrate 100. The path of the ground wiring is long or the line width of the ground wiring is large in a large area panel. Short case is available.

The ground wiring 220 is formed on the same layer as the gate wiring or the data wiring. Here, the ground line 220 is formed at a portion of the gate line and the data line or a portion of the ground line 220 which does not overlap the pad portion connected to each drive IC.

In some cases, the ground wiring having the above-described structure may be formed in the liquid crystal display of the twisted nematic (TN) mode in which the common electrode is formed on the second substrate (upper substrate). In this case, the common electrode may be omitted on the surface of the second substrate so as to correspond to a portion where the ground wiring is formed to prevent the ground voltage from being supplied to the common electrode through the seal pattern, or on the entire surface of the second substrate. After the common electrode is formed, the seal pattern and the ground voltage may be applied to the ground wiring only when grounding, and a common voltage connected to the common electrode on the second substrate may be applied on the first substrate so as to pass the conductive seal pattern separately. It can also form more paths.

- Second Embodiment -

Hereinafter, a liquid crystal display according to a second exemplary embodiment of the present invention in which a common wiring is formed at a portion overlapping the seal pattern to form a uniform common voltage level in the liquid crystal panel will be described.

6 is a plan view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a portion corresponding to one pixel and a portion B within a display area of the liquid crystal display according to the second exemplary embodiment of FIG. 6. to be.

6 and 7, the liquid crystal display according to the second exemplary embodiment of the present invention includes a first substrate 100 facing each other, each having a display area 150 in the center and a non-display area in the outer portion thereof. And a pixel region crossing the second substrate 200, the conductive seal pattern 210 formed in the non-display area between the first and second substrates 100 and 200, and the first substrate 100. A plurality of gate wirings (not shown) and data wirings (not shown), a pixel electrode 222 formed in each pixel area on the first substrate, and a common electrode 203 formed on the entire surface of the second substrate 200. ) And a plurality of gate drive ICs 110 formed in the non-display area of the first substrate 100 to apply signals to the respective gate wirings, and in the non-display area of the first substrate 100. And a plurality of data drive ICs 120 and the conductive seals to apply signals to the respective data wires. It is electrically connected to the common electrode 203 through the pattern 210 to the non-display area on the first substrate 100, to the end of the gate drive IC 110 and the end of the data drive IC 120. It includes a common wiring 320 formed to be connected.

The common wire 320 is formed to pass through the conductive seal pattern 210. That is, the common wiring 320 will be formed along the conductive seal pattern 210 of the letter '' '. The common wire 320 passing through the conductive seal pattern 210 is formed to be connected to an end of the data drive IC 120 and an end of the gate drive IC 110. Therefore, the common voltage applied to the gate drive IC 110 or the data drive IC 120 is common on the second substrate 200 through the common wiring 320 and the conductive seal pattern 210. The common voltage of the same level is formed in the electrode 203. That is, since the common wiring 320 and the seal pattern 210 are provided, a stable DC voltage value applied through the gate drive IC 110 or the data drive IC 120 is the common electrode 203. To be applied). Here, the seal pattern 210 has a closed loop shape, and the common voltage applied through the gate drive IC 110 or the data drive IC 120 is applied to the common wire 320. The common voltage value dropped by the wiring resistance while passing through the common wiring 320 can be returned to the application point of each drive IC 110 or 120 to transfer the compensated common voltage value back to the common wiring 320. Function as feedback wiring.

In addition, the first connection wiring 322 is further formed at each end of the plurality of gate drive ICs 110 in addition to the common wiring 320 to be electrically connected to the conductive seal pattern 210 adjacent thereto.

A thin film transistor is formed at an intersection of the gate line (not shown) and the data line (not shown), and a pixel electrode 222 is further formed in a pixel region defined by the gate line and the data line crossing each other.

The thin film transistor may include a gate electrode 241 protruding from the gate line, a gate insulating layer 221 formed on the first substrate 100 including the gate electrode 241, and the gate electrode 241. The semiconductor layer 233 is formed on the gate insulating layer 221, and the source electrode 214a and the drain electrode 214b are formed on both sides of the semiconductor layer 233. In this case, the semiconductor layer 233 includes an impurity layer 216 below the amorphous silicon layer 213 and the source / drain electrodes 214a and 214b from below.

In addition, a passivation layer 231 having a first hole having a portion exposing the drain electrode 214b is formed on the entire surface of the first substrate 100, and is in contact with the drain electrode 214b to form the passivation layer 231. And a pixel electrode 222 formed thereon.

In addition, a gate insulating film 221 and a protective film 231 are formed on the upper portion of the common wiring 320, and the insulating film 211 including the protective film 231 and the gate insulating film 221 is selectively removed. The second hole corresponds to the transparent electrode pattern 212 formed on the same layer as the pixel electrode 222 and the common electrode 223, so that the second hole has a shape that exposes the common wiring 320. It is formed to pass through the upper portion of the common wiring 320. The common wiring 320 and the transparent electrode pattern 212 are electrically connected to each other, and a conductive seal pattern 210 is formed on the common wiring 320 and the transparent electrode pattern 212. Here, a portion where the common wire 320 and the conductive seal pattern 210 are connected is a portion indicated by 'C' in FIG. 6, and an intersection point of the first connection wire 322 and the seal pattern 210 is shown. A contact portion having a transparent electrode pattern can be formed in such a structure as well. Here, it is assumed that both of the first connection wire 322 and the common wire 320 are metal layers formed on the same layer as the gate wire.

Here, the conductive seal pattern 210 may be formed on the first substrate 100 including the second substrate 200 or the transparent electrode pattern 212, but preferably, the second substrate 200 is flat. It is good to form on the surface.

On the second substrate 200 corresponding to the display area, a gate line and a data line, a black matrix layer 201 covering the thin film transistor forming region, a color filter layer 202 formed corresponding to at least the pixel area, and A common electrode 203 is formed on the entire surface of the second substrate 200 including the black matrix layer 201 and the color filter layer 202.

Third embodiment

8A and 8B are plan views illustrating common wires and first and second connection wires for applying a common voltage according to a third embodiment of the present invention, and FIG. 9 is a liquid crystal display according to a third embodiment of the present invention. WHEREIN: It is a top view which shows the connection relationship of common wiring and 1st, 2nd connection wiring, and an electroconductive seal pattern.

8A, the common wiring 320 and the first connection wiring 322 of the liquid crystal display according to the third exemplary embodiment of the present invention have the same shape as the second exemplary embodiment of the present invention described above. That is, the common wiring 320 is formed along the conductive seal pattern 210 of the letter '″'. The common wire 320 passing through the conductive seal pattern 210 is formed to be connected to an end of the data drive IC 120 and an end of the gate drive IC 110. Therefore, the common voltage applied to the gate drive IC 110 or the data drive IC 120 is common on the second substrate 200 through the common wiring 320 and the conductive seal pattern 210. The same level of common voltage is formed on the electrode 203. That is, since the common wiring 320 and the seal pattern 210 are provided, a stable DC voltage value applied through the gate drive IC 110 or the data drive IC 120 is the common electrode 203. To be applied). The apparatus further includes a first connection line 322 connected to the common line 320 adjacent to the gate drive IC 110. Here, the first connection wires 322 are formed to correspond to both ends of each gate drive IC 11, and a plurality of first connection wires 322 are provided, and the first connection wires are the same layer as the gate wires together with the common wire 320. It is a metal formed in.

In addition, the conductive seal pattern 210 and the intersection of the conductive seal pattern 210 and the common wiring 320, the intersection of the conductive seal pattern 210 and the first connection wiring 322, respectively, A transparent electrode pattern (see FIG. 7) is formed between the first and second contact portions ('D' portion of FIG. 9) to electrically connect the common wiring and the first connection wiring to the conductive seal pattern. .

In addition, as shown in FIG. 8B, a second connection is electrically connected to the first connection line 322 and the common line 320 from the data drive IC 120 and passes through an adjacent seal pattern 210. The wiring 321 is further included. The second connection wire 321 is a metal formed on the same layer as the data wire, and is connected to the second connection wire 321 from the portion adjacent to the gate drive IC 110 among the plurality of data drive ICs 120.

In addition, a second contact portion may be further provided at an intersection of the first connection wire 322 and the second connection wire 321, or in some cases, the first and second connection wires 322 and 321. The second contact portion between the first contact portion and the second connection wiring 321 and the conductive seal pattern 322 may be formed at the same site.

Here, the conductive seal pattern 210 includes conductive balls. For example, the conductive balls may include Au (gold) or Pt (platinum). In addition, the conductive seal pattern 210 is formed to surround the outside of the first substrate 100, thereby forming a uniform common voltage on the common electrode 203 of the second substrate 200.

Here, the common wire 320 passing through the conductive seal pattern 210 is formed to have a smaller width than the seal pattern 210. Here, since the conductive seal pattern 210 should include an epoxy resin or glass fiber in addition to the conductive balls therein, the conductivity will be lower than that of the common wiring 320, but since the conductive seal pattern 210 has a relatively wide width, the conductive seal A common voltage similar to that of the common wire 320 may be transferred to the pattern 210, thereby, the conductive seal pattern 210 surrounding edges of the first substrate 100 and the second substrate 200. By the shape, the common voltage of the same DC level will be applied to the common electrode 203 of the second substrate 200 as a whole.

In the third embodiment of the present invention, the remaining components except for the second connection wiring 321 are the same as the components of the second embodiment of the present invention and the functions thereof.

- Fourth Embodiment -

FIG. 10 is a plan view illustrating a seal pattern and a ground wiring in the liquid crystal display according to the fourth exemplary embodiment of the present invention.

As shown in FIG. 10, in the liquid crystal display according to the fourth exemplary embodiment, the feedback line 342 may be further formed on one side of the common line 341. The common wiring 341 and the feedback wiring 342 are both wirings 340 having a common voltage transfer function, and are formed on the same layer as the gate wirings.

In addition, the feedback wiring 342 is applied to the common wiring 341 by the common voltage applied through the data drive IC (see 120 of FIG. 6), and is separated by the wiring resistance while passing through the common wiring 341. The common voltage value is returned to the application point of the data drive IC 120 to function as a feedback wiring to transfer the compensated common voltage value back to the common wiring 341. The feedback wiring 342 is connected to an end of the common wiring 341 corresponding to an application point of the data drive IC 120 or a source PCB (not shown) for generating and transmitting a signal to the data driver 120. It can also be configured to connect directly to the side.

In the fourth embodiment of the present invention, the remaining components except for the feedback wiring 342 are the same as the components of the third embodiment of the present invention and the functions thereof.

11 is a circuit diagram schematically showing the upper and lower plate resistors of the present invention and a parallel configuration thereof.

As in the above-described second to fourth embodiments, when electrically connected to the conductive seal pattern 210 through the common wire 210 or 320, the first connection wire 322, and the second connection wire 321, The first resistor RL flowing in the common electrode 203 on the second substrate 200 and the second resistor flowing in the common wiring 220 or 320 are connected in parallel with respect to the conductive seal pattern 210. It is effective to divide the resistance as a whole, so that the DC voltage value (V) transmitted from the gate drive IC 110 or the data drive IC 120 is more stably applied to the common electrode 203. Delivered.

In addition, the manufacturing method of the liquid crystal display device of the present invention for achieving the same object will be described with reference to FIG. 3. Preparing a substrate 200, forming a gate wiring (not shown) and a data wiring (not shown) on the first substrate 100 so as to cross each other to define a pixel region, and the first and second Forming a conductive seal pattern 210 in a non-display area between the two substrates 100 and 200, and forming a gate driver 110 to apply a signal to the gate wiring in the non-display area of the first substrate. And forming a data driver 120 to apply a signal to the data line in the non-display area of the first substrate, and the conductive seal pattern 210 is formed on the first substrate 100. Work of the data driver 120 in place of the passing And forming a ground line 220 to be connected to one side of the gate driver 110 from a side.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

The liquid crystal display of the present invention as described above and a method of manufacturing the same have the following effects.

First, the ground wiring may be formed at a portion where the conductive seal pattern passes and electrically connected to the conductive seal pattern, thereby preventing staining due to DC potential instability in the panel through the potential stabilization of the ground wiring.

Second, by stabilizing the overall DC potential level of the panel, even if the ground voltage is applied to both the gate drive IC and the data drive IC, the overall resistance of the ground wiring is reduced, and the overall resistance is reduced, causing noisy signals to damage the gate drive IC. This can prevent the occurrence of gate-blocking shutdown (a boundary between gate drive ICs).

Third, the common wiring and the conductive seal pattern are equipotential, so that the conductive seal pattern may be used as another electrostatic supply wiring in the panel. The conductive seal pattern serves as a feedback function of a common wiring, and thus a more stable common voltage can be applied.

Fourth, the common wiring and the common electrode are connected in parallel by using a conductive seal pattern, thereby dividing the resistance imposed by the common electrode, thereby reducing the influence of the wiring resistance and forming a common voltage having a stable level.

Claims (24)

A first substrate and a second substrate opposed to each other, each having a display area at the center and a non-display area at the outside thereof; A conductive seal pattern formed in the non-display area between the first and second substrates; A plurality of gate lines and data lines crossing the first substrate to define pixel regions; A gate driver formed in the non-display area of the first substrate to apply a signal to each of the gate lines; A data driver formed in the non-display area of the first substrate to apply a signal to each of the data wires; And And a ground line electrically connected to the conductive seal pattern on the non-display area on the first substrate and formed to be connected from one side of the data driver to one side of the gate driver. The method of claim 1, And the ground line is formed to pass through the conductive seal pattern formed to correspond to sides on which the gate driver and the data driver are not formed. 3. The method of claim 2, An insulating film having a hole is formed between the ground wiring and the conductive seal pattern, and a transparent electrode pattern is formed on the hole, and a contact portion for electrically connecting the ground wiring and the conductive seal pattern is further formed. Liquid crystal display. The method of claim 1, The conductive seal pattern comprises a conductive ball, characterized in that the liquid crystal display device. 5. The method of claim 4, The conductive ball is a liquid crystal display device comprising Au (gold) or Pt (platinum). The method of claim 1, And wherein the ground line passing through the conductive seal pattern has a smaller width than the seal pattern. The method of claim 1, And a common electrode and a pixel electrode having alternate shapes are formed in each pixel area on the first substrate. The method of claim 1, And a common electrode formed on each of the pixel regions on the first substrate, and a common electrode formed on the front surface of the second substrate. The method of claim 1, And the ground line further includes a feedback line on one side thereof to enter an end portion of the data driver. The method of claim 1, And the ground wiring is formed on the same layer as the gate wiring or data wiring. A first substrate and a second substrate opposed to each other, each having a display area at the center and a non-display area at the outside thereof; A conductive seal pattern formed in the non-display area between the first and second substrates; A plurality of gate lines and data lines crossing the first substrate to define pixel regions; A pixel electrode formed in each pixel area on the first substrate; A common electrode formed on the entire surface of the second substrate; A gate driver formed in the non-display area of the first substrate to apply a signal to each of the gate lines; A data driver formed in the non-display area of the first substrate to apply a signal to each of the data wires; And And a common wiring electrically connected to the common electrode through the conductive seal pattern, and configured to connect one side of the gate driver and one side of the data driver to a non-display area on the first substrate. Device. 12. The method of claim 11, And the common wiring is formed to pass through the conductive seal pattern. 12. The method of claim 11, And the common wiring further includes a feedback wiring to enter one end of the data driver on one side thereof. 12. The method of claim 11, And the common wiring is made of the same metal as the gate wiring. 12. The method of claim 11, And a first connection line connected to the common line adjacent from the gate driver. 16. The method of claim 15, And a plurality of first connection lines. 16. The method of claim 15, And the first connection line is a metal formed on the same layer as the gate line. 16. The method of claim 15, At the intersection of the conductive seal pattern and the common wiring and the intersection of the conductive seal pattern and the first connection wiring, A transparent electrode pattern is formed between the conductive seal pattern and the first contact portion electrically connecting the common wiring and the first connection wiring to the conductive seal pattern, respectively. 16. The method of claim 15, And a second connection line electrically connected to the first connection line and the common line from the data driver and formed to pass through an adjacent seal pattern. The method of claim 19, And the second connection wiring is a metal formed on the same layer as the data wiring. The method of claim 19, And a second contact portion at an intersection portion of the first connection line and the second connection line. 12. The method of claim 11, The conductive seal pattern comprises a conductive ball, characterized in that the liquid crystal display device. 23. The method of claim 22, The conductive ball is a liquid crystal display device comprising Au (gold) or Pt (platinum). 13. The method of claim 12, And the common wiring passing through the conductive seal pattern has a smaller width than the seal pattern.

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