KR101295900B1 - Phase detector and phase locked loop comprising the same - Google Patents

Abstract

PURPOSE: A phase detector and a phase-locked loop including the same are provided for clock and data recovery (CDR) which is operated at high speed. CONSTITUTION: A phase detector includes first flip-flops (FF1_0-FF1_2N-1), second flip-flops (FF2_0-FF2_2N-1), and XOR gates (X_0-X_2N-1). The 2N first flip-flops are connected to each other in parallel to receive the same data and 2N clock signals having phases that are different from each other. The 2N second flip-flops are connected to each other in parallel and respectively connected to the output end of each of the 2N first flip-flops so as to receive the same clock signal. The 2N XOR gates are each connected to the output ends of one pair of the second flip-flops that are adjacent to each other. [Reference numerals] (11) First counter; (12) Second counter; (2) Decimator; (3-1) Loop filter; (5,5-1) Dispenser

Description

Phase detector and phase locked loop comprising the same

The present invention relates to a phase detector and a phase locked loop including the same.

Phase detectors are used in many applications, such as phase locked loops (PLLs) and clock and data recovery (CDR). This phase detector is a kind of comparator that takes a signal input with two frequencies and finds out how much phase difference there is between the two signals.

On the other hand, the phase detector is divided into a nonlinear phase detector and a linear phase detector.

The nonlinear phase detector only detects whether the phase is early or late, and the linear phase detector can detect how advanced or how high the phase is.

In addition, Patent No. 10-2010-0054582 (Phase Detector), which can be implemented with a minimum number of circuit elements, introduces a phase detector that can minimize device size, power consumption, and operation time.

 In the preceding document, a phase detector is constructed using two edge detectors and one SR latch circuit, and each block of the edge detector and SR latch circuit is configured with a minimum number of transistors, thereby minimizing power consumption of the phase detector. A phase detector is introduced that can significantly reduce device size.

Meanwhile, with the development of high-speed data communication systems such as optical communication, backplane routing, and chip-to-chip interconnections, the importance of how to recover data and clocks is increasing.

In general, a CDR circuit or a phase locked loop (PLL) is used for data / clock recovery. In the data recovery process at the data receiving side, a phase detector is used to synchronize the recovery clock with the data to be restored. Restore the data. Therefore, the role of the phase detector in correctly restoring data in a phase locked loop or the like is very important, and the operation speed of the CDR is also determined by the phase detector.

Accordingly, there is a need for a phase detector applicable to a CDR or phase locked loop for high speed data communication.

Patent 10-2010-0054582 (Phase Detector)

The present invention has been made to solve the problems of the prior art, the present invention can provide a phase detector that can be applied to a CDR or a phase locked loop and a phase locked loop to which it is applied.

According to an aspect of the present invention, 2N first terminals connected in a parallel structure receiving the same data and receiving 2N clock signals CLK _i (0 ≦ _i ≦ 2N−1) having different phases. Flip-flops FF1 ₀ , FF1 ₁ ,. , FF1 _{2N -1} ; 2N second flip-flops FF2 ₀ , FF2 ₁ ,..., 2N connected to the output terminals of the 2N first flip-flops, respectively, connected in parallel to receive the same clock signal C. , FF2 _{2N -1} ; 2N exclusive OR (XOR) gates X ₀ , X ₁ ,... Each connected to an output terminal of the pair of second flip-flops adjacent to each other. , X _{2N -1} ; A first output unit configured to receive an output of X _2j (0 ≦ _j ≦ N−1) of the 2N XOR gates and output a down signal DN; And a second output unit configured to receive an output of X _{2j +1} (0 ≦ _j ≦ N−1) among the 2N XOR gates and output an up signal UP.

The first output unit may be a counter that counts the number of zeros or counts one of the outputs of each of X _2j (0 ≦ _j ≦ N-1), which are input N signals, and the second output unit is a counter. The counter may count the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which are input N signals.

The first output unit may be an OR gate that ORs each of the outputs of the X _2j (0 ≦ _j ≦ N−1), which are N signals input to the first output unit, and the second output unit may be configured as the second output unit. It may be an OR gate for ORing the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which are N signals input to an output unit.

In addition, when X _2j = 1 X _{2j +1} , the counter and the OR gate may not be used.

In addition, the clock signals CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i + 1} may have a phase difference of π / N.

In addition, the clock signal C commonly applied to the 2N second flip-flops may have the same frequency as the clock signal CLK _i .

Each XOR gate X _k (0 ≦ _k ≦ 2N−1) may receive an output signal of the second flip-flops FF2 _k and FF2 _{((k + 1) mod 2N)} .

According to another aspect of the present invention, 2N flips connected in parallel to receive the same data and receive 2N clock signals CLK _i (0 ≦ _i ≦ 2N-1) having different phases. Flop FF ₀ , FF ₁ ... , FF _{2N −1 ,;} 2N exclusive OR (XOR) gates X ₀ , X ₁ ,... Each connected to an output terminal of the pair of flip-flops adjacent to each other. , X _2N-1 ; A first output unit configured to receive one of the outputs DN <0> to DN <N-1> of the 2N XOR gates X _2j (0 ≦ _j ≦ N−1) and output a down signal DN; And a second detector configured to receive an output of X _{2j +1} (0 ≦ _j ≦ N−1) among the 2N XOR gates and output an up signal UP. A decimator receiving the output of the first output unit and the second output unit; And a divider for dividing a clock signal C having the same frequency as the clock signal CLK _i and applying it to a clock input terminal of the decimator. A phase locked loop is provided, wherein the divider ratio of the divider is used from one.

The first output unit may be a counter that counts the number of zeros or counts one of the outputs of each of X _2j (0 ≦ _j ≦ N-1), which are input N signals, and the second output unit is a counter. The counter may count the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which are input N signals.

The first output unit may be an OR gate that ORs each of the outputs of the X _2j (0 ≦ _j ≦ N−1), which are N signals input to the first output unit, and the second output unit may be configured as the second output unit. It may be an OR gate for ORing the outputs of the respective X _2j (0 ≦ _j ≦ N−1), which are N signals input to an output unit.

In addition, the clock signals CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i + 1} may have a phase difference of π / N.

Each XOR gate X _k (0 ≦ _k ≦ 2N−1) may receive an output signal of the flip-flops FF _k and FF _{((k + 1) mod 2N)} .

According to another aspect of the present invention, 2N flip-flops connected in parallel in parallel receiving 2N clock signals CLK _i (0 ≦ _i ≦ 2N-1) having the same data and having different phases. FF ₀ , FF ₁ ,... , FF _{2N -1} , 2N exclusive OR (XOR) gates X ₀ , X ₁ ,..., Each connected to an output terminal of the pair of flip-flops adjacent to each other. , X _{2N -1} , a first output unit configured to receive an output of X _2j (0 ≦ _j ≦ N−1) of the 2N XOR gates and output a down signal DN, and X _2j of the 2N XOR gates A phase detector including a second output unit configured to receive an output of ₊₁ (0 ≦ j ≦ N−1) and output a down signal DN; A loop filter configured to receive outputs of the first output unit and the second output unit; And a divider for dividing a clock signal C having the same frequency as the clock signal CLK _i and applying it to a clock input terminal of the loop filter.

The first output unit may be a counter that counts the number of zeros or the number of ones among the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are input N signals, and the second output unit is a counter. The counter may count the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which are input N signals.

The first output unit is an OR gate that ORs each of the outputs of the X2j (0 ≦ j ≦ N−1), which are N signals input to the first output unit, and the second output unit is the second output unit. It may be an OR gate that ORs the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are N signals inputted negatively.

In addition, the clock signals CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i + 1} may have a phase difference of π / N.

Each XOR gate X _k (0 ≦ _k ≦ 2N−1) may receive an output signal of the flip-flops FF _k and FF _{((k + 1) mod 2N)} .

According to an embodiment of the present invention, it is possible to provide a phase detector applicable to a CDR and a phase locked loop operating at a high speed and a phase locked loop to which the same is applied.

1 is a block diagram illustrating a digital phase locked loop according to an embodiment of the present invention.
2 to 5 are circuit diagrams illustrating phase detectors according to different embodiments of the present invention, respectively.
6 to 7 are timing diagrams for describing an operation of a phase detector according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[Description of Fig. 1]

1 is a block diagram illustrating a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 1, a phase locked loop according to an embodiment of the present invention includes a phase detector 1, a decimator 2, a digital loop filter 3, and digitally controlled DCO. Oscilator; 4).

The phase detector 1 compares the phase of the input data signal with the phase of the output signal, and can generate a pulse indicating early or late for each transition of the data pulse. The lock condition of the phase locked loop is that the average number of the advance pulse and the ground pulse is the same. A phase detector according to various embodiments of the present invention will be described in more detail later with reference to FIGS. 2 to 5.

The decimator 2 is a module that reduces data by lowering a sampling rate of a signal. The decimator (2) a predetermined decimation coefficient can be set, the decimation coefficient means the ratio of the output rate to the input rate.

In one embodiment, the decimator may be implemented with a finite impulse response (FIR) structure, and in particular, may be implemented with a FIR boxcar filter.

In one embodiment, the decimator 2 may be implemented to sum data for a period corresponding to the decimation coefficients (decimation by summing). When implemented in this way, there is no loss in data input to the decimator 2, and there is no change in the loop gain of the proportional path.

In another embodiment, the decimator 2 may be implemented to take input data at a set period of decimation coefficients and discard the remaining data (down sampling). That is, in this case, the decimator 2 can select any one of the decimation coefficient L data samples to determine whether it is the truth or the ground.

If the decimation coefficient of the decimator is 1, the decimator may be omitted.

In another embodiment, the decimator 2 may determine whether the fact is the ground or the ground using the sign of the data calculated from the data decimation by summing.

The configuration of the phase locked loop according to the embodiment of the present invention has been described above. Hereinafter, various embodiments of the phase detector according to the present invention will be described with reference to FIGS. 2 to 5.

[Description of FIGS. 2 and 3]

2 is a circuit diagram illustrating an example of a phase detector according to an embodiment of the present invention.

Referring to FIG. 2, the phase detector 1 according to an embodiment of the present invention includes 2N first flip-flops FF1 ₀ , FF1 ₁ ,. , FF1 _{2N -1} . In addition, the phase detector 1 includes 2N (N is a natural number) second flip-flops FF2 ₀ , FF2 ₁ ,..., Respectively connected to the output terminals of the 2N first flip-flops. , _2N XOR gates X ₀ , X ₁ ,..., Respectively connected to the output terminals of the pair of second flip-flops adjacent to each other, FF 2 _{2N −1} . , X _{2N -1} may be included.

Referring to FIG. 2, the 2N first flip-flops FF1 ₀ , FF1 ₁ ,... , FF1 _{2N - 1} may be connected in parallel to each other, and the 2N second flip-flops FF2 ₀ , FF2 ₁ ,. , FF2 _2N-1 and the 2N XOR gates X ₀ , X ₁ ,. , X _{2N -1} are also connected in parallel.

In detail, the group of circuit units including the first flip-flop FF1 _i (0 ≦ _i ≦ 2N−1), the second flip-flop FF2 _i and the XOR gate X _i may be connected to each other in parallel.

Meanwhile, the 2N first flip-flops FF1 ₀ , FF1 ₁ ,... , FF1 _{2N -1} receives the same data data, and the first flip-flop FF1 _i (0≤i≤2N-1) can receive clock signals CLK <i> having different phases at each clock input terminal. .

In a particular embodiment, the clock signals CLK <i> (0 ≦ i ≦ 2N−1) and CLK <i + 1> may have a phase difference of 2π / 2N. For example, when the phase detector 1 is composed of eight circuit units, CLK <0> and CLK <1>, CLK <1> and CLK <2>,... , CLK <6> and CLK <7> may have a phase difference of 45 degrees.

The 2N second flip-flops FF2 ₀ , FF2 ₁ ,... , FF2 _{2N -1} can receive the same clock signal CLK <X> at the clock input terminal, and the second flip-flop FF2 _i (0≤i≤2N-1) can receive the output of the first flip-flop FF1 _i . have. In a particular embodiment, the clock signal CLK <X> commonly applied to the 2N second flip-flops may have the same frequency as the clock signal CLK <i>.

Further, the XOR gates X ₀ , X ₁ ,... , X _{2N - 1} may be respectively connected to the output terminals of the pair of second flip-flops adjacent to each other. In a particular embodiment, each XOR gate X _k (0 ≦ _k ≦ 2N−1) may receive an output signal of the second flip-flops FF2 _k and FF2 _{((k + 1) mod 2N)} .

On the other hand, the phase detector 1 according to an embodiment of the present invention is a signal of the output (DN <0> to DN <N-1>) of X _2j (0≤j≤N-1) of the 2N XOR gates A first output unit for receiving any one of the signals and outputting the down signal DN and outputs of X _{2j +1} (0 ≦ _j ≦ N−1) among the 2N XOR gates (UP <1> to UP <N) It may further include a second output unit for receiving any one of the signals of -1>) and outputs the up signal (UP).

In the embodiment of FIG. 2, the first output unit and the second output unit may be a first counter 11 and a second counter 12, respectively.

When the first output unit and the second output unit are implemented as counters, the first counter 11 is the number of 1 of each of the outputs of each of X _2j (0 ≦ _j ≦ N−1), which is N signals inputted. The second counter 12 may count the number of 1 of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which is an input N signal.

However, the present invention is not limited thereto, and each counter may be implemented to count the number of zeros instead of ones. Thus, in the embodiment of FIG. 1, the up signal and the down signal may consist of log ₂ (2N-1) bits rather than 1 bit outputs (ie, 0 or 1).

In addition, when X _2j = 1 X _{2j +1} = 1, the counter may not be used.

The phase detector according to the present embodiment uses all phase error information and does not affect the overall loop parameter.

3 is a circuit diagram illustrating an example of a phase detector according to another embodiment of the present invention.

In the embodiment shown in FIG. 3, the phase detector 1 has the remainder except that the above-described first and second output portions are composed of a first OR gate 15 and a second OR gate 16, respectively. The components are the same as those shown in FIG. In the embodiment of FIG. 3, the first output unit generates a down signal by ORing the signals from DN <0> to DN <N-1>, and the second output unit generates a down signal from UP <0> to UP <N-1>. The up signal can be generated by ORing the signals. Thus, in the present embodiment, both the down signal and the up signal can be configured with one bit of output.

In addition, when X _2j = 1 X _{2j +1} = 1, the OR gate may not be used.

[Description of FIGS. 4 and 5]

4 and 5 are circuit diagrams each illustrating an embodiment of a phase detector and part of a satellite locked loop including the same according to the present invention.

Referring to FIG. 4, the phase detector 1 according to an embodiment of the present invention receives the same data data and has 2N clock signals CLK <i> (0 ≦ i ≦) having different phases. 2N flip-flops FF ₀ , FF ₁ ,... FF _2N-3 and 2N-3 exclusive OR (XOR) gates X ₀ , X ₁ ,..., Respectively connected to the output terminals of the pair of flip-flops adjacent to each other. , X _{2N -3} .

Some signals are not used in one embodiment of the present invention.

Referring to FIG. 4, the last two flip-flops FF _{2N- 1} FF _{2N- 2} are configured in a floting state.

In a particular embodiment, the clock signals CLK <i> (0 ≦ i ≦ 2N−1) and CLK <i + 1> may have a phase difference of 2π / 2N.

4, the 2N flip-flops FF ₀ , FF ₁ ,... , FF _{2N - 1} may be connected in parallel with each other.

The phase detector 1 according to an embodiment of the present invention may include any one of the outputs DN <0> to DN <N-1> of X _2j (0 ≦ _j ≦ N−1) of the 2N XOR gates. A first output unit for receiving a signal and outputting a down signal DN and an output (UP <1> to UP <N-1> of X _{2j +1} (0 ≦ _j ≦ N-1) among the 2N XOR gates) The display apparatus may further include a second output unit configured to receive any one of the signals and output the up signal UP.

In the embodiment shown in FIG. 4, the first output unit and the second output unit may be implemented as counters. That is, when the first output unit and the second output unit are implemented as counters, the first counter 11 is one of the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are N signals inputted. The second counter 12 may count the number of 1 of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N−1), which is an input N signal. However, the present invention is not limited thereto, and each counter may be implemented to count the number of zeros instead of ones.

Meanwhile, the phase locked loop including the phase detector 1 illustrated in FIG. 4 includes the decimator 2 and the clock signal CLK <receiving the outputs of the first counter 11 and the second counter 12. A divider 5 for dividing the clock signal CLK <X> having the same frequency as i> and applying it to the clock input terminal of the decimator 2 is included.

The division ratio of the divider starts from 1, and as the division ratio of the divider 5 increases, the loss of phase error information increases.

Referring to FIG. 4, current consumption may be reduced as the gate is reduced by selectively using only a few signals without using all of the UP / DN signals.

FIG. 5 is a diagram illustrating an example of a phase detector having a configuration similar to that of the phase detector shown in FIG. 4 and a part of a satellite fixed loop including the same;

In comparison with FIG. 4, in the phase detector shown in FIG. 5, the first output unit and the second output unit may be implemented as OR gates instead of a counter. Since the description of the case where the first output unit and the second output unit are implemented as the OR gate has been described above, a detailed description thereof will be omitted.

[Description of Fig. 6]

6 and 7 are timing diagrams for describing an operation of a phase detector according to an exemplary embodiment of the present invention. 6 and 7 show an example of the operation of the phase detector 1 according to FIG. 2, where N is set to 4, and the decimator 2 is a FIR Boxcar structure, and assumes a decimation coefficient of 2. FIG. do.

FIG. 6 shows an example where the clock phase is fast, and FIG. 7 shows an example where the clock phase is slow.

When N is 4, for example, it is preferable that the clock 45 (CLK45) be in the middle of the data being patched. In other words, sampling in the middle of the data is desirable in a high speed clock environment due to the influence of data noise. Especially in circuits required for high-speed communications such as CDRs, clocks can be sampled in relation to incoming data in order to perform synchronized operations (e.g., retiming or demultiplexing) on asynchronous data. Should be created to best suit the However, when an edge of the clock occurs at the midpoint of each data bit, sampling may occur with the largest margin from the previous data transition and the following data transition. Therefore, timing uncertainty can be minimized.

However, in FIG. 6, the rising edge of the clock 45 CLK45 is slightly faster than the middle point of the data bit, and in FIG. 7, the rising edge of the clock 45 CLK45 is slightly slower than the middle point of the data bit. have.

Referring to FIG. 6 (Clock Early), first, eight second flip-flops FF2 ₀ , FF2 ₁ ,. The bits 0, 1, 1, 0, 0, 1, 1, and 1 are sequentially output from, FF2 ₇ . Then, in the XOR gates X ₀ , X ₂ , X ₄ , and X ₆ for generating the down signal, 1, 1, 1, 0 are output as DN <0> to DN <3>, and the number of 1 of the output signals is output. a 3 is output as a down signal, the X _1, X ₃ XOR gates for generating an up signal, X _5, X ₇ the output of 0, 0, 0, 0 as uP <0> to uP <3> 0, which is the number of 1s among the output signals, is output as an up signal.

Second flip-flops FF2 ₀ , FF2 ₁ ,... At the timing (rising edge) of the next CLK <X>. From FF2 ₇ , the bits 1, 0, 0, 1, 1, 0, 0, 0 are sequentially output. Then, in the XOR gates X ₀ , X ₂ , X ₄ , and X ₆ for generating the down signal, 0, 1, 1, 1 are output as DN <0> to DN <3>, and the number of 1 of the output signals is obtained. a 3 is output as a down signal, the X _1, X ₃ XOR gates for generating an up signal, X _5, X ₇ the output of 0, 0, 0, 0 as uP <0> to uP <3> 0, which is the number of 1s among the output signals, is output as an up signal.

Then, as previously assumed, since the decimation coefficient of the decimator 2 is set to 2, the decimator 2 selects the first input DN: 3, UP: 0 and the next input DN: 3, UP: 0. The clock generated by the DCO may be adjusted by applying the input and adding the output of −6 to the loop filter 3.

Referring to FIG. 7 (Clock Late), first, eight second flip-flops FF2 ₀ , FF2 ₁ ,. The bits 1, 1, 0, 0, 1, 1, 1, and 1 are sequentially output from, and FF2 ₇ . Then, in the XOR gates X ₀ , X ₂ , X ₄ , and X ₆ for generating the down signal, 0, 0, 0, 0 are output as DN <0> to DN <3>, and the number of 1 of the output signals is obtained. 0 this is output as the down signal, the X _1, X ₃ XOR gates for generating an up signal, X _5, X ₇ the output of 1, 1, 0 and 1 as the uP <0> to uP <3> 3, which is the number of 1 of the output signals, is output as an up signal.

Second flip-flops FF2 ₀ , FF2 ₁ ,... At the timing (rising edge) of the next CLK <X>. The bits 0, 0, 1, 1, 0, 0, 0, and 0 are sequentially output from, and FF2 ₇ . Then, in the XOR gates X ₀ , X ₂ , X ₄ , and X ₆ for generating the down signal, 0, 0, 0, 0 are output as DN <0> to DN <3>, and the number of 1 of the output signals is obtained. 0 this is output as the down signal, the X _1, X ₃ XOR gates for generating an up signal, X _5, X ₇ the output of 1, 1, 0 and 1 as the uP <0> to uP <3> 3, which is the number of 1 of the output signals, is output as an up signal.

Then, as previously assumed, since the decimation coefficient of the decimator 2 is set to 2, the decimator 2 selects the first inputs DN: 0, UP: 3 and the next inputs DN: 0, UP: 3 The clock generated by the DCO may be adjusted by applying the sum of the inputs and applying the output of 6 to the loop filter 3.

The above has been described with respect to the case of the phase detector mainly an embodiment of the present invention, those skilled in the art of the present invention from the examples of Figures 6 and 7 The function will be easy to apply.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

1: phase detector
2: decimator
3, 3-1: loop filter
4: Digially Controlled Oscilator
5, 5-1: Divider
11, 12: counter
15, 16: OR gate

Claims (18)

2N first flip-flops FF1 ₀ , FF1 ₁ , connected in parallel, receiving the same data and receiving 2N clock signals CLK _i (0 ≦ _i ≦ 2N−1) having different phases. … , FF1 _{2N -1} ;
2N second flip-flops FF2 ₀ , FF2 ₁ ,..., 2N connected to the output terminals of the 2N first flip-flops, respectively, and connected in parallel to receive the same clock signal C. , FF2 _{2N -1} ;
2N exclusive OR (XOR) gates X ₀ , X ₁ ,... Each connected to an output terminal of the pair of second flip-flops adjacent to each other. , X _{2N -1} ;
A first output unit configured to receive an output of X _2j (0 ≦ _j ≦ N−1) of the 2N XOR gates and output a down signal DN; And
And a second output unit configured to receive an output of X _{2j +1} (0 ≦ _j ≦ N−1) of the 2N XOR gates and output an up signal UP.
The method of claim 1,
The first output unit,
A counter that counts the number of zeros or the number of ones of the outputs of each of X _2j (0 ≦ _j ≦ N-1), which is an input N signal,
The second output unit,
A phase detector, which is a counter that counts the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N-1), which is an input N signal.
The method according to claim 2, wherein
Phase detector characterized in that no counter is used when X _2j = 1 or X _{2j +1} = 1
The method of claim 1,
The first output unit,
OR gates for ORing the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are N signals input to the first output unit,
The second output unit,
And an OR gate for ORing each of the outputs of X _{2j +1} (0 ≦ _j ≦ N−1), which are N signals input to the second output unit.
5. The method of claim 4,
Phase detector characterized in that OR gate is not used when X _2j = 1 or X _{2j +1} = 1
The method of claim 1,
And the clock signals CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i +} 1 have a phase difference of π / N.
The method according to claim 6,
And a clock signal C commonly applied to the 2N second flip-flops has the same frequency as the clock signal CLK _i .
The method of claim 1,
Each XOR gate X _k (0 ≦ _k ≦ 2N−1) _receives an output signal of the second flip-flop FF2 _k and FF2 _{((k + 1) mod 2N)} ;
2N flip-flops FF ₀ , FF ₁ ,... Connected in parallel receiving the same data and receiving 2N clock signals CLK _i (0 ≦ _i ≦ 2N−1) having different phases. , FF _2N-1 ;
2N exclusive OR (XOR) gates X ₀ , X ₁ ,... Each connected to an output terminal of the pair of flip-flops adjacent to each other. , X _2N-1 ;
A first output unit configured to receive one of the outputs DN <0> to DN <N-1> of the 2N XOR gates X _2j (0 ≦ _j ≦ N−1) and output a down signal DN;
A phase detector including a second output unit configured to receive an output of X _{2j + 1} (0 ≦ _j ≦ N−1) of the 2N XOR gates and output an up signal UP;
A decimator receiving the output of the first output unit and the second output unit; And
A divider for dividing a clock signal C having the same frequency as the clock signal CLK _i and applying it to a clock input terminal of the decimator (where the division ratio of the divider is used from 1);
Phase locked loop comprising a. 10. The method of claim 9,
The first output unit,
A counter that counts the number of zeros or the number of ones of the outputs of each of X _2j (0 ≦ _j ≦ N-1), which is an input N signal,
The second output unit,
A phase locked loop, which is a counter that counts the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N-1), which are input N signals.
10. The method of claim 9,
The first output unit,
OR gates for ORing the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are N signals input to the first output unit,
The second output unit,
And an OR gate for ORing the outputs of each of the X _2j (0 ≦ _j ≦ N−1) signals, which are N signals input to the second output unit.
10. The method of claim 9,
The clock signal CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i +} 1 having a phase difference of π / N.
10. The method of claim 9,
Each XOR gate X _k (0 ≦ _k ≦ 2N−1) _receives an output signal of the flip-flops FF _k and FF _{((k + 1) mod 2N)} .
2N flip-flops FF ₀ , FF ₁ ,... Connected in parallel, receiving the same data, and receiving 2N clock signals CLK _i (0 ≦ _i ≦ 2N−1) having different phases. , FF _2N-1 ;
2N exclusive OR (XOR) gates X ₀ , X ₁ ,... Each connected to an output terminal of the pair of flip-flops adjacent to each other. , X _2N-1 ;
A first output unit configured to receive one of the outputs DN <0> to DN <N-1> of the 2N XOR gates X2j (0 ≦ j ≦ N−1) and output a down signal DN;
A phase detector including a second output unit configured to receive an output of X2j + 1 (0 ≦ j ≦ N−1) of the 2N XOR gates and output an up signal UP;
A loop filter configured to receive outputs of the first output unit and the second output unit; And
A divider for dividing a clock signal C having the same frequency as the clock signal CLK _i and applying it to a clock input terminal of the loop filter (where the division ratio of the divider is used from 1);
Phase locked loop comprising a. 15. The method of claim 14,
The first output unit,
A counter that counts the number of zeros or the number of ones of the outputs of each of X _2j (0 ≦ _j ≦ N-1), which is an input N signal,
The second output unit,
A phase locked loop, which is a counter that counts the number of zeros or the number of ones of the outputs of each of X _{2j +1} (0 ≦ _j ≦ N-1), which are input N signals.
15. The method of claim 14,
The first output unit,
OR gates for ORing the outputs of each of X _2j (0 ≦ _j ≦ N−1), which are N signals input to the first output unit,
The second output unit,
And an OR gate for ORing the outputs of each of the X _2j (0 ≦ _j ≦ N−1) signals, which are N signals input to the second output unit.
15. The method of claim 14,
The clock signal CLK _i (0 ≦ _i ≦ 2N−1) and CLK _{i +} 1 having a phase difference of π / N.
15. The method of claim 14,
Each XOR gate X _k (0 ≦ _k ≦ 2N−1) _receives an output signal of the flip-flops FF _k and FF _{((k + 1) mod 2N)} .

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