KR101295468B1 - Light emitting device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A light emitting device and a method for fabricating the same are provided to reduce defects by burying a thin n-type electrode in a recessed part. CONSTITUTION: A p-type semiconductor layer is formed on an active layer. A p-type electrode (900) is formed on the p-type semiconductor layer. An n-type electrode (400) is formed in an n-type semiconductor layer. An n-type pad (800) is arranged on the exposed surface of the n-type semiconductor layer. An insulating layer is formed on the n-type electrode.

Description

Light Emitting Device and Method of Fabricating the Same

The present invention relates to a light emitting device and a method of manufacturing the same, and more particularly, to a light emitting device including an electrode inside the light emitting device.

Light-emitting diodes (LEDs) are a type of p-n junction diodes, and are semiconductor devices using electroluminescence, a phenomenon in which a monochromatic light is emitted when a voltage is applied in a forward direction.

In recent years, nitride semiconductor compound semiconductors are used to achieve high brightness. That is, a blue quantum well structure is adopted between GaN-based compound semiconductors to implement blue light, and a fluorescent material is introduced on the top to realize white light.

The operation of the light emitting diode is a mechanism in which a voltage is applied to two electrodes represented by an anode and a cathode, and a light emitting operation is performed by supplying a current according to the application of the voltage. In particular, an n-type semiconductor layer and a p-type semiconductor layer are in contact with the upper and lower portions of the active layer in which the multi-quantum well structure is formed. The n-type semiconductor layer supplies electrons to the active layer, and the p-type semiconductor layer supplies holes to the active layer. Electrons and holes injected into the multi-quantum well structure are defined inside the well layer by the quantum confinement effect, and light emission operation is performed by recombination.

When fabricating a conventional horizontal light emitting diode, a portion of the p-type semiconductor layer and the active layer are etched to form an electrode on the n-type semiconductor surface, thereby reducing the area of the active layer and reducing the surface area emitted. do.

In addition, an electrode is formed in a portion of the n-type semiconductor surface, thereby causing a problem of current density.

Korean Patent Laid-Open No. 10-2005-0093876 (September 23, 2005) discloses a technique of increasing the surface area emitted by forming at least one through hole in a sapphire substrate and forming an n-type electrode in the through holes. . However, in this case, since the n-type electrode is connected to the buffer layer and not directly connected to the n-type semiconductor layer, current injection is not efficient.

Therefore, there is a need for the development of a light emitting device capable of minimizing the reduced area of the active layer, increasing the surface area emitted, and improving the current injection effect.

The technical problem to be solved by the present invention is to provide a light emitting device that can minimize the reduced area of the active layer, increase the surface area to be emitted, and improve the current injection effect.

One aspect of the present invention to achieve the above technical problem is a substrate; An n-type semiconductor layer formed on the substrate; An active layer formed on the n-type semiconductor layer; A p-type semiconductor layer formed on the active layer; A p-type electrode formed on the p-type semiconductor layer; An n-type electrode formed inside the n-type semiconductor layer; And an n-type pad in contact with the n-type electrode and disposed on an exposed surface of the n-type semiconductor layer, wherein the thickness of the n-type semiconductor layer below the n-type electrode is 1 μm to 5 μm. do.

The semiconductor device may further include an insulating layer formed inside the n-type semiconductor layer and formed on the n-type electrode.

The insulating layer is characterized in that the current spreads to the lower side and the side of the n-type electrode.

The width of the n-type electrode may be 3㎛ to 10㎛.

The n-type electrode may have a thickness of 0.5 μm to 5 μm.

A buffer layer may be further included between the substrate and the n-type semiconductor layer.

A current diffusion layer may be further included between the p-type semiconductor layer and the p-type electrode.

The n-type electrode may include any one selected from the group consisting of Ni, Cr, W, Rh, In, Au, Sn, Zr, Ta, Al, Ti, and compounds thereof.

The insulating layer may include any one selected from the group consisting of SiO ₂ , silicon nitride, silicide, gallium nitride, and a rare earth material.

Another aspect of the present invention to achieve the technical problem is preparing a substrate; Forming an n-type semiconductor layer in which an n-type electrode is embedded on the substrate; Forming an active layer on the n-type semiconductor layer; Forming a p-type semiconductor layer on the active layer; Exposing a portion of the n-type semiconductor layer to form an n-type pad in contact with the n-type electrode; And forming a p-type electrode on the p-type semiconductor layer, wherein the thickness of the n-type semiconductor layer below the n-type electrode is 1 μm to 5 μm.

The forming of the n-type semiconductor layer may include forming an n-type semiconductor layer on the substrate; Forming a recess on a surface of the n-type semiconductor layer; Forming an n-type electrode filling at least a portion of the recess; And re-growing the n-type semiconductor layer to cover the n-type electrode.

The forming of the n-type pad may include etching the portions of the p-type semiconductor layer, the active layer, and the n-type semiconductor layer so that a portion of the n-type electrode is exposed to the outside; And forming an n-type pad on the exposed surface of the n-type semiconductor layer to contact the n-type electrode.

Prior to forming the n-type semiconductor layer, the method may further include forming a buffer layer on the substrate.

The method may further include forming a current spreading layer on the p-type semiconductor layer between the forming of the p-type semiconductor layer and the forming of the n-type pad.

As described above, according to the present invention, by forming the n-type electrode inside the n-type semiconductor layer, it is possible to minimize the reduced area of the active layer, increase the surface area emitted light to improve the light extraction efficiency of the light emitting device.

In addition, the thickness of the n-type electrode may be formed to be reduced to reduce the amount of emitted light.

In addition, by adjusting the position and size of the n-type electrode, and forming an insulating layer on the n-type electrode to improve the effect of current spreading and current injection can improve the light extraction efficiency of the light emitting device.

In addition, the width of the n-type electrode is designed to be thin and embedded in the concave portion of the n-type semiconductor layer, thereby reducing defects or voids that may occur in the regrowth process of the n-type semiconductor layer. have.

However, the effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view of a light emitting device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the light emitting device of FIG. 1 taken along the line II ′. FIG.
3 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention according to a process step.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Example 1

1 is a cross-sectional view of a light emitting device according to an embodiment of the present invention.

Referring to FIG. 1, a buffer layer 200, an n-type semiconductor layer 300, an active layer 500, a p-type semiconductor layer 600, a current diffusion layer 700, and a p-type electrode 900 are formed on a substrate 100. In this order, the n-type electrode 400 is formed in the n-type semiconductor layer 300. In addition, an n-type pad 800 in contact with the n-type electrode 400 is disposed on an exposed surface of the n-type semiconductor layer 300.

The substrate 100 may be any material as long as it has a predetermined light transmittance and may facilitate growth of the n-type semiconductor layer 300. For example, when the light emitting structure is formed of a nitride compound semiconductor or an oxide compound semiconductor, and has a hexagonal structure, the substrate 100 also preferably has a hexagonal crystal structure. In addition, the substrate 100 may be provided in a form in which a single crystal thin film is provided thereon in a state in which a crystal structure other than an amorphous phase or a hexagonal system is provided. In addition, the substrate 100 may be provided in the form of a nanostructure formed on any substrate. The nanostructure may have a pattern shape.

For example, the substrate 100 may be a sapphire (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a GaN substrate, a ZnO substrate or a silicon substrate.

The buffer layer 200 may be formed of a nitride film or an oxide film. The buffer layer 200 may minimize the occurrence of crystal defects due to mismatches between lattice constants and thermal expansion coefficients between the substrate 100 and the n-type semiconductor layer 300. It is provided. For example, after forming a low temperature GaN buffer layer on a sapphire substrate, a high quality single crystal GaN nitride semiconductor layer may be grown on the GaN buffer layer.

However, the buffer layer 200 may be omitted according to the embodiment. For example, when an n-GaN semiconductor layer is grown on a GaN substrate, there is no problem of mismatch of lattice constant, and thus, it is sufficient that an additional buffer layer is not interposed between the GaN substrate and the n-GaN semiconductor layer.

An n-type semiconductor layer 300 is formed on the buffer layer 200.

The n-type semiconductor layer 300 may be a nitride semiconductor or an oxide semiconductor.

The nitride semiconductor may be composed of GaN. In this case, a Group 4 element is used as the dopant, and Si is preferably used as the dopant. The oxide semiconductor may be composed of ZnO. In this case, it is preferable that a group 3 element is used as a dopant.

An active layer 500 is formed on the n-type semiconductor layer 300.

The active layer 500 may be formed of a material having a crystal structure that is the same as that of the lower n-type semiconductor layer 300. For example, when the n-type semiconductor layer 300 is GaN-based, the active layer 500 is also preferably formed of GaN-based.

However, according to the exemplary embodiment, the active layer 500 may be formed by heterojunction with the n-type semiconductor layer 300. For example, when the n-type semiconductor layer 300 includes ZnO, the active layer 500 may be formed of a GaN-based film.

In addition, the active layer 500 may have a single quantum well structure or a multi quantum well structure. Multiple quantum well structures are preferred. The multi quantum well structure refers to a structure in which a barrier layer and a quantum well layer are alternately stacked. The barrier layer has a band gap higher than that of the well layer. Through this, the quantum confinement effect in the well layer is effectively expressed. Formation of the well layer or barrier layer is performed by bandgap engineering.

For example, when the GaN-based active layer 500 is to be formed, a material having a lower bandgap than GaN may be introduced to control the bandgap of the well layer. That is, the well layer may be formed of InGaN by introducing In atoms, and the well layer and the barrier layer may be formed by controlling the fraction of In. When the fraction of In is relatively low, it behaves as a barrier layer. When the fraction of In is relatively high, it behaves as a well layer. In addition, the well layer or the barrier layer may be formed in a binary, ternary or quaternary system. For example, a quaternary AlInGaN thin film can be used as the active layer.

In addition, when the active layer 500 is formed of ZnO series, bandgap engineering may be performed by introducing Mg, Cd, or Be, and the like. Of course, the well layer or barrier layer may be formed in a binary, ternary or quaternary system.

However, the band gap of the well layer is required to be lower than the barrier layer, and the band gap of the barrier layer is preferably set lower than that of the p-type semiconductor layer 600.

The p-type semiconductor layer 600 is formed on the active layer 500.

The p-type semiconductor layer 600 is preferably formed of the same base material as the base material forming the n-type semiconductor layer 300 or the active layer 500. For example, when the n-type semiconductor layer 300 or the active layer 500 includes GaN, it is preferable that the p-type semiconductor layer 600 also includes GaN. In addition, when the n-type semiconductor layer 300 or the active layer 500 includes ZnO, it is preferable that the p-type semiconductor layer 600 also includes ZnO.

However, the material of the p-type semiconductor layer 600 is a material having a structure and bandgap that can minimize the absorption of light formed in the active layer 500, and may be used if the material having a predetermined light transmittance. .

Various types of dopants may be introduced to form the p-type semiconductor layer 600. For example, when the p-type semiconductor layer 600 includes GaN, a Group 2 element may be used as the dopant, and Mg is preferably used. In addition, when the n-type semiconductor layer 300 includes ZnO, a group 1 element or a group 5 element may be used as the dopant.

The current diffusion layer 700 is formed on the p-type semiconductor layer 600.

The current spreading layer 700 improves ohmic junction characteristics between the p-type semiconductor layer 600 and the p-type electrode 900 and serves to spread current. A conductive oxide such as ITO may be used as the current spreading layer 700. However, the current spreading layer 700 may be omitted according to the embodiment.

The p-type electrode 900 is formed on the current spreading layer 700.

The p-type electrode 900 may be any material that can form an ohmic junction with the p-type semiconductor layer 600. For example, the p-type electrode 900 may be formed of Cr / Au.

In addition, a p-type pad (not shown) may be connected to the p-type electrode 900.

The n-type electrode 400 is formed in the n-type semiconductor layer 300. Therefore, by forming the n-type electrode 400 inside the n-type semiconductor layer 300, it is possible to increase the electrode contact area to improve the current diffusion effect. In addition, since only the area for forming the n-type pad 800 is to be etched, the area of the active layer 500 is minimized compared to the conventional horizontal light emitting device, and the surface area emitted to the outside increases the light extraction efficiency of the light emitting device. Can be improved.

The width of the n-type electrode 400 may be 3㎛ to 10㎛. The width of the n-type electrode 400 may be thinly formed to have a thickness of about 3 μm to 10 μm to reduce defects or voids that may occur in the regrowth process of the n-type semiconductor layer 300. .

If the width of the n-type electrode 400 is less than 3 μm, the area where the n-type electrode 400 and the n-type semiconductor layer 300 meet is small and current injection efficiency may be reduced. In addition, when the width of the n-type electrode 400 is greater than 10㎛, the area blocking the path from which the light generated in the active layer 500 is emitted to the outside can be increased to reduce the light extraction efficiency.

The n-type electrode 400 may have a thickness of 0.5 μm to 5 μm. Therefore, when the n-type electrode 400 is formed on the surface of the n-type semiconductor layer 300, only the lower area of the n-type electrode 400 contacts the n-type semiconductor layer 300, the present invention is the n-type Since the lower and side portions of the electrode 400 meet the n-type semiconductor layer 300, the current injection area can be increased to improve the current injection effect.

If the thickness of the n-type electrode 400 is less than 0.5 μm, the current injection area may be small and thus the current injection may not be sufficient. In addition, if the thickness of the n-type electrode 400 is greater than 5㎛, the n-type electrode is positioned to the middle height inside the n-type semiconductor layer may reduce the current injection efficiency.

The n-type semiconductor layer 300 below the n-type electrode 400 may have a thickness of 1 μm to 5 μm. If the thickness of the n-type semiconductor layer 300 under the n-type electrode 400 is less than 1 μm, the thickness of the n-type semiconductor layer 300 under the n-type electrode 400 is too thin and current spreading may occur. The path that occurs can be small. In addition, if the thickness of the n-type semiconductor layer 300 below the n-type electrode 400 is greater than 5 μm, an area where current does not pass in the n-type semiconductor layer 300 below the n-type electrode 400. This may increase.

When the n-type semiconductor layer 300 includes GaN, the n-type electrode 400 is composed of Ni, Cr, W, Rh, In, Au, Sn, Zr, Ta, Al, Ti, and compounds thereof It may include any one selected from the group. In addition, the n-type electrode 400 may be formed of Ti / Au.

In addition, when the n-type semiconductor layer 300 includes ZnO, the n-type electrode 400 is Ni, Cr, W, Rh, In, Au, Sn, Zr, Ta, Al, Ti and compounds thereof It may include any one selected from the group consisting of. In addition, the n-type electrode 400 may be formed of Pt / Au.

Meanwhile, an insulating layer (not shown) may be further formed on the n-type electrode 400.

The insulating layer allows the current of the n-type electrode 400 to spread to the lower side and the side of the n-type electrode 400 without spreading over the n-type electrode 400. Therefore, the current spreading effect can be improved to increase the light extraction efficiency of the light emitting device.

The insulating layer may include any one selected from the group consisting of SiO ₂ , silicon nitride, silicide, gallium nitride, and a rare earth material.

The n-type pad 800 is disposed on an exposed surface of the n-type semiconductor layer 300 to contact the n-type electrode 400.

Current may be injected into the n-type electrode 400 inside the n-type semiconductor layer 300 through the n-type pad 800.

If there are a plurality of n-type electrodes 400, it is preferable to form n-type pads so as to contact the plurality of n-type electrodes 400.

The n-type pad 800 may include any one selected from the group consisting of Ni, Cr, W, Rh, In, Au, Sn, Zr, Ta, Al, Ti, and compounds thereof. The material of the n-type pad 800 may be the same as or different from the material of the n-type electrode 400.

FIG. 2 is a cross-sectional view of the light emitting device of FIG. 1 taken along the line II ′. FIG.

2, it can be seen that a plurality of n-type electrodes 400 are in contact with one n-type pad 800. Accordingly, current may be injected to the plurality of n-type electrodes 400 at the same time through the n-type pad 800.

Example  2

3 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting device according to an embodiment of the present invention according to a process step.

3 to 6, the n-type semiconductor layer 300 having the n-type electrode 400 embedded therein is formed on the buffer layer 200 formed on the substrate 100.

Referring to FIG. 3, first, a substrate 100 is prepared. The substrate 100 may be a sapphire (Al ₂ O ₃ ) substrate, a silicon carbide (SiC) substrate, a GaN substrate, a ZnO substrate, or a silicon substrate.

A buffer layer 200 is formed on the substrate 100. The buffer layer 200 may be appropriately selected according to the material of the substrate and the n-type semiconductor layer. The buffer layer 200 is formed using metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) or molecular beam growth (MBE). can do.

An n-type semiconductor layer 300 is formed on the buffer layer 200. The n-type semiconductor layer 300 may be formed using MOCVD, HVPE or MBE.

Referring to FIG. 4, a recess 310 is formed on a surface of the n-type semiconductor layer 300. The recess 310 may be single or plural. The concave portion 310 may have various shapes such as a cylindrical shape, a conical shape, a pyramid shape, a polygonal column shape, or a bar shape. In addition, the recess 310 may have a zigzag shape.

The recess 310 may be formed such that the thickness of the n-type semiconductor layer 300 under the recess 310 is 1 μm to 5 μm. If the thickness of the n-type semiconductor layer 300 below the recess 310 is less than 1 μm, the n-type semiconductor layer 300 below the n-type electrode 400 embedded in the recess 310 may be formed. The thickness can be so thin that the path through which current spreading occurs can be small. In addition, if the thickness of the n-type semiconductor layer 300 below the recess 310 is greater than 5 μm, the n-type semiconductor layer (under the n-type electrode 400 buried in the recess 310) There is a fear that the area where the current does not pass in 300 increases.

The recess 310 may be formed using a lithography process and an etching process. For example, the forming of the recess 310 on the n-type semiconductor layer 300 may include forming a resist pattern on the n-type semiconductor layer 300 and an n-type semiconductor layer exposed by the resist pattern ( And etching the 300 to form the recess 310 and removing the resist pattern.

The resist pattern may be formed using a lithography method, and specifically, may be performed using a nanoimprint lithography method, a laser interference lithography method, an electron beam lithography method, an ultraviolet lithography method, a holographic lithography method, or an immersion lithography method.

The etching process may include dry etching or wet etching. Preferably, the process may be performed using an inductively coupled plasma (ICP) process.

The resist pattern may be removed using a resist removal gas or a removal solution. The resist removal gas may be Ar / O ₂ or He / O ₂ , and the resist removal solution may be acetone.

Referring to FIG. 5, an n-type electrode 400 filling at least a portion of the recess 310 is formed. The n-type electrode 400 may fill some or all of the recess 310 of the recess 310.

The n-type electrode 400 may have a thickness of 0.5 μm to 5 μm.

Depending on the thickness of the n-type electrode 400 to be formed, the n-type electrode 400 may be embedded in a portion of the concave portion 310 or may be embedded in the whole. In addition, the n-type electrode 400 may be embedded in the recess 310 and further grown thereon. However, when the n-type electrode 400 is buried in the recess 310 and further grown, there is a fear that a flow of the n-type electrode may occur when the n-type semiconductor layer is subsequently grown again. Therefore, it is preferable to embed the n-type electrode 400 in the recess 310.

The n-type electrode 400 may be formed using a conventional deposition method such as metal deposition, sputtering, or sol-gel, or using a solution based method.

Meanwhile, after the forming of the n-type electrode 400, a step of forming an insulating layer (not shown) on the n-type electrode 400 may be added.

After forming the n-type electrode 400, the insulating layer may be formed on the n-type electrode 400 using a lithography process and a conventional deposition process.

Referring to FIG. 6, the n-type semiconductor layer 300 is regrown to cover the n-type electrode 400. The n-type electrode 400 may be covered with the n-type semiconductor layer 300 by using a regrowth method using MOCVD.

If an insulating layer is formed on the n-type electrode 400, the n-type semiconductor layer 300 may be regrown to cover the n-type electrode 400 and the insulating layer.

Referring to FIG. 7, an active layer 500, a p-type semiconductor layer 600, and a current diffusion layer 700 are sequentially formed on the regrown n-type semiconductor layer 300. The current spreading layer 700 may be omitted according to the embodiment.

The active layer 500, the p-type semiconductor layer 600, and the current spreading layer 700 may be formed using MOCVD, HVPE, MBE, E-beam or sputter regardless of each other.

8 is a cross-sectional view of the light emitting device of FIG. 7 taken along the cutting line II-II '.

Referring to FIG. 8, the n-type electrode 400 is positioned inside the n-type semiconductor layer 300. On the other hand, although the n-type electrode 400 appears to separate the n-type semiconductor layer 300 from the drawing, in practice, the n-type electrode 400 does not separate the n-type semiconductor layer 300.

9 and 10, a portion of the n-type semiconductor layer 300 is exposed to form an n-type pad 800 in contact with the n-type electrode 400. In addition, a p-type electrode 900 is formed on the current spreading layer 700.

9, a portion of the current diffusion layer 700, the p-type semiconductor layer 600, the active layer 500, and the n-type semiconductor layer 300 are etched to expose a portion of the n-type electrode 400. .

The etching process may be mesa etching using ICP.

Referring to FIG. 10, an n-type pad 800 is formed on the surface of the n-type semiconductor layer 300 exposed by the etching to contact the n-type electrode 400. The n-type pad 800 may be formed using a conventional deposition method such as metal deposition, sputtering, or sol-gel, or using a solution based method.

In addition, a p-type electrode 900 is formed on the current spreading layer 700. If the current diffusion layer 700 is omitted, the p-type electrode 900 will be formed on the p-type semiconductor layer 600.

The p-type electrode 900 may be formed using a conventional deposition method such as metal deposition, sputtering, or sol-gel, or using a solution based method.

Meanwhile, the p-type electrode 900 may be formed before the forming of the n-type pad.

In addition, a p-type pad (not shown) connected to the p-type electrode may be formed.

In the light emitting device according to the present invention, by forming an n-type electrode inside the n-type semiconductor layer, it is possible to minimize the reduced area of the active layer and increase the surface area emitted, thereby improving the light extraction efficiency of the light emitting device.

In addition, by reducing the width of the n-type electrode to reduce the area blocking the path of the emitted light to the outside can be reduced the amount of light is absorbed into the interior.

In addition, the position of the n-type electrode can be positioned closer to the lower portion inside the n-type semiconductor layer to improve the current injection effect.

In addition, by forming an insulating layer on the n-type electrode to design the current spreading to the lower and side portions of the n-type electrode can improve the current spreading effect.

In addition, the width of the n-type electrode is designed to be thin and embedded in the concave portion of the n-type semiconductor layer, thereby reducing defects or voids that may occur in the regrowth process of the n-type semiconductor layer. have.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the present invention is not limited to the disclosed exemplary embodiments, and various changes and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention. Change is possible.

100: substrate 200: buffer layer
300: n-type semiconductor layer 310: recessed portion
400: n-type electrode 500: active layer
600: p-type semiconductor layer 700: current diffusion layer
800: n-type pad 900: p-type electrode

Claims (14)

Board;
An n-type semiconductor layer formed on the substrate;
An active layer formed on the n-type semiconductor layer;
A p-type semiconductor layer formed on the active layer;
A p-type electrode formed on the p-type semiconductor layer;
An n-type electrode formed inside the n-type semiconductor layer;
An n-type pad in contact with the n-type electrode and disposed on an exposed surface of the n-type semiconductor layer; And
And an insulating layer formed in the n-type semiconductor layer and formed on the n-type electrode.
Light emitting element. The method of claim 1,
The thickness of the n-type semiconductor layer below the n-type electrode is 1㎛ to 5㎛,
Light emitting element The method of claim 1,
The light emitting device, characterized in that the current spreads to the lower side and the side of the n-type electrode by the insulating layer. The method of claim 1,
The width of the n-type electrode is a light emitting device of 3㎛ 10㎛. The method of claim 1,
The n-type electrode has a thickness of 0.5㎛ 5㎛ light emitting device. The method of claim 1,
The light emitting device further comprises a buffer layer between the substrate and the n-type semiconductor layer. The method of claim 1,
And a current spreading layer between the p-type semiconductor layer and the p-type electrode. The method of claim 1,
The n-type electrode includes any one selected from the group consisting of Ni, Cr, W, Rh, In, Au, Sn, Zr, Ta, Al, Ti, and compounds thereof. The method of claim 2,
The insulating layer includes any one selected from the group consisting of SiO ₂ , silicon nitride, silicide, gallium nitride and rare earth materials. Preparing a substrate;
Forming an n-type semiconductor layer in which an n-type electrode is embedded on the substrate;
Forming an active layer on the n-type semiconductor layer;
Forming a p-type semiconductor layer on the active layer;
Exposing a portion of the n-type semiconductor layer to form an n-type pad in contact with the n-type electrode; And
Forming a p-type electrode on the p-type semiconductor layer,
The forming of the n-type semiconductor layer in which the n-type electrode is embedded includes: forming an n-type semiconductor layer on the substrate; Forming a recess on a surface of the n-type semiconductor layer; Forming an n-type electrode filling at least a portion of the recess; And re-growing the n-type semiconductor layer to cover the n-type electrode.
The thickness of the n-type semiconductor layer below the n-type electrode is 1㎛ to 5㎛,
Light emitting device manufacturing method. delete The method of claim 10, wherein forming the n-type pad,
Etching a portion of the p-type semiconductor layer, the active layer, and the n-type semiconductor layer so that a portion of the n-type electrode is exposed to the outside; And
And forming an n-type pad on the exposed surface of the n-type semiconductor layer to be in contact with the n-type electrode. The method of claim 10, before the forming of the n-type semiconductor layer,
Forming a buffer layer on the substrate further comprising a light emitting device manufacturing method. The method of claim 10,
Between forming the p-type semiconductor layer and forming the n-type pad,
And forming a current spreading layer on the p-type semiconductor layer.

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