KR101288840B1 - Liquid crystal display device - Google Patents

Abstract

According to the present invention, a digital-to-analog converter is formed between a timing controller and a data drive integrated circuit, not inside the data drive integrated circuit, so that the latch part of the data drive integrated circuit is configured as a simple circuit, thereby excluding the digital-analog converter. To a liquid crystal display device mounted directly on a liquid crystal panel. The present invention includes a liquid crystal panel in which a plurality of pixels in which data lines and gate lines intersect are formed, and displays an image; A timing controller for generating a control signal for driving the liquid crystal panel using signals input from the outside and rearranging and outputting pixel data from the outside; A digital-analog converter converting the digital pixel data supplied from the timing controller into an analog pixel signal and outputting the analog pixel signal; A gate drive integrated circuit sequentially applying scan signals to gate lines according to the control signal; And an analog pixel signal applied to the data lines according to the control signal, and is achieved by a data drive integrated circuit mounted directly on the liquid crystal panel except for the digital-analog converter.

Description

[0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

1 is a plan view schematically showing a general liquid crystal display device.

2 is a plan view schematically showing a liquid crystal display according to a preferred embodiment of the present invention.

3 is a block diagram illustrating a data drive integrated circuit and peripheral components in accordance with a preferred embodiment of the present invention.

4 is a circuit diagram showing a circuit configuration inside the latch portion of FIG.

FIG. 5 is an enlarged circuit diagram of region A of FIG. 4. FIG.

DESCRIPTION OF THE REFERENCE SYMBOLS

102: timing controller

104: digital / analog converter

108: data driver

118: data drive integrated circuit

118a: shift register section

118b: Latch

118c: buffer section

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving unit of a liquid crystal display device. In particular, a digital-to-analog converter for converting digital pixel data into an analog pixel signal is formed between a timing controller and a data drive integrated circuit instead of a data drive integrated circuit. The present invention relates to a liquid crystal display device in which a data drive integrated circuit excluding a digital-to-analog converter is mounted directly on a liquid crystal panel by configuring the latch portion of the circuit in a simple circuit.

In general, a liquid crystal display device includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled therebetween; It is configured to include a driver for performing the operation of the panel.

Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

In the liquid crystal panel, pixels are formed in regions where the gate lines that are regularly spaced apart from each other and the data lines that are vertically spaced apart from each other intersect with each other, and the gate lines and the data lines cross each other.

The driving circuit includes a gate driver for driving gate lines and a data driver for driving data lines.

The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line.

The gate driver includes a plurality of gate drive integrated circuits to drive the gate lines by dividing the gate lines.

The data driver supplies a pixel signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines.

Such a data driver includes a plurality of data drive integrated circuits to divide and drive data lines.

Hereinafter, a general liquid crystal display according to the related art will be described with reference to the drawings.

FIG. 1 is a plan view schematically illustrating a general liquid crystal display, and illustrates a liquid crystal panel 1, a gate driver 6, a data driver 8, and a timing controller 4 for driving the liquid crystal panel 1.

Here, the gate driver 8 includes a plurality of gate drive integrated circuits, and the data driver 6 includes a plurality of data driver integrated circuits.

Conventional data drive integrated circuits include a shift register for outputting a sequential sampling signal although not shown in the drawings, a latch portion for sequentially latching and simultaneously outputting pixel data in response to the sampling signal, and a digital output from the latch portion. And a digital-to-analog converter for converting pixel data into an analog pixel signal, and a buffer unit for buffering and outputting pixel signals from the digital-analog converter.

In addition, the data drive integrated circuit may include various control signals supplied from the timing controller and a signal controller for relaying pixel data, and a gamma voltage unit for supplying the positive and negative gamma voltages required by the digital-analog converter. It is provided with.

Such data drive integrated circuits are typically mounted on a tape carrier package and connected to the liquid crystal panel in a tabbed manner.

However, recently, a technology for implementing a thinning of a liquid crystal display device by applying a chip on glass (COG) method in which the data drive integrated circuit and the gate drive integrated circuit are directly mounted on a glass substrate of a liquid crystal panel has been developed. There is a growing trend to apply the COG method in the actual manufacturing of liquid crystal display devices.

In the liquid crystal display device using the COG method, it is the biggest problem to minimize the size of the gate drive integrated circuit or the data drive integrated circuit mounted directly on the glass substrate of the liquid crystal panel in order to reduce the thickness of the liquid crystal display device.

However, data drive integrated circuits are not easy to reduce their size due to their complex configuration. In particular, data-drive integrated circuits minimize the size of data drive integrated circuits due to the large volume of digital-to-analog converters. There has been a limit.

Therefore, the present invention is designed to solve the above problems, and a digital-to-analog converter for converting digital pixel data into an analog pixel signal is formed between the timing controller and the data drive integrated circuit instead of inside the data drive integrated circuit. The present invention provides a liquid crystal display device in which a latch unit inside an integrated circuit is configured as a simple circuit and directly mounts a data drive integrated circuit to a liquid crystal panel except for a digital-analog converter.

According to an aspect of the present invention, there is provided a liquid crystal display including: a liquid crystal panel in which a plurality of pixels in which data lines and gate lines intersect are formed, and displays an image; A timing controller for generating a control signal for driving the liquid crystal panel using signals input from the outside and rearranging and outputting pixel data from the outside; A digital-analog converter converting the digital pixel data supplied from the timing controller into an analog pixel signal and outputting the analog pixel signal; A gate drive integrated circuit sequentially applying scanning signals to gate lines according to the control signal; And a data drive integrated circuit configured to apply an analog pixel signal to data lines according to the control signal, and to be mounted directly on the liquid crystal panel except for the digital-to-analog converter.

The data drive integrated circuit may further include a shift register unit configured to sequentially output a sampling signal in response to a control signal from the timing controller; An analog latch unit for sequentially latching and simultaneously outputting an analog pixel signal from the digital-analog converter in response to a control signal from the timing controller and the sampling signal; And a buffer unit for buffering the analog pixel signal from the analog latch unit and supplying the analog pixel signal to the data line.

The analog latch unit may include: a first switching device configured to control conduction of the analog pixel signal in response to the sampling signal; A capacitor for temporarily storing the analog pixel signal output from the first switching element; A plurality of latches having a second switching device for outputting a voltage stored in the capacitor in response to a control signal from the timing control unit is characterized in that an array.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view briefly illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a data drive integrated circuit and peripheral components in accordance with a preferred embodiment of the present invention, wherein the data driver integrated circuit 118 of FIG. 3 includes a plurality of data drive integrated devices constituting the data driver of FIG. One of the circuits is shown.

As shown in FIG. 3, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of pixels in which data lines DL1 to DLn and gate lines GL1 to GLn intersect are formed to display an image. A liquid crystal panel (100 in FIG. 2); A timing controller 102 generating a control signal for driving the liquid crystal panel 100 using signals input from the outside and rearranging and outputting pixel data from the outside; A digital-analog converter 104 converting the digital pixel data supplied from the timing controller 102 into an analog pixel signal and outputting the analog pixel signal; A gate drive integrated circuit (not shown) sequentially applying a scanning signal to gate lines GL1 to GLn according to the control signal; And a data drive integrated circuit 118 applying an analog pixel signal to the data lines DL1 to DLn according to the control signal and mounted directly on the liquid crystal panel 100 except for the digital-to-analog converter 104. It is configured to include.

2 and 3, each component of a liquid crystal display driver driving unit according to an exemplary embodiment of the present invention will be described with reference to the flow of pixel data.

The timing controller 102 generates a control signal for driving the liquid crystal panel using signals input from the outside, and rearranges and outputs the pixel data input from the outside. To this end, the timing controller 102 includes a control signal generator (not shown) and a pixel data reordering unit (not shown).

The control signal generator may include a gate start pulse (GSP) and a gate shift clock (GSC) to control the gate drive integrated circuit using a main clock signal input from an external source and horizontal and vertical synchronization signals. Generating a gate control signal such as a gate output signal (GOE), a source start pulse (SSP), a source shift clock (Sourse Shift Clock) to control the data drive integrated circuit 118; SSC), a source output enable signal (Sourse Output Enable (SOE)), a data polarity selection (Data Reverse; REV), and a polarity control signal (Polarity; POL).

The data rearranging unit rearranges and outputs the red (R), green (G), and blue (B) pixel data supplied from the outside so as to be supplied to the data drive integrated circuit 118, and to reduce the transmission frequency. The data is divided into even data and odd data and simultaneously output through each transmission line.

Here, each of the even data and the odd data includes pixel data of red (R), green (G), and blue (B).

The digital-to-analog converter 104 is located outside the data drive integrated circuit 118 as shown in FIG. 3, and more specifically, is formed between the timing controller 102 and the data drive integrated circuit 118. do.

The digital-analog converter 104 converts the digital pixel data output from the timing controller 102 into an analog pixel signal using a gamma reference voltage, and then the data drive integrated circuit 118, that is, the data drive integrated circuit 118. ) To the internal latch portion 118a.

The gamma reference voltage is a signal supplied from the gamma voltage generator 110 of FIG. 3.

Although not shown in the figure, the digital-to-analog converter 104 includes a positive (P) decoding unit, a negative (N) decoding unit, and a multiplexer (MUX) unit.

The n P decoders included in the P decoding unit convert the data input from the timing controller 102 into the positive analog pixel signal using the positive gamma reference voltages.

The n N decoders included in the N decoding unit convert the data input from the timing controller 102 into the negative analog pixel signal using the negative gamma reference voltages.

The n multiplexers included in the multiplexer unit select and output a positive analog pixel signal from the P decoder or a negative analog pixel signal from the N decoder in response to the polarity control signal POL from the timing controller 102. The positive analog pixel signal and the negative analog pixel signal are supplied to the latch unit 118a in the data driver integrated circuit 118.

As shown in FIG. 3, the data drive integrated circuit 118 includes: a shift register unit 118a for sequentially outputting sampling signals in response to a control signal from the timing controller 102; An analog latch unit 118b for sequentially latching and simultaneously outputting an analog pixel signal from the digital-to-analog converter 104 in response to a control signal from the timing controller 102 and the sampling signal; And a buffer unit 118c for buffering the analog pixel signal from the analog latch unit 118b and supplying the analog pixel signal to the data lines DL1 to DLn.

In addition, a signal controller 118d for outputting various control signals and the analog pixel signal from the timing controller 102 to the corresponding components is further provided.

The shift register unit 118a sequentially shifts the source start pulse SSP from the timing controller 102 in accordance with the source sampling clock signal SSC to supply the latch unit 118b, which is a sampling signal. to be.

The source start pulse SSP and the source sampling clock signal SSC are output from the timing controller 102 and input to the shift register unit 118a through the signal controller 118d.

 As illustrated in FIG. 3, the latch unit 118b sequentially samples and latches analog pixel signals from the timing control unit 102 in predetermined units in response to a sampling signal from the shift register unit 118a. To this end, the latch unit 118b is composed of an array of n latches. Details of the internal circuits of the latch unit 118b will be described later with reference to FIGS. 4 and 5.

The latch unit 118b latches the even pixel signal and the odd pixel signal whenever the sampling signal is supplied from the shift register unit 118a. Here, each of the even pixel signal and the odd pixel signal includes red (R), green (G), and blue (B) pixel signals, as mentioned in the description of the timing controller 102. Accordingly, the latch unit 118b simultaneously latches the even pixel signal and the odd pixel signal, that is, six pixel signals supplied from the timing controller 102 and supplied through the digital-analog converter 104.

Subsequently, the latch unit 118b simultaneously outputs the n pixel data output from the timing controller 102 and latched in response to the source output enable signal SOE input through the signal controller 118d. It supplies to the part 118c.

As shown in FIG. 3, the buffer unit 118c buffers and amplifies analog pixel signals output from the latch unit 118b and supplies them to the data lines DL1 to DLn of the liquid crystal panel 100. 118c consists of n buffer arrays.

As described above, the structure of the liquid crystal display device according to the present invention, in which the digital-to-analog converter 104 is not formed inside the data drive integrated circuit 118 and is formed outside the data drive integrated circuit 118, has been previously known. Advantage of minimizing the size of the data drive integrated circuit 118 by removing the digital-analog converter 104, which occupies the largest volume in the drive integrated circuit, from the data drive integrated circuit and forming it outside the data drive integrated circuit 118. There is this.

The micro data drive integrated circuit 118 has an advantage of manufacturing a thinner liquid crystal display device by directly mounting the data drive integrated circuit 118 to the liquid crystal panel 100 by applying a COG method.

3 to 5, the detailed configuration of the latch unit according to the preferred embodiment of the present invention will be described.

FIG. 4 is a circuit diagram showing a circuit configuration inside the latch portion of FIG. 3, which shows an embodiment of the present invention for an analog latch portion composed of a simple circuit by removing the digital-analog converter from the data drive integrated circuit.

FIG. 5 is an enlarged circuit diagram of A of FIG. 4, and is an enlarged circuit diagram of one latch constituting the latch unit.

The latch unit 118b is an analog latch unit, and as shown in FIG. 4, a first NMOS transistor T11 for controlling conduction of the analog pixel signal in response to the sampling signal; A capacitor C1 for temporarily storing the analog pixel signal output from the first NMOS transistor T11; A plurality of starting from the first latch (region A in FIG. 4) having a second NMOS transistor T12 for outputting a voltage stored in the capacitor C1 in response to a control signal from the timing controller 102. The latch is configured as an array.

In addition, the latch unit 118b is provided with output resistors R1 to Rn connected in parallel to the output terminals of each latch, which adjusts the output impedance of each latch.

Referring to FIG. 5, the operation of one latch configured in the analog latch unit will be described below.

First, when the sampling signal of “HIGH” is input to the first NMOS transistor T11, the first NMOS transistor T11 is turned on.

Accordingly, the analog pixel signal is charged in the first capacitor C1.

Thereafter, when the source output enable signal SOE of "HIGH" is input to the second NMOS transistor T12, the second NMOS transistor T12 is turned on.

Accordingly, the analog pixel signal charged in the first capacitor C1 is output and supplied to the buffer unit 118C.

Referring to FIG. 4, the operation of the entire analog latch unit 118b will be described with reference to surrounding components connected to the analog latch unit 118b.

Here, for convenience of description, the data driver 108 will be described under the assumption that the data driver integrated circuit 118 is configured.

Each NMOS transistor is provided in each latch of the analog latch unit 118b, and the names of each NMOS transistor include a first NMOS transistor T11 and a first transistor provided in the first latch. Starting from the second NMOS transistor T12, the second nMOS transistor Tn1 and the second nMOS transistor Tn2 included in the nth latch are determined.

First, when the sampling signal of "HIGH" from the shift register 118a is input to the first, third, five, seven, nine, and eleven transistors T11, T21, T31, T41, T51, and T61, The first, third, five, seven, nine, and eleven transistors T11, T21, T31, T41, T51, and T61 are turned on.

Accordingly, the analog pixel signal is charged in the first to sixth capacitors C1 to C6 of the first to sixth latches.

Next, the "HIGH" sampling signal is input from the shift register section 118a to the thirteenth, fifteenth, seventeenth, nineteenth, twenty-first, and thirteenth NMOS transistors, and the thirteenth, fifteenth, seventeenth, nineteenth, thirteenth, and thirteenth signals. The NMOS transistor is turned on. Accordingly, the analog pixel signal is stored in the seventh to twelfth capacitors C7 to C12.

The above process is repeated until the analog pixel signal is stored in the n th capacitor Cn of the n th latch.

After that, the timing controller 102 outputs the source output enable signal SOE of “HIGH” through the signal controller 118d to the first to second n-MOS transistors T11 to Tn2 simultaneously. In this case, the first to second n-MOS transistors are simultaneously turned on.

Accordingly, the analog pixel signals charged in the first to nth capacitors C1 to Cn are supplied to the buffer unit 118c connected to the output terminals of the first to nth latches.

Since the analog latch 118b circuit configured as described above is configured based on two switching elements, its structure is simple.

Therefore, there is an effect of minimizing the size of the data drive integrated circuit 118, there is an easy advantage in mounting the data drive integrated circuit 118 directly to the liquid crystal panel 100 in the COG method.

As described in detail above, the present invention has the following advantages.

The present invention has the effect of minimizing the size of the data drive integrated circuit by forming the digital-to-analog converter between the timing controller and the data drive integrated circuit rather than inside the data drive integrated circuit.

In addition, in the structure in which the digital-to-analog converter is not formed inside the data drive integrated circuit as described above, by applying an analog latch having a simple structure in which a plurality of latches composed of two switching elements and one capacitor are formed as an array. As a result, the size of the data drive integrated circuit is further minimized.

Accordingly, the liquid crystal display device to which the present invention is applied is extremely thin in size, so that the data drive integrated circuit can be directly mounted on the liquid crystal panel by applying the COG method, thereby making it possible to realize a thinner liquid crystal display device. There is an advantage.

Claims (7)

A liquid crystal panel in which a plurality of pixels in which data lines intersect gate lines are formed, and displays an image; A timing controller for generating a control signal for driving the liquid crystal panel using signals input from the outside and rearranging and outputting pixel data from the outside; A digital-to-analog converter including a P decoder, an N decoder, and a multiplexer to convert digital pixel data supplied from the timing controller into an analog pixel signal and output the analog pixel signal; A gate drive integrated circuit sequentially applying scanning signals to gate lines according to the control signal; And A signal control unit for receiving the control signal and the analog pixel signal, and an analog latch unit for sequentially storing and outputting the analog pixel signal applied from the signal control unit through a sampling signal according to the control signal, the analog pixel signal A data drive integrated circuit for supplying the data lines to the data lines; The analog latch unit comprises a plurality of latches in an array, The latch is, A first NMOS transistor connected to the signal controller and outputting the analog pixel signal in response to the sampling signal; A capacitor connected to the first NMOS transistor and temporarily storing the output analog pixel signal; A second NMOS transistor connected to the signal controller and configured to output a voltage stored in the capacitor in response to a source enable signal among the control signals; And An output resistor connected in parallel with the second NMOS transistor to adjust an output impedance And the liquid crystal display device. The integrated circuit of claim 1, wherein the data drive integrated circuit comprises: A shift register section for sequentially outputting a sampling signal in response to a control signal from the timing controller; And And a buffer unit for buffering the analog pixel signal from the analog latch unit and supplying the analog pixel signal to the data line. delete delete The liquid crystal display of claim 1, wherein a control signal input from the timing controller to the second NMOS transistor is commonly input to the plurality of latches. delete delete

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