KR101277298B1 - Apparatus for cross correlation - Google Patents

Abstract

The cross-correlation apparatus includes an input signal processor that outputs N sample signals sampled from the input signal, and a sample that receives N sample signals and outputs a plurality of sample signal sequences each including M sample signals among the N sample signals. A signal processor, a reference signal processor for outputting a reference signal sequence including the number of reference signals corresponding to the sample signal sequence, and an N-sample signal input to add and process an addition for each sample signal group including two or more sample signals. A shared addition processing unit for generating a value and outputting a plurality of addition result values, and receiving a sample signal sequence, a reference signal sequence, and an addition result value, and performing cross-correlation processing with the reference signal sequence in parallel for each of the plurality of sample signal sequences. It includes a cross correlation processing unit for calculating a correlation value.

Description

Cross Correlation Device {APPARATUS FOR CROSS CORRELATION}

The present invention relates to a cross correlation device.

The signal correlator is used to measure the similarity between a reference signal and an input signal, and is used as a key element in a communication device such as a signal pattern and a synchronization detection device.

A conventional cross correlator measures the similarity through a multiplication operation between an input signal and a reference signal sequentially input according to time t as shown in Equation 1 below.

&Quot; (1) "

 In this case, the cross correlator requires N multipliers when implemented as a circuit operating at the same frequency as the sampling frequency of the input signal.

As such, when multiplying the entire operation in multi-correlation with respect to the input signal samples, power consumption by the multiplier is high, which may cause system overload.

In order to solve such a problem, Korean Patent No. 0667552 discloses a matched filter including a parallel cross correlator and a cross correlation method thereof. Specifically, a matching filter and a cross-correlation method for driving a plurality of cross-correlators in parallel to increase the system efficiency by reducing the number of multipliers are disclosed.

As such, by performing parallel correlation on input sample signals and performing cross correlation in parallel, cross correlation with sample signals input at large bandwidths can be performed at high speed even with a low speed multiplier.

However, in order to actually perform the operation of one multiplier, it is necessary to combine the operations of a plurality of adders, and thus, a simpler cross-correlation circuit is required to efficiently reduce the power consumption of the circuit. In addition, the conventional cross-correlation method has a disadvantage in that a cross correlation process fixed to a specific reference sequence waveform must be performed.

The present invention is to solve the above-mentioned problems of the prior art, to provide a cross-correlation device that can increase the power efficiency and circuit configuration efficiency.

According to an aspect of the present invention, there is provided a cross-correlation device for performing a cross-correlation process between an input signal and a reference signal, including: an input signal processor configured to output N samples of sampled samples of the input signal; A sample signal processor configured to receive the N sample signals and output a plurality of sample signal sequences each including M sample signals among the N sample signals; A reference signal processor configured to output a reference signal sequence including the reference signals corresponding to the sample signal sequence; A shared addition processor configured to receive the N sample signals and perform an addition process for each sample signal group including two or more sample signals to generate an addition result value, and output a plurality of the addition result values; And a cross-correlation processor that receives the sample signal sequence, the reference signal sequence, and the addition result value, and performs cross-correlation processing with the reference signal sequence in parallel for each of the plurality of sample signal sequences to calculate a cross correlation value.

According to any one of the problem solving means of the present invention described above, by driving a cross-correlator composed of a plurality of adders and multiplexers in parallel, it is possible to increase the power efficiency in the cross-correlation processing between the input signal and the reference signal and to quickly cross-correlate There is an effect.

According to one of the problem solving means of the present invention, a plurality of cross correlators share and use the result values calculated through a plurality of adders in the cross-correlation process so that the cross-correlation can be processed with only a minimal adder. The efficiency is increased.

In addition, according to any one of the problem solving means of the present invention, by using the reference signal as the drive control signal of the multiplexer included in each cross-correlator, it is possible to calculate the cross-correlation value according to various types of reference signals in parallel Can be.

1 is a block diagram showing the structure of a cross correlation device according to an embodiment of the present invention.
2 is a diagram illustrating a shared addition processor and a cross correlation processor according to an embodiment of the present invention.
3 is a detailed view of a cross correlation processing unit according to an embodiment of the present invention.
4 is a detailed view of a cross correlator according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when an element is referred to as "comprising ", it means that it can include other elements as well, without departing from the other elements unless specifically stated otherwise.

1 is a block diagram showing the structure of a cross correlation device according to an embodiment of the present invention.

2 is a diagram illustrating a shared addition processor and a cross correlation processor according to an embodiment of the present invention.

First, as shown in FIG. 1, the cross-correlation apparatus 100 according to an embodiment of the present invention includes an input signal processor 110, a sample signal processor 120, a shared addition processor 130, and a cross correlation processor ( 140, and a reference signal processor 150.

The input signal processor 110 receives a sample signal obtained by sampling a continuous input signal, and outputs the input signal by a predetermined number (hereinafter, referred to as 'first'). For reference, the input signal processor 110 may receive an input signal and sample the process by extracting a sample signal by itself.

In this case, the input signal processor 110 outputs a plurality of sample signals to the sample signal processor 120, but outputs a first sample signal per clock according to a preset frequency.

The sample signal processor 120 continuously receives the first sample signal, and includes a shared sample signal sequence consisting of the first sample signal input for each clock and a predetermined number smaller than the first number (hereinafter, A separate sample signal sequence consisting of two sample signals is output through a plurality of different paths, respectively.

In detail, the sample signal processor 120 outputs one shared sample signal sequence per clock to the shared addition processor 130, and outputs a plurality of individual sample signal sequences per clock to the cross correlation processor 140.

In this case, the sample signal processing unit 120 is composed of a second sample signal of the first sample signal included in the shared sample signal sequence, and outputs a plurality of individual sample signal sequences, each of which is a different sample signal sequence.

Each of the individual sample signal sequences may include a sequential second sample signal, and each of the individual sample signal sequences may be a sample signal sequence in which a predetermined number of sample signals are delayed compared to the individual sample signal sequences of the preceding order. For reference, each individual sample signal sequence may be generated simultaneously or sequentially in time, all output on the same clock, or sequentially output for multiple clocks. Therefore, the 'individual sample signal sequence of the preceding order' means that the sample signal sequence preceding the sequence or the sample sequence outputted first in time.

For example, if eight separate sample signal sequences are sample signal sequences delayed by one sample signal but the second number is eight, the first individual sample signal sequence is the sample signals from the first sample signal to the eighth sample signal. And a second individual sample signal sequence consists of sample signals from the second sample signal to the ninth sample signal. In this order, the last eighth individual sample signal sequence consists of sample signals from the seventh sample signal to the fifteenth sample signal. As a result, when the second number is eight, the first number is sixteen.

Meanwhile, the shared sample signal sequence output to the shared addition processor 130 is input by a predetermined number to a plurality of adders in the shared addition processor 130. In addition, the plurality of individual sample signal sequences output to the cross correlation processor 140 are individually input to each of the plurality of cross correlators in the cross correlation processor 140.

The shared addition processor 130 receives the shared sample signal sequence and adds the first sample signals included in the shared sample signal sequence by a predetermined number. The shared addition processor 130 outputs the addition result values in a plurality of paths.

For example, as shown in FIG. 2, the shared addition processor 130 adds two input sample signals I and outputs each addition result value to the cross correlation processor 140. In this case, the shared addition processor 130 outputs each addition result value through a plurality of paths, and the outputted addition result values are respectively input to a plurality of cross correlators in the cross correlation processor 140. As such, at least one of the addition result values added through the shared addition processor 130 may be shared by each cross correlator of the cross correlation processor 140.

1 again, the cross correlation processor 140 receives a plurality of individual sample signal sequences, and cross-correlates the second sample signals included in each individual sample signal sequence through each cross correlator.

Specifically, as shown in FIG. 2, the cross correlation processor 140 includes a plurality of cross correlators, and a plurality of cross correlators are connected in parallel.

The cross-correlators connected in parallel are each an individual sample signal sequence input from the sample signal processor 120, an addition result value input from the shared addition processor 130, and a reference signal sequence R input from the reference signal processor 150. Compute the cross-correlation value using.

2 illustrates that W cross correlators are connected to the cross correlation processor 140 in parallel, and the plurality of cross correlators includes an adder including a plurality of multiplexers and at least one adder, respectively. In this case, the plurality of cross correlators use the sample signal sequence I, the addition result value, and the reference signal sequence R input to the same clock as input data and driving control data of each multiplexer.

As such, the cross-correlation processor 140 cross-correlates a plurality of input signals, reference signals, and shared addition results through a multiplexer and a summer, thereby significantly reducing power consumption compared to the cross-correlation processing method using only a plurality of multipliers. There is an effect of reducing the circuit configuration efficiency.

Such a cross correlation method through the cross correlation processor 140 will be described in detail with reference to FIGS. 3 and 4.

1 again, the reference signal processor 150 outputs a plurality of reference signal sequences consisting of a plurality of reference signals. In this case, the reference signal processor 150 according to an embodiment of the present invention outputs reference signals having a sign bit value. For reference, each reference signal sequence includes a reference signal having a magnitude (ie, a number) corresponding to an individual sample signal sequence, and each reference signal sequence may be configured of different reference signals from other reference signal sequences. That is, different reference signals may be simultaneously input to the cross correlator, and thus, there is an effect of simultaneously performing cross-correlation processing between various reference signals and input signals without being limited to a specific reference signal. Such a reference signal sequence is input as drive control data of a plurality of multiplexers included in the cross correlator.

Hereinafter, the cross correlation processing scheme according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a detailed view of a cross correlation processing unit according to an embodiment of the present invention.

4 is a detailed diagram of a cross correlator according to an embodiment of the present invention.

First, the derivation process of the cross correlation processing equation applied to the cross correlation processor 140 according to an embodiment of the present invention to calculate the cross correlation value will be described with reference to FIGS. 3 and 4.

The reference signal processor 150 according to an embodiment of the present invention outputs a reference signal sequence by taking only a sign bit without representing the reference signal as a plurality of bits. This is because a signal of the reference signal waveform can be represented by a sign bit when using a reference signal waveform having excellent orthogonality. For example, the reference signal processor 150 takes a '1' bit if the reference signal value is a negative value and a '0' bit if the reference signal value is a positive value or zero.

In Equation 2, a function having a positive y value when x is 0 and a y value having a negative value when x is 1 is defined. That is, when x is the reference signal value R and y is the sample signal value I, the sign of the sample signal value may be changed and applied according to the reference signal value.

&Quot; (2) "

At this time, as shown in Equation 3 below, the sign of the y value may be inverted according to the x value. The symbol '~' in Equation 3 refers to an operator that inverts all bit values of the sample signal value.

&Quot; (3) "

On the other hand, in the case of using two's complement expressions for the functions of Equations 2 and 3, a circuit in which all bit values of the sample signal value (that is, the y value) are inverted and then added is added. Can be.

For example, in order to change the sign of a sample signal value, a method of adding 1 separately may be used, and a technique of calculating the value in advance may be used.

Under such conditions, the cross correlation function C (t) may be defined as shown in Equation 4 below.

&Quot; (4) "

On the other hand, when the sign of the corresponding sample signal value is applied according to the reference signal value as shown in Equation 2 and 3, the cross-correlation function defined in Equation 4 may be redefined as in Equation 5 below. .

<Equation 5>

However, when implementing the circuit according to Equation 5, at least N adders are required. As such, the cross-correlation device of which power consumption is reduced more than that of the cross-correlation device implemented according to Equation 5 may be implemented through Equations 6 to 12. According to Equations 6 to 12, a plurality of adders (for example, half adders) may be further reduced compared to Equation 5.

In detail, the cross-correlation function defined in Equation 4 may be expressed by Equation 7 by applying Equation 6 below. In this equation, S + is an index of signals having a positive or zero value in the reference signal R, and S- is an index of signals having a negative value in the reference signal.

<Equation 6>

<Equation 7>

이고 교집합이 공집합이므로 하기 수학식 8이 성립된다.In this case, the union of S + and S- is

Since the intersection is an empty set, Equation 8 is established.

<Equation 8>

According to Equation 8, Equation 4 may be replaced with Equation 9 below.

&Quot; (9) &quot;

In this case, in Equation 9, S may take one of S + and S-, and K has a value of -1 when S + is S- and +1 when S +. For reference, multiplying the K value may be implemented by a simple circuit. However, since the cross correlation value calculated by the cross correlator according to the exemplary embodiment of the present invention produces an absolute value, the K value will be ignored.

The first term in Equation 9 may be converted to Equation 10 and implemented using one register and two adders. In addition, since multiplying the second term by 2 in Equation 9 corresponds to a shift operation, a separate circuit implementation is not required. For reference, in the following Equation 10, the T (t) function is a value of the sum of the sample intervals that are subject to cross correlation.

&Quot; (10) &quot;

In addition, when the value of S is selected using Equation 11, the maximum number of adders required to calculate the second term in Equation 9 is N / 2. This is because the number of members of the union of S + and S− is N and the intersection is an empty set.

Equation (11)

Therefore, when implementing a circuit for cross-correlation processing using Equations 10 and 11, an adder close to half by adding one register as compared to a circuit implemented using Equation 5 (that is, N adders are required) (( N / 2) +2 required) can be saved.

On the other hand, the cross-correlation processing apparatus 100 according to an embodiment of the present invention supports various reference waveforms to perform cross-correlation processing between the sample signal and the reference signal.

In this case, when the cross correlation processor 140 according to an embodiment of the present invention performs cross correlation processing using a plurality of types of reference signals, the shared addition processor 130 is illustrated in FIGS. 3 and 4. A multiplexer circuit is used to connect each addition result output from the element with the corresponding sample signal I according to the S value.

However, as the number of reference signals is supported, the number of elements of the sample signal I connected to each reference signal for each cross correlator of the cross correlation processor 140 increases, thereby increasing the complexity of the circuit.

That is, when implementing a circuit based on Equations 10 and 11 compared to Equation 5, the number of adders close to half can be saved, but when various reference signals are used in cross correlation processing using Equations 10 and 11 The complexity of the multiplexer can be excessively high.

Therefore, by implementing a cross-correlator having a high sampling frequency of the input signal in a parallel circuit, the operating frequency of the circuit is lowered to meet the constraint of the operating frequency of the circuit or the power consumption due to the high-speed operation of the circuit.

At this time, the cross-correlation processing unit 140 according to an embodiment of the present invention uses the W parallel cross correlators within one clock period (clock period) according to the following Equation 12 according to the W cross-correlation values (C (t) ~ ( t + W-1)). That is, the operating frequency of the circuit can be lowered by W times based on the sampling frequency of the input signal.

&Quot; (12) &quot;

By applying Equation 12, the W independent cross correlators may cross-correlate the input sample signal by t by a parallel cross correlator number w to (t + w + n).

However, when implementing the W independent cross correlator circuits as shown in Equation 12, the area of the circuit may be increased by W times.

Therefore, based on the cross-correlation function of Equation 12, the cross-correlation function as shown in Equation 13 can be defined by applying the condition that K = 1, S = S- in Equation 9 above. That is, each cross correlator of the cross correlation processor 140 may be implemented with a plurality of adders and multiplexer circuits. For reference, S may be any of S + and S−.

Specifically, Equation 9 may be expressed as Equations 13 and 14 below.

&Quot; (13) &quot;

&Quot; (14) &quot;

Equation 14 represents a cross-correlation processing function of the cross correlator corresponding to the number W among the W cross correlators as shown in Equation 12 above.

In this case, the addition operation corresponding to the first condition in Equation 13 is performed by the adder of the shared addition processor 130.

In FIG. 3, an internal structure of the shared add processor 130 and a cross correlator and a connection relationship between the cross correlator of the parallel adder and the adders of the shared add processor 130 are illustrated.

That is, as shown in FIG. 3, the shared addition processor 130 groups the sample signals of the input shared sample signal sequence by two and adds them for each adder in the shared addition processor 130. The shared addition processor 130 provides the cross correlators with the operation result of each adder. As such, at least one of the addition result values calculated by the shared addition processor 130 is input to each of the parallel correlators, so that each cross correlator includes an adder for selectively adding only addition results between groups of sample signals. Can be configured.

In addition, in the crosscorrelator of the cross-correlation processing unit 130 according to an embodiment of the present invention, a predetermined number of multiplexers is set regardless of the type and number of reference waveforms (refer to 'four' in FIGS. 3 and 4). It takes only input data of, and since the default input data is 0, the complexity of the multiplexer is low.

The W cross correlators of the cross correlation processor 140 that have received the addition result of each adder of the shared addition processor 130 perform cross correlation processing according to Equations 15 to 18 below.

First, a function applied to each adder of the shared addition processor 130 is expressed by Equation 15 below. The addition result for each adder input for each W cross correlator may be defined by Equation 16 below, and the reference signal value input for each cross correlator may be defined by Equation 17 below. In addition, a sample signal value input for each of the W cross correlators may be defined by Equation 18 below.

&Quot; (15) &quot;

&Quot; (16) &quot;

&Quot; (17) &quot;

&Quot; (18) &quot;

The cross correlation processor 140 according to an embodiment of the present invention applies a condition according to Equations 16 to 18 to perform a cross correlation operation according to Equations 19 and 20.

&Quot; (19) &quot;

&Quot; (20) &quot;

Hereinafter, a method in which the cross-correlation apparatus 100 according to an embodiment of the present invention performs cross-correlation processing between a sample signal and a reference signal by applying Equations 19 and 20 will be described in detail with reference to FIGS. 3 and 4. Explain.

As shown in FIG. 3, the shared addition processor 130 receives a shared sample signal sequence including a first sample signal ('19' in FIG. 3). The shared addition processor 130 performs an addition process on a plurality of sample signal groups each consisting of a predetermined number ('2' in FIG. 3) sample signals among the shared sample signal sequences. That is, the plurality of adders included in the shared addition processor 130 add the two sample signals and output the two sample signals to the plurality of cross correlators.

In FIG. 3, a shared sample signal sequence including 19 sample signals from I (t + 0) to I (t + 18) is input to the shared addition processor 130.

Meanwhile, as shown in FIG. 3, each cross correlator of the cross correlation processor 140 includes a plurality of addition result values output from the shared addition processor 130, individual sample signal sequences output from the sample signal processor 120, and a reference. Reference signal sequences output from the signal processor 150 are respectively input.

3 shows that an individual sample signal sequence including a second (16 in FIG. 3) sample signal is input to each cross correlator. For reference, each individual sample signal sequence and a plurality of addition result values shown in FIG. 3 are not inputted to each cross correlator through a cross correlator of the preceding index, but each sample signal sequence and addition result values are stored through separate paths. It is input to each crosscorrelator.

Specifically, in FIG. 3, an individual sample signal sequence including 16 sample signals from I (t + 0) to I (t + 15) is input to the first cross correlator, and the first cross correlator is input to the second cross correlator. It is shown that an individual sample signal sequence including 16 sample signals from I (t + 1) to I (t + 16) in which one sample signal is delayed from the individual sample signal sequence input to is input. In this manner, individual sample signal sequences sequentially delayed by one sample signal are input to the W crosscorrelators.

For reference, in FIG. 3, four cross correlators are included in the cross correlation processor 140, but the number may be variously set. In this case, the number of sample signals included in the individual sample signal sequence and the shared sample signal sequence may be set according to the number of cross correlators. That is, the index of the cross correlator may be set by the difference between the number of sample signals included in the individual sample signal sequence and the number of sample signals included in the shared sample signal sequence. For example, when four cross-correlators are included in the cross correlation processor 140 as shown in FIG. 3, the indices of the cross correlators are set from 0 to 3. When the index of the first cross correlator is referred to as '0', the index of the last cross correlator is set to a value ('3' in FIG. 3) of the sample signal number difference between the shared sample signal sequence and the individual sample signal sequence.

As shown in FIG. 3, a plurality of addition result values of each addition result output from each adder of the shared addition processor 130 are input to each cross correlator through a plurality of paths. In other words, a number of addition results are shared and used in parallel by a cross correlator.

In this case, the shared addition processor 130 includes an adder shared by all crosscorrelators, an adder shared by some crosscorrelators, and an adder shared by one crosscorrelator. This is because the sample signal included in the individual sample signal sequence input to each cross correlator is delayed by one sample signal.

In addition, as shown in FIG. 3, a reference signal sequence R output from the reference signal processor 150 and a T value according to Equation 20 are input to each cross correlator of the cross correlation processor 140. The index of the signal sequence and the T value is the same as the cross correlator index. That is, the same number of reference signal sequences and T values as the number of cross correlators are input, and the reference signal sequences may be of different types.

In this case, each of the cross correlators of the cross correlation processor 140 calculates a cross correlation value Cw (t) according to Equations 19 and 20.

Specifically, as shown in FIG. 4, each cross correlator included in the cross correlation processor 140 according to an embodiment of the present invention inputs a sample signal and an addition result value included in an individual sample signal sequence as input data. And a plurality of multiplexers 141 that receive a reference signal included in the reference signal sequence as driving control data. In addition, each cross correlator includes an adder 142 that adds all of the values output through the multiplexer to calculate a cross correlation value. For reference, FIG. 4 illustrates the internal configuration of the W-th correlator in detail, and the internal configuration of each cross correlator is the same.

In this case, each multiplexer 141 receives two sample signals among the sample signals included in the inputted individual sample signal sequence as input data, and receives addition result values for the corresponding two sample signals as input data. Input the default value of 0 as input data. Each multiplexer 141 receives two reference signals from the input reference signal sequence R _W as driving control data. That is, the output path of the multiplexer is determined by using a 2-bit sign bit as a driving control signal, and one of zero, two sample signals, and an addition result value of the two sample signals is determined according to the reference signal value. Data is output through the multiplexer. Accordingly, through such a cross correlator, an operation of calculating a result value according to a reference signal condition as in Equation 19 may be implemented on consecutive sample signals.

In addition, the adder 142 included in the cross-correlator includes a plurality of adders for summing output values of the multiplexers 141 and a multiplier for multiplying a result value by summing output values of all the multiplexers 141. (Which can be replaced by a shift operation), and a subtractor which subtracts the result value of the multiplier from the T value. Through the summer 142, the calculation according to Equation 20 may be implemented to calculate the cross correlation value of each cross correlator.

As such, the cross-correlation apparatus 100 according to an exemplary embodiment may calculate cross-correlation values according to Equation 20 by driving cross-correlators including a plurality of adders and multiplexers in parallel. As such, only the adder and multiplexer can handle cross-correlation between the input signal and the reference signal, resulting in higher power and circuit configuration efficiency and faster processing speeds. In addition, by using the reference signal as a drive control signal of the multiplexer, various reference signals can be conveniently applied to the cross correlator.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: cross-correlation device 110: input signal processing unit
120: sample signal processing unit 130: shared addition processing unit
140: cross correlation processing unit 141: multiplexer
142: summer 150: reference signal processor

Claims (8)

In the cross-correlation device for performing a cross-correlation process between the input signal and the reference signal,
An input signal processor configured to output N sample signals each sampled by the input signal;
A sample signal processor configured to receive the N sample signals and output a plurality of sample signal sequences each including M sample signals among the N sample signals;
A reference signal processor configured to output a reference signal sequence including the reference signals corresponding to the sample signal sequence;
A shared addition processor configured to receive the N sample signals and perform an addition process for each sample signal group including two or more sample signals to generate an addition result value, and output a plurality of the addition result values; And
A cross-correlation processing unit configured to receive the sample signal sequence, the reference signal sequence, and the addition result value, and perform cross-correlation processing with the reference signal sequence in parallel for each of the plurality of sample signal sequences to calculate a cross correlation value;
The cross correlation processing unit includes a plurality of cross correlators driving in parallel,
For each cross correlator,
A plurality of multiplexers each receiving a sample signal included in the sample signal sequence and the addition result value as input data, and receiving a reference signal included in the reference signal sequence as driving control data, respectively; And
And a summer for adding all of the values outputted through the multiplexers to calculate the cross-correlation value. The method of claim 1,
The cross correlation processing unit,
Cross-correlation apparatus for calculating the cross-correlation value through the cross-correlation function according to the equation (1).
&Quot; (1) &quot;

,

(Where Cw (t) is a cross-correlation value, I is a sample signal value and R is a reference signal value) The method of claim 1,
The reference signal processor,
Outputting the reference signal sequence for each of the plurality of types of reference signals,
And the plurality of types of reference signals are signal waveforms different from each other. delete The method of claim 1,
The multiplexer,
And a sum result value for each of the sample signal group and the sample signal group, and each of the two or more reference signals. The method of claim 1,
The plurality of cross correlators,
And receiving each of the different sample signal sequences, and sharing and using a plurality of addition result values among the input addition result values. The method of claim 1,
The sample signal processing unit,
And a plurality of sample signal sequences sequentially delayed by a predetermined number of sample signals. The method of claim 1,
And wherein the reference signal sequence consists of a plurality of sign bits.

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