KR101261807B1 - Data transmitting and receiving device with reducing the number of transmission line - Google Patents

Abstract

A data transmission / reception apparatus capable of reducing the number of transmission lines is posted. A data transmitting and receiving device of the present invention comprises a data transmitting circuit for generating and transmitting a data signal, the data signal including: the data transmitting circuit reflecting the data bits of the data packet in serial; A transmission line for transmitting the data signal; And a data receiving circuit configured to receive the data signal transmitted through the transmission line, generate an internal clock signal according to the data signal, and sample the data signal according to the internal clock signal to restore the data bits. The internal clock signal has an internal clock period based on a transition of the data signal, and the period reference of the internal clock signal is reset by a difference in data values between successive data bits in one data packet. The data receiving circuit is provided. According to the data transmitting and receiving device and the data transmitting and receiving method of the present invention, in the data communication between different devices, the number of transmission lines used as data flow lines is reduced.

Description

DATA TRANSMITTING AND RECEIVING DEVICE WITH REDUCING THE NUMBER OF TRANSMISSION LINE}

The present invention relates to a data transmission and reception apparatus and a data transmission and reception method, and more particularly, to a data transmission and reception apparatus for transmitting and receiving data information together with clock information.

In recent years, as electronic and computer technologies have evolved, communication of information between different devices in close proximity or in isolation has become increasingly important. For example, it is becoming important to communicate between different chips on circuit boards, different circuit boards in a system, and different systems.

At this time, for communication between different systems, it is required to transmit and receive clock information together with the data information. Here, the clock information serves as a reference for operating different systems at appropriate and effective timing.

And, in data communication between different devices, it is one of important problems to reduce the number of transmission lines used as data flow lines.

Therefore, in data communication between different devices, development of a data transmission / reception apparatus capable of reducing the number of transmission lines used as data flow lines is required.

An object of the present invention is to provide a data transmission and reception apparatus that can reduce the number of transmission lines used as data flow lines in data communication between different devices.

One aspect of the present invention for achieving the above technical problem relates to a data transmitting and receiving device for transmitting and receiving a data packet consisting of a plurality of data bits. A data transmitting and receiving device of the present invention comprises a data transmitting circuit for generating and transmitting a data signal, the data signal including: the data transmitting circuit reflecting the data bits of the data packet in serial; A transmission line for transmitting the data signal; And a data receiving circuit configured to receive the data signal transmitted through the transmission line, generate an internal clock signal according to the data signal, and sample the data signal according to the internal clock signal to restore the data bits. The internal clock signal has an internal clock period based on a transition of the data signal, and the period reference of the internal clock signal is generated by a difference in data values between successive data bits in one data packet. And said data receiving circuit reset in response to every transition of said data signal to be made.

According to the data transmitting and receiving device and the data transmitting and receiving method of the present invention, in the data communication between different devices, the number of transmission lines used as data flow lines is reduced.

A brief description of each drawing used in the present invention is provided.
1 is a view schematically showing a data transmission and reception apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram for describing generation of an internal clock signal in the data transceiver of FIG. 1.
3 is a diagram illustrating in detail the data transmission circuit of FIG. 1.
4 is a diagram illustrating the data receiving circuit of FIG. 1 in detail.
5 is a diagram illustrating the internal clock generator of FIG. 4 in more detail.
FIG. 6 is a diagram for describing an operation of a period checking mode in the internal clock generator of FIG. 5.
FIG. 7 is a diagram illustrating the transition detection block of FIG. 5 in detail.
8 is a view illustrating in detail the internal clock generation part of FIG.
9 is a diagram illustrating the FIG. 8 half-cycle transition unit in more detail.
FIG. 10 is a circuit diagram illustrating the rise detection group of FIG. 9 in detail.
FIG. 11 is a circuit diagram illustrating the falling detection group of FIG. 9 in detail.
FIG. 12 is a diagram illustrating the rising drive group of FIG. 9 in detail.
FIG. 13 is a diagram specifically illustrating a falling drive group of FIG. 9.
14A and 14B are timing diagrams for explaining the operation of the main signal of the internal clock generator of the present invention.

For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. In understanding each of the figures, it should be noted that like parts are denoted by the same reference numerals whenever possible. Further, detailed descriptions of known functions and configurations that may be unnecessarily obscured by the gist of the present invention are omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view schematically showing a data transmission and reception apparatus according to an embodiment of the present invention. Referring to FIG. 1, a data transmission and reception apparatus of the present invention includes a data transmission circuit PATSD, a transmission line LTR, and a data reception circuit PATRV.

The data transmission circuit PATSD generates and transmits a data signal DIN. In this case, as illustrated in FIG. 2, the data signal DIN is a signal that reflects a plurality of data bits DB1 to DB6 as a serial. That is, the data signal DIN is a signal that sequentially reflects data values of the data bits DB1 to DB6 in synchronization with a system clock SYS_CLK, which is a reference clock of the data transmission circuit PATSD.

In this case, as shown in FIG. 2, the data packets PA_DAT1 to PA_DAT3 include data values of the data bits DB1 to DB6. In addition, the data packets PA_DAT1 to PA_DAT3 may include a transition induction bit DT.

The data bits DB1 to DB6 may be provided in a serial or parallel manner from a data storage device such as a memory (not shown) included in an external or internal device. In the present specification, the data bits DB1 to DB6 are described on the assumption that they are provided in parallel from a data storage device (not shown).

The transmission line LTR transmits the data signal DIN from the data transmission circuit PATSD to the data reception circuit PATRV.

The data receiving circuit PATRV receives the data signal DIN transmitted through the transmission line LTR and generates an internal clock signal ICLK according to the data signal DIN. The data receiving circuit PATRV restores the data bits DB1 to DB6 by sampling the data signal DIN according to the internal clock signal ICLK.

In this case, the internal clock signal ICLK is a clock having an internal clock period TCLK based on a period of transition of the data signal DIN. In addition, the period reference of the internal clock signal ICLK is the data signal DIN generated by a difference in data values between the consecutive data bits DB1 to DB6 in one data packet PA_DAT1 to PA_DAT3. It is reset in response to every transition of.

In other words, when a new transition of the data signal DIN occurs within the transition period TW, the internal clock signal ICLK is a new signal of the data signal DIN. The transition is based on the transition (see TR in FIG. 2).

When the new transition of the data signal DIN does not occur within the transition period TW, the internal clock signal ICLK transitions with respect to the previous transition at every transition period TW. (See TC of Figure 2)

In the present embodiment, the transition period TW is one half of the internal clock period TCLK.

Meanwhile, in the data transmitting and receiving device of the present invention, the transition induction bit DT included in each of the data packets PA_DAT1 to PA_DAT3 is for intentionally generating a transition of the data signal DIN. The data values of DB1 to DB6 are continuously the same, thereby preventing and eliminating accumulation of errors in timing of the internal clock signal ICLK with respect to the system clock SYS_CLK.

The transition induction bit DT may be generated in various ways.

In the present embodiment, the transition induction bit DT is shown and described as being assigned to the first bit in each of the data packets PA_DAT1 to PA_DAT3 as the inversion data bits / DB1 of the first data bit DB1. . However, the transition induction bit DT may be an inverted data bit of other data bits DB2 to DB6, in which case it is allocated adjacent to the corresponding data bits DB2 to DB6.

In addition, the transition induction bit DT may be generated as an inverted data bit of the specified data bits DB1 to DB6 only when the data values of the data bits DB1 to DB6 in one or two or more data packets are all the same. It may be implemented, which can be easily implemented by those skilled in the art.

Subsequently, each component of the data transmitting and receiving apparatus of the present invention is described in more detail.

FIG. 3 is a diagram illustrating in detail the data transmission circuit PATSD of FIG. 1. Referring to FIG. 3, the data transmission circuit PATSD includes an inverter INV, an integrated serial data generating means GMSD, and a driver DRV.

The inverter INV is one of the data bits DB1 to DB6, which in this embodiment, inverts the data bit DB1 to generate the transition induction bit DT.

The integrated serial data generating means GMSD receives the data bits DB1 to DB6 and the transition induction bit DT. In addition, the integrated serial data generating means GMSD sequentially outputs the transition induction bit DT and the data bits DB1 to DB6 in synchronization with the system clock SYS_CLK.

The driver DRV has a voltage level corresponding to the transition induction bit DT and the data values of the data bits DB1 to DB6 sequentially output from the integrated serial data generation means GMSD. The data signal DIN is provided to the transmission line LTR in synchronization with the system clock SYS_CLK.

4 is a diagram illustrating in detail the data receiving circuit PATRV of FIG. 1. Referring to FIG. 4, an internal clock generator GICK and a sample recoverer SARC are provided.

The internal clock generator GICK receives the data signal XCLK and generates the internal clock signal ICLK. In this case, the internal clock signal ICLK has the internal clock period TCLK based on the transition of the data signal XCLK.

The sample reconstructor SARC reconstructs and outputs the data bits DB1 to DB6 by sampling the data signal DIN according to the internal clock signal ICLK.

Subsequently, the internal clock generator GICK for generating the internal clock signal ICLK of the present invention is described in detail.

FIG. 5 is a diagram illustrating the internal clock generator GICK of FIG. 4 in more detail. Referring to FIG. 5, the internal clock generator GICK includes a transition detection block 100 and an internal clock generation block BGIC.

The transition detection block 100 detects the transition of the data signal DIN and provides 'transition information'. In the present embodiment, the 'transition information' includes a rising transition confirmation signal PCTA_R and a falling transition confirmation signal PCTA_F.

The internal clock generation block BGIC checks the clock period of the data signal DIN through the transmission line LTR in the period confirmation mode (MTDG of FIG. 6) in which the mode signal XMOD becomes “H”. Generate periodic digital data (TDIG).

In this case, the clock period of the data signal DIN corresponds to the internal clock period of the internal clock signal ICLK (TCLK in FIG. 6).

In addition, the internal clock generation block BGIC is obtained from the transition of the data signal DIN detected through the transition information in the internal clock generation mode (MGIC of FIG. 6) in which the mode signal XMOD becomes “L”. The internal clock signal ICLK is repeatedly generated as the transition time (TW in FIG. 6) elapses. In this case, the transition time TW is determined by the periodic digital data TDIG.

In the present embodiment, as described above, the transition time TW is 1/2 of the internal clock period TCLK of the data signal DIN.

In this way, the internal clock cycle TCLK of the time concept is checked to generate periodic digital data TDIG, which is digital data, and the transition time TW is determined using the periodic digital data TDIG. It can be easily implemented by those skilled in the art using a counter), etc. In the present specification, for the sake of simplicity, a detailed description thereof will be omitted.

FIG. 7 is a diagram illustrating the transition detection block 100 of FIG. 5 in detail. Referring to FIG. 7, the transition detection block 100 includes a rising transition checking unit 110 and a falling transition checking unit 120.

The rising transition confirming unit 110 provides the rising transition confirmation signal PCTA_R generated by an "L" pulse in response to the rising transition of the data signal DIN (see t11 in FIG. 14A).

The falling transition confirming unit 120 provides the falling transition confirmation signal PCTA_F generated by an "L" pulse in response to the falling transition of the data signal DIN (see t12 in FIG. 14A).

Referring to FIG. 5 again, the internal clock generation block BGIC includes an internal clock generation part 200 and an internal clock transition part 300.

The internal clock generation part 200 generates the periodic digital data TDIG in the period confirmation mode MTDG. In addition, the internal clock generation part 200 repeats the "L" pulse from the transition of the data signal DIN detected through the transition information in the internal clock generation mode MGIC as the transition time elapses. Provide the generated clock transition signal XCKT.

FIG. 8 is a diagram illustrating in detail the internal clock generation part 200 of FIG. 1. Referring to FIG. 8, the internal clock generation part 200 includes a rising transition response unit 210, a falling transition response unit 220, an integrated transition response unit 230, and an internal clock transition unit PICT.

The rising transition response unit 210 generates a rising transition response signal PCTB_R in response to the rising transition confirmation signal PCTA_R. In this case, the rising transition response signal PCTB_R is generated as an “L” pulse in response to a lagging edge of the pulse of the rising transition confirmation signal PCTA_R (see t21 in FIG. 14A).

The falling transition response unit 220 generates a falling transition response signal PCTB_F in response to the falling transition confirmation signal PCTA_F. At this time, the falling transition response signal PCTB_F is generated as an “L” pulse in response to the trailing end of the pulse of the falling transition confirmation signal PCTA_F (see t22 in FIG. 14A).

The integrated transition response unit 230 provides a reset signal RST in response to the rising transition confirmation signal PCTA_R and the falling transition confirmation signal PCTA_F. At this time, the reset signal RST is generated as an "L" pulse in response to the leading edge of the pulse of the rising transition confirmation signal PCTA_R and the falling transition confirmation signal PCTA_F (t23 in FIG. 14A). And t24s).

The internal clock transition unit PICT generates the periodic digital data TDIG in the period confirmation mode MTDG. The internal clock transition unit PICT provides the clock transition signal XCKT in response to the rising transition response signal PCTB_R and the falling transition response signal PCTB_F in the internal clock generation mode MGIC. . In this case, the clock transition signal XCKT is generated as an "L" pulse in response to the pulses of the rising transition response signal PCTB_R and the falling transition response signal PCTB_F. In addition, the clock transition signal XCKT is repeatedly generated as a pulse for each of the transition time TW in the internal clock generation mode MGIC, and the generation of the pulse is blocked in response to the reset signal RST.

Specifically, the internal clock transition unit PICT includes a half cycle transition unit 240 and a clock transition generation unit 250.

The half-cycle transition unit 240 generates the periodic digital data TDIG in the period confirmation mode MTDG, and generates the rising half-cycle signal XHT_R and the falling half-cycle signal XHT_F in the internal clock generation mode MGIC. Occurs.

At this time, the rising half-cycle signal XHT_R generates an "L" pulse with a delay of the transition time TW in response to the rising transition response signal PCTB_R (see t31 in FIG. 14A). The rising half-cycle signal XHT_R generates an "L" pulse with a delay of the transition time TW relative to the generation of the pulse of the falling half-cycle signal XHT_F. However, when the pulse of the reset signal RST is generated within the transition time TW, the pulse generation of the rising half-cycle signal XHT_R is blocked (see t32 in FIG. 14A).

The falling half-cycle signal XHT_F generates an "L" pulse with a delay of the transition time TW in response to the falling transition response signal PCTB_F (see t33 in FIG. 14A). The falling half-cycle signal XHT_F generates an "L" pulse with a delay of the transition time TW relative to the generation of the pulse of the rising half-cycle signal XHT_R. However, when the pulse of the reset signal RST is generated within the transition time TW, the pulse generation of the falling half-cycle signal XHT_F is blocked (see t34 in FIG. 14A).

FIG. 9 illustrates the half-cycle transition unit 240 of FIG. 4 in more detail. Referring to FIG. 9, the half-cycle transition unit 240 includes a rising sensing group 241, a rising driving group 243, a falling sensing group 245, and a falling driving group 247.

The rising detection group 241 receives the rising transition response signal PCTB_R, the rising half-cycle signal XHT_R, the reset signal RST, and the falling transition driving signal EN_F provided from the falling detection group 245. Receive and provide a rising transition drive signal EN_R. In this case, the rising transition drive signal EN_R is a pulse of the rising transition response signal PCTB_R generated when the reset signal RST is activated at the "H" state, and "L" of the falling transition drive signal EN_F. In response to deactivation of the furnace, it is activated with "H" (see t41 and t42 in FIG. 14A), and in response to the pulse of the reset signal RST and the rising half-cycle signal XHT_R, it is deactivated with "L" (FIG. 14A). T43 and t44).

The rising drive group 243 receives the rising transition drive signal EN_R and generates the rising half-cycle signal XHT_R. The rising half-cycle signal XHT_R generates a pulse at " L " in response to the transition time TW in response to activation of the rising transition drive signal EN_R at " H " (see t45 in FIG. 14A). At this time, if the deactivation of the rising transition drive signal EN_R to "L" occurs during the transition time TW, the pulse of the rising half-cycle signal XHT_R is not generated because it is blocked (see t46 in FIG. 14A). ).

The falling detection group 245 receives the falling transition response signal PCTB_F, the falling half-cycle signal XHT_F, the reset signal RST, and the rising transition driving signal EN_R provided from the rising detection group 241. And a falling transition drive signal EN_F. In this case, the falling transition drive signal EN_F is a pulse of the falling transition response signal PCTB_F and the "L" of the rising transition drive signal EN_R generated when the reset signal RST is activated at the "H" state. In response to deactivation of the furnace, it is activated as "H" (see t51 and t52 in FIG. 14A), and in response to the pulses of the reset signal RST and the falling half-cycle signal XHT_F, it is deactivated as "L" (FIG. 14A). T53 and t54).

The falling drive group 247 receives the falling transition drive signal EN_F and generates the falling half-cycle signal XHT_F. The falling half-cycle signal XHT_F generates a pulse at " L " in response to the transition time TW delaying the activation of the falling transition drive signal EN_F to " H " (see t55 in FIG. 14A). At this time, when the deactivation of the falling transition drive signal EN_F generated to the "L" occurs during the transition time TW, the pulse of the falling half-cycle signal XHT_F is cut off and is not generated (Fig. 14A). t56).

FIG. 10 is a circuit diagram illustrating the rise detection group 241 of FIG. 9 in detail. Referring to FIG. 10, the rise detection group 241 includes a first rise logic logic 241a and a second rise logic logic 241b.

The first rising logic logic 241a receives the rising transition response signal PCTB_R, the falling transition driving signal EN_F, and the rising output signal n241 output from the second rising logic logic 241b. The rising transition drive signal EN_R is generated. In this case, the rising transition driving signal EN_R is activated as "H" in response to the "L" pulse of the rising transition response signal PCTB_R and the falling transition driving signal EN_F, and the rising output signal n241. In response to the activation of "L" is deactivated.

The second rising logic logic 241b receives the reset signal RST, the rising half-cycle signal XHT_R, and the rising transition driving signal EN_R, and generates the rising output signal n241. In this case, the rising output signal n241 is activated as "H" in response to the "L" pulse of the reset signal RST and the rising half-cycle signal XHT_R, and is activated to activate the rising transition drive signal EN_R. In response, it is deactivated to "L".

FIG. 11 is a circuit diagram illustrating the fall detection group 245 of FIG. 9 in detail. Referring to FIG. 11, the falling detection group 245 includes a first falling logic logic 245a and a second falling logic logic 245b.

The first falling logic logic 245a receives the falling output signal n245 output from the falling transition response signal PCTB_F, the rising transition driving signal EN_R, and the second falling logic logic 245b. The falling transition drive signal EN_F is generated. In this case, the falling transition drive signal EN_F is activated as "H" in response to the "L" pulse of the falling transition response signal PCTB_F and the rising transition drive signal EN_R, and the falling output signal n245. In response to the activation of "L" is deactivated.

The second falling logic logic 245b receives the reset signal RST, the falling half-cycle signal XHT_F, and the falling transition drive signal EN_F, and generates the falling output signal n245. In this case, the falling output signal n245 is activated as “H” in response to the “L” pulse of the reset signal RST and the falling half-cycle signal XHT_F, and the activation of the falling transition drive signal EN_F is performed. In response, it is deactivated to "L".

FIG. 12 is a diagram illustrating the lift drive group 243 of FIG. 9 in detail. Referring to FIG. 12, the rising drive group 243 includes a divider 243a, a feeder 243b, an oscillator 243c, a counter 243d, a half cycle latch 243e, and a comparator 243f.

The divider 243a enlarges the period of the data signal DIN by 2 times and outputs the period extended signal EDN1. The feedbacker 243b outputs any one of the periodic extension signal EDN1 and the rising transition drive signal EN_R as the enable signal XEN1 in accordance with the mode signal XMOD. In the present embodiment, in the period confirmation mode in which the mode signal XMOD becomes " H ", the period extension signal XEN1 is selected and output as the enable signal XEN1. In the internal clock generation mode in which the mode signal XMOD becomes "L", the rising transition drive signal EN_R is selected and output as the enable signal XEN1.

The oscillator 243c is enabled in response to the transition of the enable signal XEN1 to " H " and generates an oscillation signal OSC1. The counter 243d is reset in response to the transition of the enable signal XEN1 to " H ", and counts the number of transitions of the oscillation signal OSC1 to " H " to generate a counting signal CNT1. .

The half period latch 243e resets in response to the transition of the mode signal XMOD to " H ". In response to the transition of the mode signal XMOD to " L ", the half-cycle latch 243e divides the data value of the counting signal CNT1 by 1/2 to latch the periodic digital data TDIG. Occurs. In the present embodiment, the processing for the remaining value may be performed by the method of rounding up or down, and a separate circuit corresponding to the remaining value may be configured.

In this case, the periodic digital data TDIG has a data value corresponding to the period of the data signal DIN.

In the internal clock generation mode, the comparator 243f generates the rising half-cycle signal XHT_R generated by an “L” pulse when the counting signal CNT1 coincides with the periodic digital data TDIG. do.

As a result, in the internal clock generation mode, the rising half-cycle signal XHT_R turns into an "L" pulse after the half-cycle of the data signal DIN has elapsed from the end of the "L" pulse of the rising-shift drive signal EN_R. Is generated.

FIG. 13 is a view illustrating the descending driving group 247 of FIG. 9 in detail. Referring to FIG. 13, the lower driving group 247 includes a divider 247a, a mixer 247b, an oscillator 247c, a counter 247d, a half cycle latch 247e, and a comparator 247f.

The divider 247a enlarges the period of the data signal DIN by 2 times and outputs it as a period extension signal EDN2. The feedback signal 247b outputs one of the period extension signal EDN2 and the falling transition drive signal EN_F as the enable signal XEN2 according to the mode signal XMOD. In the present embodiment, in the period confirmation mode in which the mode signal XMOD becomes " H ", the period extension signal XEN2 is selected and output as the enable signal XEN2. In the internal clock generation mode in which the mode signal XMOD becomes "L", the falling transition drive signal EN_F is selected and output as the enable signal XEN2.

The oscillator 247c is enabled in response to the transition of the enable signal XEN2 to " H " and generates an oscillation signal OSC2. The counter 247d is reset in response to the transition of the enable signal XEN2 to " H ", and generates a counting signal CNT2 by counting the number of transitions of the oscillation signal OSC2 to " H ". .

The half cycle latch 247e resets in response to the transition of the mode signal XMOD to " H ". The half-cycle latch 247e divides the data value of the counting signal CNT2 by 1/2 in response to the transition of the mode signal XMOD to " L " to latch the periodic digital data TDIG. Occurs. In the present embodiment, the processing for the remaining value may be performed by the method of rounding up or down, and a separate circuit corresponding to the remaining value may be configured.

In this case, the periodic digital data TDIG has a data value corresponding to the period of the data signal DIN.

In the internal clock generation mode, the comparator 243f generates the falling half-cycle signal XHT_F generated by an “L” pulse when the counting signal CNT2 coincides with the periodic digital data TDIG. do.

As a result, in the internal clock generation mode, the falling half-cycle signal XHT_F is turned into an "L" pulse after the half-cycle of the data signal DIN has elapsed from the end of the "L" pulse of the falling transition drive signal EN_F. Is generated.

In this embodiment, the rising drive group 243 and the falling drive group 247 is implemented in the same configuration. In this case, if the process difference is ignored, the periodic digital data of the rising drive group 243 and the periodic digital data of the falling drive group 247 are the same. Therefore, in the present specification, for convenience of understanding, the periodic digital data of the rising drive group 243 and the periodic digital data of the falling drive group 247 are denoted by the same reference numerals.

Referring back to FIG. 8, the clock transition generation unit 250 may be configured to the rising transition response signal PCTB_R, the rising half-cycle signal XHT_R, the falling transition response signal PCTB_F, and the falling half-cycle signal XHT_F. Generate the transition clock signal XCKT in response.

In this case, when any one of the rising transition response signal PCTB_R, the rising half cycle signal XHT_R, the falling transition response signal PCTB_F and the falling half cycle signal XHT_F occurs as “L”, the transition clock signal (XCKT) also generates an "L" pulse (see Fig. 14A).

Referring back to FIG. 5, the internal clock transition part 300 generates the internal clock signal ICLK in response to the clock transition signal XCKT. At this time, the internal clock signal ICLK alternately transitions a logic state in response to a pulse of the clock transition signal XCKT.

Accordingly, the internal clock signal ICLK is shifted in response to the transition of the data signal DIN, as shown in FIG. 14B, and every fixed transition time TW even when the data signal DIN is not transitioned. Alternately transitions.

The internal clock generator GICK may generate the internal clock signal ICLK using the internal clock period TCLK from the data signal DIN.

As described above, in the data transmitting and receiving apparatus of the present invention, in addition to the data information, the clock information is transmitted and received in one data signal. Therefore, according to the data transmission / reception apparatus and the data transmission / reception method of the present invention, in the data communication between different devices, the number of transmission lines used as data flow lines is reduced.

Further, in the data transmitting and receiving apparatus of the present invention, the data signal provided from the data transmitting circuit to the data receiving circuit has one voltage level at the "H" level and the "L" level, respectively. In other words, the data signal is a digital value. Therefore, in the data transmitting and receiving apparatus of the present invention, a separate analog voltage sensing circuit for identifying the voltage level of the data signal is not required. Therefore, the data transmitting and receiving apparatus of the present invention has the advantage that the circuit configuration is simple.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (5)

In the data transmitting and receiving device for transmitting and receiving a data packet consisting of a plurality of data bits,
A data transmission circuit for generating and transmitting a data signal, the data signal comprising: the data transmission circuit for serially reflecting the data bits of the data packet;
A transmission line for transmitting the data signal; And
A data receiving circuit for receiving the data signal transmitted through the transmission line, generating an internal clock signal according to the data signal, and sampling the data signal according to the internal clock signal to restore the data bits. The internal clock signal has an internal clock period based on the transition of the data signal, and the period reference of the internal clock signal is generated by a difference in data values between successive data bits in one data packet. And said data receiving circuit reset in response to each transition of said data signal.
The method of claim 1, wherein the data receiving circuit
An internal clock generator configured to generate the internal clock signal having the internal clock period based on the transition of the data signal; And
And a sample decompressor for reconstructing the data bits by sampling the data signal according to the internal clock signal.
The method of claim 2, wherein the internal clock generator
A transition detection block for sensing a transition of the data signal; And
And an internal clock generation block configured to generate an internal clock signal that transitions according to a transition time with respect to the transition of the data signal detected by the transition detection block.
The method of claim 3, wherein the transition detection block is
A rising transition confirming unit providing a rising transition confirming signal in response to the rising transition of the data signal; And
And a falling transition confirmation unit for providing a falling transition confirmation signal in response to the falling transition of the data signal.
The method of claim 3, wherein the internal clock generation block is
An internal clock generation generates periodic digital data in a periodic confirmation mode and provides a clock transition signal generated by a pulse every elapse of the transition time from the transition of the data signal detected by the transition detection block in the internal clock generation mode. The internal clock generation part, wherein the transition time is determined by the periodic digital data; And
And an internal clock transition part for generating the internal clock signal in which a logic state alternately transitions in response to a pulse of the clock transition signal.

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