KR101233175B1 - Method For Encoding And Decoding Turbo Code With Continuous Length - Google Patents

Abstract

The present invention relates to a turbo code encoding and decoding method having a continuous length. According to the present invention, a frequency code of a system is improved by inserting temporary bits corresponding to a difference between a length required for interleaving and an input sequence for encoding a turbo code having a continuous length, and then puncturing them prior to transmission. It is not reduced, and the supplementary signal can be inserted so that the received signal has the required length again at the decoding stage, so that turbo code encoding and decoding of continuous length can be effectively performed.

Turbo Code, Temporary Bits, Basic Interleaver

Description

Method for Encoding And Decoding Turbo Code With Continuous Length

1 shows the basic structure of a turbo encoder.

2 is a diagram showing the basic structure of a turbo decoder.

3 illustrates a structure for encoding a turbo code having a continuous length using temporary bits in accordance with an embodiment of the present invention.

4 illustrates a structure for receiving and decoding a signal having a continuous length encoded by the structure shown in FIG.

TECHNICAL FIELD The present invention relates to wireless communication technology, and more particularly to a method of encoding and decoding turbo codes having a continuous length.

FIG. 1 is a diagram illustrating a basic structure of a turbo encoder.

The turbo code (hereinafter referred to as "TC") is a code obtained by connecting two recursive symmetric convolutional codes in parallel using an interleaver. The TC outputs the input data X of the turbo encoder as shown in FIG. 1 as structured bits, and encodes the structured bits and the input data by the first configuration encoder ENC ₁ 101. Parity bits Y ₁ , and the interleaved input data by the interleaver 102, and then generated through a combination with the parity bits Y ₂ encoded by the second configuration encoder EN ₂ 103. .

The performance of TC is better when the minimum Hamming Distance ("MHD") is larger. Such MHD can be represented by the number of bits having different information in the neighbor position corresponding to each sequence.In general, when the sequence consisting of 000 .. is used as the reference sequence, the MHD is the number of bits having a difference from the reference sequence. It can be represented by the number of weights (ie, "1") included in each sequence. Therefore, such MHD is affected by preventing the same information from being located between neighboring positions of the sequence inputted to the RSC 1 configuration encoder 101 and the RSC 2 configuration encoder 103, and such performance is affected. It may be dictated by the interleaver 102. In FIG. 1, an interleaver using Regular Rectangular Permutation, which reads a sequence of length k in the row direction of a rectangular matrix of M * N bits and reads it in the column direction, is used as an interleaver. As shown.

2 is a diagram illustrating a basic structure of a turbo decoder.

The decoder which decodes the TC comprises two component decoders 201 and 203 symmetrically with the encoder shown in FIG. 1, and these two component decoders 201 and 203 repeatedly give additional information. Receive and decoding is performed. That is, the first component decoder 201 (hereinafter “DEC ₁ ”) corresponds to the received signal of the input data X, the first parity bit Y ₁ , and the second parity bit Y ₂ transmitted from the transmitter. After calculating R ^X , R ^Y1 , and R ^Y2 , and calculating the side information corresponding to the entire length of the received signal, the calculated side information is interleaved by the interleaver 202 to perform a second component decoder 203 (hereinafter referred to as “DEC ₂ ”). Used by. Incidental information calculated by DEC ₂ 203 is deinterleaved by reverse interleaver 204 and used again in DEC ₁ 201. As such, the collateral information transmitted and received by two component decoders, such as DEC ₁ and DEC ₂ , is repeatedly calculated and updated in these component decoders, so that TC exhibits good performance.

The above-described configuration decoder first calculates a forward metric, a backward metric, and a branch metric in order to calculate the side information. In this case, instead of calculating the three metrics for the total length, a constituent encoder divides the total length into several windows and sequentially calculates the three metrics for each window, and calculates side information as much as the window length. There is a way.

In this way, when the unit information is calculated for all windows sequentially and the calculation of the unit information is completed for the entire length, the calculated unit information is interleaved or deinterleaved to calculate new (updated) unit information at different component decoders. It is used to As described above, a method of sequentially calculating the side information as much as the window length is called sliding window decoding, and is an implementation technique of a general TC decoder.

 Meanwhile, in the above-described sliding window decoding, there is a method in which each window simultaneously calculates the side information in parallel without sequentially calculating the side information for each window, which is called a parallel decoding method of TC.

Conventional turbo encoders and decoders as shown in Figs. 1 and 2 exist in which the length of the interleaver used for a particular purpose is limited. For example, in the case of the ARP interleaver for avoiding a specific RTZ sequence in the interleaved sequence through the RP interleaver used in the encoder side shown in FIG. 1, only the multiple length of the period of the fluctuation vector used in the ARP is used. Can have Such problems have been invented by the present inventors, filed by the present applicant, and are incorporated herein by reference, which include "Interleaver providing methods for providing continuous lengths, interleaving methods and turbo encoders thereby (Patent Application No. 2006- 103483).

In addition, in parallel decoding in the decoding stage illustrated in FIG. 2, windows of each component decoder must connect different memory banks at one unit time in order to avoid memory bank contention problems. The length of the interleaver used for decoding is limited to have a multiple length of the number of windows of each component decoder. Such problems have been invented by the present inventors, filed by the present applicants, and are incorporated herein by reference, and include "interleaver providing methods, interleaving methods and decoding methods using the same. 0105881).

Accordingly, in order to solve the length limitation problem of the interleaver including the above-described example, various techniques are limited, and in particular, the length limitation problem of the interleaver using temporary bits to maintain the conventional encoder and decoder configuration as it is. In this case, a method for easily performing decoding is required.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to perform interleaving and turbo code encoding through the concept of temporary bits to provide an interleaver of continuous length, and to perform decoding in the decoding stage using the characteristics of the temporary bits. It is to provide a method for decoding a received signal more easily.

In addition, by using the basic interleaver concept set to perform interleaving for parallel decoding without memory bank contention and ARP interleaving to avoid a specific RTZ sequence using the encoding and decoding method using temporary bits as described above, It is intended to provide a method that enables ARP interleaving and / or continuous length parallel decoding.

Turbo code encoding method according to an embodiment of the present invention for achieving the above object comprises the steps of: generating a systematic sequence by inserting temporary bits in the original sequence; Encoding the structured sequence by a first encoder to generate a first parity sequence; Interleaving the structured sequence; Encoding the interleaved sequence by a second encoder to generate a second parity sequence; And setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index. It includes.

In this case, in the structured sequence generation step, the temporary bit may be inserted into an original sequence having a length corresponding to a difference between a length of the original sequence and a length of a selected basic interleaver among a preset basic interleaver set. The basic interleaver set is set to have a multiple length of the variation vector period of the ARP, and the selected basic interleaver may have a minimum multiple length that is greater than or equal to the length of the original sequence among multiples of the variation vector period.

In addition, it is preferable that both the encoding bit and the puncturing index are known to both the encoding end and the decoding end.

On the other hand, the turbo code decoding method according to another embodiment of the present invention, the step of inserting temporary bits (temporary bits) in the original sequence to generate a structured sequence (systematic bits); Encoding the structured sequence by a first encoder to generate a first parity sequence; Interleaving the structured sequence; Encoding the interleaved sequence by a second encoder to generate a second parity sequence; And setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index. A method of receiving and decoding a transmitting side signal generated by the receiving side through a channel, the method comprising: each of the structured sequence corresponding signal, the first parity sequence corresponding signal and the second parity bit corresponding signal of the received signal; Inserting a supplementary signal into the puncturing index; And decoding the structured sequence correspondence signal, the first parity sequence correspondence signal and the second parity bit correspondence signal into which the supplementary signal is inserted, respectively.

In this case, in the supplementary signal insertion step, the supplementary signal inserted into the puncturing index of the structured sequence corresponding signal has a sign determined according to a modulation method of the temporary bit and the temporary bit and has an absolute value greater than 1. In the inserting of the supplementary signal, the supplementary signal inserted into the puncturing index of the first parity sequence corresponding signal and the second parity bit corresponding signal may be zero.

The temporary bit may be inserted into an original sequence having a length corresponding to a difference between a length of the original sequence and a length of a selected basic interleaver among a preset basic interleaver set. The decoding step may include an interleaving step by an interleaver of the same length as the selected basic interleaver.

In addition, the preset basic interleaver set is set to have a multiple length of a variation vector period of ARP, and the selected basic interleaver may have a minimum multiple length that is greater than or equal to the length of the original sequence among multiples of the variation vector period. The preset basic interleaver set may be set to have a multiple length of the number of windows used for parallel decoding, and the selected basic interleaver length may have a minimum multiple length that is greater than or equal to the length of the original sequence among multiples of the number of windows.

On the other hand, the turbo code encoder according to another embodiment of the present invention, the temporary bit inserting unit for inserting the temporary bits (temporary bits) in the original sequence to generate a structured sequence (systematic sequence); A first encoder for encoding the structured sequence to generate a first parity sequence; An interleaver for interleaving the structured sequence; A second encoder for encoding the interleaved sequence to generate a second parity sequence; And setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index. It includes a temporary bit removing unit.

Finally, a turbo code decoder according to another embodiment of the present invention includes: a temporary bit inserter for inserting temporary bits into an original sequence to generate a systematic sequence; A first encoder for encoding the structured sequence to generate a first parity sequence; An interleaver for interleaving the structured sequence; A second encoder for encoding the interleaved sequence to generate a second parity sequence; And setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index. A turbo code decoder for receiving and decoding a transmitting side signal generated by a turbo code encoder including a temporary bit removing unit through a channel, wherein the structured sequence corresponding signal of the received signal and the first parity sequence corresponding A supplementary signal insertion unit inserting a supplementary signal into the puncturing index of each of the signal and the second parity bit corresponding signal; And a decoder for decoding the structured sequence correspondence signal, the first parity sequence correspondence signal and the second parity bit correspondence signal into which the supplementary signal is inserted.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced. The following detailed description includes specific details in order to provide a thorough understanding of the present invention. However, those skilled in the art will appreciate that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are omitted or shown in block diagram form around the core functions of each structure and device in order to avoid obscuring the concepts of the present invention. In addition, the same components will be described with the same reference numerals throughout the present specification.

One embodiment of the present invention utilizes the concept of "temporary bits" to solve the length limitation problem of the interleaver used in the turbo encoder and decoder as described above, while maintaining the efficiency of the system and continuously adjusting the length of the input sequence. It provides a turbo code encoding of a long length, and provides a method for easily decoding a received signal. Here, the "temporary bit" is free to select '0' or '1', but should be information known to both the transmitting and receiving sides, that is, the encoding and decoding stages.

In addition, one preferred embodiment of the present invention utilizes the concept of a “Basic Interleaver” to enable continuous length ARP interleaving and parallel decoding. The basic interleaver herein is an interleaver having a preset length to implement an interleaver having a required length. In general, it is preferable that a basic interleaver set having various lengths is preset as necessary.

3 illustrates a structure for encoding a turbo code having a continuous length using temporary bits according to an embodiment of the present invention.

According to one embodiment of the invention, a temporary bit inserter 301 inserts a temporary bit into the original sequence X to generate a systematic sequence of a length that can be encoded by the turbo encoder 302. This structured sequence is then generated by the encoding through the first configuration encoder 302a, the first parity sequence Y1, interleaved by the interleaver 302b, and then encoded by the second configuration encoder 302c. This generates the second parity sequence Y2. However, the temporary bits inserted into the structured sequence and the first and second parity sequences (Y1 and Y2) generated as described above may be removed by the temporary bit removing unit 303 as shown in FIG. 3 after encoding is completed. By removing the inserted temporary bits and transmitting them through the channel, it is possible to prevent further reduction of the frequency efficiency of the system.

In addition, the interleaver 302b of the turbo encoder 302 is preferably a basic interleaver selected to have a specific length among a preset set of basic interleavers of various lengths. For example, when performing ARP interleaving in an encoder according to an embodiment of the present invention, the preset basic interleaver set as described above has the length of the interleaver in the ARP being only a multiple of the variation vector period of the ARP as described below. Considering that it can only be performed, it can be set to have a multiple length of the ARP variation vector period. In addition, the basic interleaver set may be preset to have a multiple length of the number of windows included in each component decoder of the decoding stage in order to use a contention-free interleaver designed so that a memory bank contention problem does not occur. Application to parallel decoding without memory bank contention is described in more detail below.

Referring to a specific operation according to an embodiment of the present invention shown in FIG. 3, first, the length of the interleaver 302b in the temporary bit inserting unit 301 in the original length X of the K length, specifically the interleaver set in advance Temporary bits (K'-K) corresponding to the difference between the length K 'of the interleaver having the selected length among the set and the length K of the original sequence are inserted. For example, if an input sequence of length K is X = (b ₀ , b ₁ , ...., b _{k -1} ), the structured sequence of length K 'with K'-K temporary bits inserted is For example, it can be expressed as X '= (b ₀ ', b ₁ ', ..., b _{k -1} ', b _k ', ..., b _{k' -1} '). Here, the position at which the temporary bits are inserted may be any index as long as both the encoding side and the decoding side know it. For example, K'-K temporary bits may be inserted at K or more indexes. Temporary bits may be inserted into K'-K indexes randomly selected from '-1'.

In this way, the input sequence into which the temporary bits are inserted is output as a structured sequence, and is encoded by the first configuration encoder 302a to generate the first parity sequence Y1 ', and interleaved by the interleaver 302b, for example. For example, ARP interleaving generates an interleaved sequence O (i.e., O = (o ₀ , o ₁ , ..., o _{k ' -1} )). Here, the index mapping relationship by the interleaver may be i = π (j), that is, _{bπ (j) = i} = o _j when the index of X 'is i and the index of the interleaved sequence O' is j. have. Then, the interleaved length K ', sequence O, is encoded by second configuration encoder 302c to produce a second parity sequence Y2'.

Each of X ', Y1', and Y2 'having a length of K' generated through the above-described process is inserted by the temporary bit removing unit 303 for adjusting the length according to the embodiment of the present invention. Puncture the incremented bits. For example, when K'-K indexes are inserted in a portion where the temporary bit has an index K or more in the original sequence X, a portion whose index K or more is included in the structured sequence X 'and the first parity sequence Y1 is determined. Set to the puncturing index, and output only the indexes other than this to the sequence X and Y1 to be transmitted. In the second parity sequence Y2 ', the index satisfying K≤i≤K'-1 among the indices of the structured sequence (X'). J index corresponding to (i.e. each j corresponding to the relationship j = π (i) for each i satisfying K≤i≤K'-1) is set as a puncturing index, This can be performed by outputting only the index to the sequence Y2 to be transmitted.

In this way, the structured sequence X ', the first parity sequence Y1', and the second parity sequence Y2 'in which the temporary bits are inserted are not transmitted as they are, and information other than the bits due to the temporary bit insertion is transmitted from them. This can further increase the frequency efficiency in the communication system. For example, in the case of transmitting sequences in which K'-K temporary bits are inserted as it is, if the coding rate of the encoding stage is 1/3, the amount of information to be transmitted is 3 * (K ') compared to the amount of information required. -K) information is further increased, and this increase in unnecessary information may require additional frequency resources.

Meanwhile, a method of efficiently decoding the transmitted encoding sequence will be described below.

4 is a diagram illustrating a structure for receiving and decoding a signal having a continuous length encoded by the structure shown in FIG. 3.

X, Y1, and Y2 transmitted through the process as described above in FIG. 3 are received at the receiver through a channel. Accordingly, the received signal is included in the received signal corresponding to the structured sequence X from which the temporary bits have been removed (hereinafter referred to as the "structured sequence correspondence signal R ^X ") and the first parity sequence Y1 from which the temporary bits have been removed. A corresponding received signal (hereinafter referred to as "first parity sequence correspondence signal R ^Y1 ") and a received signal corresponding to second parity sequence Y2 (hereinafter referred to as "second parity bit correspondence signal R ^Y2 ) ""). However, as described above, R ^X , R ^Y1 , and R ^Y2 constituting the received signal have a problem that they cannot be decoded due to the limitation of the length of the interleaver. Therefore, in one embodiment of the present invention, the supplementary signal corresponding to the temporary bit inserted in the encoding stage by the supplementary signal adding unit 401 is added to the received signal to adjust the length back to K '. As a result, decoding can be performed through the turbo decoder 402 using a basic interleaver having a length K 'as in the encoding stage. The above-described base interleaver length K 'may be a base interleaver having a length of K or more among preset basic interleaver sets set to have multiples of the variation vector period in ARP interleaving according to the utilization thereof, and / or parallel decoding The basic interleaver whose length is greater than or equal to K may be selected from among a set of basic interleavers preset to have multiples of the number of windows included in the component decoder used for. This will be described in detail below.

Meanwhile, the supplementary signal added by the supplementary signal adding unit 401 is as follows.

In the decoding method according to the present invention, since the decoder knows the temporary bit information inserted at the encoding side and the puncturing index from which the temporary bit has been removed, the depuncturing, that is, the supplementary signal insertion method, is performed according to the method. This is done by reinserting the supplemental signal corresponding to the value into the corresponding puncturing position.

Specifically, for example, when a temporary bit is inserted into a portion having an index K or more in the input sequence X in the encoding stage, since the puncturing index here is K ≦ i, the structured sequence corresponding signal R ^X = (R ₁ ^x , R ₂ ^x , ... R _{K -1} ^x )) part where index i is less than K is used as R ^x value as the result of depuncture R ^{x '} , and the complementary signal for the index i is greater than or equal to K Insert

Where, n _i is the gateuna │n _i │ at every index, an integer in which the code is determined by the modulation method and the temporary bit was inserted for each index, preferably has a size relative to a value of ni, at least It is preferable to set it to a number larger than one. In this way, inserting the supplementary signal by multiplying the average value of the received structured sequence correspondence signal R ^x by n _i may remove all possible metrics in the decoding step while already knowing information about the temporary bits inserted by the transmitter. Rather than take into account, it is to improve the decoding performance by limiting the branch metric estimateable in the decoding step.

On the other hand, in the puncturing indexes of the first parity sequence correspondence signal R ^Y1 and the second parity sequence correspondence signal R ^Y2 , as described above, since the receiver already has information on the temporary bits, it is estimated when decoding. Since extra parity bit information is unnecessary, '0' is inserted. Accordingly, as use of the first parity sequence corresponding signal index i is R ^Y1 value index is less than the K of (R ^Y1) in the example described above, and the i is inserted "0" into the index, R ^Y1 or more K R ^{Y1 '} Create In addition, the value of R ^Y2 is used as the index j corresponding to i of 0 ≤ i ≤ K-1 of the index j of the second parity sequence correspondence signal R ^Y2 , and '0 is used for the index j corresponding to i equal to or greater than K. Insert ^', to create R ^Y2' .

Therefore, according to one embodiment of the present invention as shown in FIG. 4, the signals input to the decoder 402 are R ^{X '} , R ^Y1' and R ^{Y2 '} each having a length K'. Accordingly, the decoder 402 uses the basic interleaver of length K 'as the interleaver 402b, and adds the first component decoder 402a and the second component decoder 402c through the corresponding deinterleaver 402d. Decoding may be performed by repeating information operation and storage.

Hereinafter, a turbo code encoding and decoding method according to an embodiment of the present invention described with reference to FIGS. 3 and 4 will be described with more specific examples.

First, the length K of the input original sequence is 14 and the required interleaver length K 'is 16. Accordingly, i = 14, 15 is selected as an index into which the temporary bits are inserted in the encoding stage, and' 0 'is selected as the temporary bit. Assume the case of insertion.

The input original sequence is called X = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13} for convenience and a structured sequence X with a temporary bit inserted '= {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}. That is, the number written on each sequence represents the index of the original sequence X or structured sequence X 'with a temporary bit inserted therein.

The interleaver receiving the above-described structured sequence X 'performs interleaving, and accordingly, the interleaved sequence O = {0, 4, 2, 6, 8, 7, 11, 9, 12, 14, 15, 1, 3, 5, 10}. Through this, it is possible to know the index mapping relationship according to interleaving.

On the other hand, in the encoding stage, the structured sequence X 'into which the temporary bit is inserted, the first parity sequence Y1' encoded by the first constituent encoder, and the O interleaved X 'are encoded by the second constituent encoder. In the second parity sequence Y2 ', only the remaining indexes, except for the puncturing index due to temporary bit insertion, are output as X and Y1 and transmitted through the channel. That is, the bits corresponding to 14 and 15 of X 'and Y1' are not output. In addition, in Y2 ', only the remaining indexes are output as Y2 except indexes 10 and 11 corresponding to indexes 14 and 15 of the structured sequence X'.

As described above, except for the information of the puncturing index, the outputted lengths X, Y1, and Y2 are received by the receiver through the channel.

를 나타낸다.The receiving end inserts the supplementary signal so that each of the signals having a length of 14 has a length of 16 again, with the received signals as R ^X , R ^Y1 , and R ^Y2 corresponding to X, Y1, and Y2, respectively. In this case, R ^X inserts ni · R R ^X _av in case the index i is greater than or equal to smaller than 14, as used in R ^{X 'of} the received R ^X, and i is 14. Where R _av is

Indicates.

In addition, since R ^Y1 also has the same puncturing index as R ^X , when i is less than 14, R ^Y1 is used as it is, and when i is 14 or more, R ^Y1 is inserted to obtain R ^Y1 . In addition, R ^Y2 is because the according to an index mapping relationship according to the above-described interleaving, j = 10, 11 correspond to the puncturing index, j = 10, inserting "0" into the 11, and the other index has the R ^Y2 value as R ^Y2 Used for ^'

Through this depuncturing, the decoding stage can decode a received signal having a length of 16.

Meanwhile, the following describes a method of implementing an ARP interleaver having a continuous length by using the turbo code encoding and / or turbo code decoding method according to an embodiment of the present invention as described above together with the basic interleaver concept.

ARP adds a fluctuation vector to the RP to avoid certain sequences, such as RTZ sequences with a weight of 6 or 9, and distorts them during writing and reading. If j is represented by the following index mapping relationship.

Here, K is the size of the interleaver, P is an arbitrary integer that is small with K and corresponds to the number of columns in the matrix in which writing is in the row direction and reading is in the column direction in RP. In addition, Q (j) represents a variation vector, and specifically, it may be expressed as follows.

Here, C denotes a distortion period (also a period of the variation vector Q), and A (j) and B (j) are cycle functions having C as a cycle, which is 20% or less of P and K / P. It is also possible to select Q (0) = 0, and this ARP may be defined by 2 (C-1) integers and P defining A (j) and B (j).

As such, the variation vector Q used for ARP has a period C, and therefore, in order to perform ARP interleaving, it must have a multiple length of C.

Accordingly, in one embodiment of the present invention, in the process of performing such ARP, the basic interleaver set is set in advance as a multiple of the variation vector period of the ARP, and the minimum multiple length (K) of the variation vector period that is equal to or greater than the length K of the input sequence. By selecting a basic interleaver having '), interleaving and encoding by inserting the above-described temporary bits by K'-K can encode a turbo code having a continuous length.

On the other hand, even when receiving a signal from which the temporary bit inserted after encoding as described above, the receiving end can adjust the length of the received signal to a multiple of the ARP variation vector by performing the de-punching process as described above. ARP interleaving and ARP deinterleaving may be performed to perform decoding.

Meanwhile, in the following, the turbo code encoding and / or turbo code decoding method according to an embodiment of the present invention as described above can be used in parallel decoding with a basic length of interleaver and without memory bank contention problem. A method of performing decoding will be described.

In the parallel decoding of the TC, each window has a different component decoder different from the bitwise received value received on the channel in order to calculate the three metrics of the forward metric, the reverse metric, and the branch metric as described above. Use the computed extrinsic information. Received values and collateral information are stored in a fixed memory space in order (bitwise), and each component decoder reads the values needed to compute the metric from memory and writes the collateral information calculated by the configuration decoder back into memory. do.

At this time, each window should be connected to one memory bank at a time for parallel decoding. If a plurality of windows are connected to one memory bank, a memory bank contention problem occurs. In general, such a memory bank contention problem does not occur in the storage of the secondary information calculation value of the first component decode in the decoding stage, but an index interleaving the secondary information stored in a plurality of memory banks instead of the stored index. As a result, contention may occur when each window connects to the memory bank.

The memory bank connection contention problem as described above can be solved using a well designed interleaver, and an interleaver designed such that the memory bank connection contention problem does not occur is referred to as a "contention-free interleaver".

General contention free interleaver has the following properties.

Here, j ₁ and j ₂ have different read positions in the index of the entire K length, but mean indexes read in the same unit time in different windows of the component decoder, and can be expressed as follows.

는 제 2 구성 디코더에서 계산하는 j 번째 부대 정보를 계산하기 위하여 접속해야 하는 메모리 뱅크의 주소를 나타내는 것으로 볼 수 있다. 따라서, 상기 수학식 4를 만족하는 인터리버를 설계할 경우 서로 다른 윈도우가 동일 시간에 서로 다른 메모리 뱅크를 접속하게 된다. 이때, 메모리 뱅크 내에서 저장된 부대 정보가 몇 번째인지는 중요하지 않다. 단 전체 부대 정보가 각각 한 번씩 접속하게 되면 된다.In Equation (1)

Can be regarded as representing the address of the memory bank to which the second component decoder should access in order to calculate the j th sub information. Therefore, when designing an interleaver that satisfies Equation 4, different windows connect different memory banks at the same time. At this time, it is not important how many auxiliary information is stored in the memory bank. However, all unit information is accessed once each.

However, the contention-free interleaver has a limitation that its length must have a multiple of the number of windows included in each component decoder in order to satisfy the conditions described above.

Accordingly, in one embodiment of the present invention, in the process of performing parallel decoding using such a contention-free interleaver, the basic interleaver set is preset to have a multiple of the number of windows included in each component decoder, and the length of the input sequence ( It is possible to encode a turbo code having a continuous length by selecting a basic interleaver having a minimum multiple length K 'of the number of windows greater than or equal to K) and interleaving and encoding by inserting the above-described temporary bits by K'-K. have.

On the other hand, even when receiving the signal from which the temporary bit inserted after encoding as described above, the receiving end can adjust the length of the received signal to a multiple of the number of windows used for parallel decoding by performing the de-punching process as described above again. Through this, decoding can be performed by performing interleaving and deinterleaving without contention.

The detailed description of the preferred embodiments of the invention disclosed as described above is provided to enable any person skilled in the art to make and practice the invention. Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can. Accordingly, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

According to one embodiment of the present invention as described above, in order to provide an interleaver with a continuous length, interleaving and turbo code encoding are performed using the temporary bit concept, and the decoding stage is more easily performed using the characteristics of the temporary bit. A method of decoding a received signal is provided.

In addition, by using the basic interleaver concept set to perform interleaving for parallel decoding without memory bank contention and ARP interleaving to avoid a specific RTZ sequence using the encoding and decoding method using temporary bits as described above, Enable ARP interleaving and / or continuous length parallel decoding.

Claims (12)

Inserting temporary bits into an original sequence to generate a systematic sequence; Encoding the structured sequence by a first encoder to generate a first parity sequence; Interleaving the structured sequence; Encoding the interleaved sequence by a second encoder to generate a second parity sequence; And Setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index; Turbo code encoding method comprising. The method of claim 1, And in the generating a structured sequence, inserting the temporary bits into an original sequence having a length corresponding to a difference between the length of the original sequence and the length of a selected basic interleaver among a preset basic interleaver set. The method of claim 2, The preset basic interleaver set is set to have a multiple length of the variation vector period of ARP, And the selected basic interleaver has a minimum multiple length greater than or equal to the length of the original sequence among multiples of the variation vector period. 4. The method according to any one of claims 1 to 3, And said temporary bit and said puncturing index are known to both encoding and decoding stages. Inserting temporary bits into an original sequence to generate systematic bits; Encoding the structured sequence by a first encoder to generate a first parity sequence; Interleaving the structured sequence; Encoding the interleaved sequence by a second encoder to generate a second parity sequence; And Setting an index corresponding to a bit added due to the temporary bit insertion in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and outputting an index except the puncturing index. In the method for receiving and decoding the transmission side signal generated by the receiving side through a channel, Inserting a supplementary signal into the puncturing index of each of the structured sequence corresponding signal, the first parity sequence corresponding signal and the second parity bit corresponding signal of the received signal; And And decoding the structured sequence correspondence signal, the first parity sequence correspondence signal and the second parity bit correspondence signal into which the supplementary signal is inserted, respectively. 6. The method of claim 5, In the supplementary signal inserting step, the supplementary signal inserted into the puncturing index of the structured sequence corresponding signal is a signal whose sign is determined according to a modulation method of the temporary bit and the temporary bit and whose absolute value is greater than one. Turbo code decoding method. The method according to claim 5 or 6, And the supplementary signal to be inserted into the puncturing index of the first parity sequence corresponding signal and the second parity bit corresponding signal is 0 in the supplementary signal insertion step. 6. The method of claim 5, In the step of generating a structured sequence of the transmitting side, the temporary bit is inserted into an original sequence having a length corresponding to a difference between the length of the original sequence and the length of a basic interleaver selected from a set of preset basic interleavers, And the decoding step of the receiving side comprises an interleaving step by an interleaver of the same length as the selected basic interleaver. 9. The method of claim 8, The preset basic interleaver set is set to have a multiple length of the variation vector period of ARP, Wherein the selected basic interleaver has a minimum multiple length greater than the length of the original sequence of multiples of the variation vector period. 9. The method of claim 8, The preset basic interleaver set is set to have a multiple length of the number of windows used for parallel decoding. And the selected basic interleaver length has a minimum multiple length greater than or equal to the length of the original sequence among multiples of the window number. A temporary bit inserter for inserting temporary bits into an original sequence to generate a structured sequence; A first encoder for encoding the structured sequence to generate a first parity sequence; An interleaver for interleaving the structured sequence; A second encoder for encoding the interleaved sequence to generate a second parity sequence; And Temporary to set an index corresponding to a bit added due to the insertion of the temporary bit in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and output an index except the puncturing index. Turbo code encoder comprising a bit remover. A temporary bit inserter for inserting temporary bits into an original sequence to generate a structured sequence; A first encoder for encoding the structured sequence to generate a first parity sequence; An interleaver for interleaving the structured sequence; A second encoder for encoding the interleaved sequence to generate a second parity sequence; And Temporary to set an index corresponding to a bit added due to the insertion of the temporary bit in the structured sequence, the first parity sequence, and the second parity sequence as a puncturing index, and output an index except the puncturing index. A turbo code decoder for receiving and decoding a transmitting side signal generated by a turbo code encoder including a bit removing unit through a channel, A supplementary signal insertion unit inserting a supplementary signal into the puncturing index of each of the structured sequence corresponding signal, the first parity sequence corresponding signal, and the second parity bit corresponding signal of the received signal; And And a decoder for decoding the structured sequence correspondence signal, the first parity sequence correspondence signal and the second parity bit correspondence signal into which the supplementary signal is inserted.

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