KR100297739B1 - Turbo codes with multiple tails and their encoding / decoding methods and encoders / decoders using them - Google Patents

Abstract

The present invention relates to a multi-tailed turbo code, a method of encoding / decoding thereof, and an encoder / decoder using the same. The multi-tail turbo code encoder of the present invention encodes by adding a multi-tail in each encoder. That is, while the conventional turbo code has only one tail, the turbo code of the present invention has a multi-tail having a tail added to each block after dividing an input into at least one block. The encoder / decoder of the multi-tail turbo code is implemented by changing only the operation time of each block of the encoder / decoder of the existing turbo code. Multi-tailed turbocodes perform better because there is more information available for decoding, but they have more tails than conventional turbocodes, requiring more transmission power and more bandwidth. However, when the input length is large, the difference between the transmission power and the bandwidth of a multi-tail turbo cord and a conventional turbo code is negligible. Since the MAP decoder for decoding the existing turbo code is determined by the size of the input symbol and the number of memory of the component code, a different MAP decoder is required for each service. However, in the case of a multi-tail turbo code, all services are processed regardless of the input length by dividing the input data into at least one block with one MAP decoder, and in particular, the multi-tail turbo code is capable of parallel decoding. Using the MAP decoder can solve the existing serious decoding delay problem.

Description

Turbocode with Multiple Tails and Its Encoding / Decoding Method and Encoder / Decoder Using the Same

1 is a block diagram of an encoder of a turbo code having multiple tails according to the present invention.

FIG. 2 is a detailed block diagram of the constituent encoder of FIG. 1.

3 is a detailed block diagram of the tail generator of FIG. 1.

4 is a block diagram of a turbo code decoder having multiple tails according to the present invention.

5 is a conceptual diagram illustrating a general single tail decoding algorithm.

6 is a conceptual diagram for explaining a multi-tail decoding algorithm of the present invention.

Explanation of symbols on the main parts of the drawings

10, 40 ... first and second timing controllers, 11, 25 ... interleaver,

12, 15, 18 ... 1st to 3rd selectors, 13, 16 ... 1st and 2nd component encoders,

14, 17 ... first and second tail generator, 19 ... buffer,

20 ... address calculator, 21, 30 ... first and second delayers,

22, 23, 26, 27 ... fourth to seventh selectors, 24, 28 ... first and second MAP decoders,

29 deinterleaver, 31 discriminator

The present invention relates to a turbo code having a multi-tail, an encoding / decoding method thereof, and an encoder / decoder using the same, and more particularly, by dividing an input into at least one or more blocks, and then changing only the operating time of the encoder and the decoder. The present invention relates to a turbo code having multiple tails, a method of encoding / decoding thereof, and an encoder / decoder using the same, in which a tail is added to each block.

Turbocode is a kind of nickname first used by the developer (Berrou). The first official names appeared were called parallel convolutional code, multi-component code or parallel chain tail bit convolutional code. The encoding characteristics of the turbo code are well illustrated in the drawings except for the timing controller of FIG. 1. That is, the first encoder 100 and the second encoder 110 are connected in parallel with respect to the input, the input is encoded in the first encoder 100, the same input is interleaved in the interleaver 11, and then the second encoder 110 is connected. Is encoded. This was called parallel chain code. For reference, the old (serial) chain code is serially connected to the first encoder and the second encoder to the input. After the input is encoded at the first encoder, the output of the first encoder is interleaved and then encoded at the second encoder. In general, in serial chain codes, one uses a convolutional code and one block code, while in a parallel chain code, all components are convolutional codes. The decoding characteristic of the turbo code is that iterative decoding is performed. In other words, the turbo code decodes again using the decoded result. To do this, the decoder must be able to output a soft output. Turbocode uses either a maximum a posteriori (MAP) algorithm or a soft output viterbi algorithm (SOVA) for decoding. The new code, which includes many of these features, outperformed any code that existed before and was called Turbocode. The current turbocode does not refer to only those described above, but those employing only some of the characteristics of the turbocode are also called turbocodes in a broad sense. Prior arts using such turbo codes, i.e., turbo codes, are described in US Pat. No. 5,446,747 (Error correction coding method with at least two systematic convolutional codings in parallel, corresponding iterative decoding method, decoding module and decoder), 5,729,560 (Method and coding). means for protected transmission of data on the basis of multi-component coding) and 5,721,745 (Parallel concatenated tail-biting convolutional code and decoder), and these prior art coders and decoders shown in FIGS. Similar blocks are disclosed except for timing controllers in the block of.

These turbo codes are recently developed channel error correcting codes, and since they are very superior in performance to existing error correcting codes, they are expected to be adopted as error correcting codes in many communication systems in the future. However, the conventional turbo code has a problem in that it is delayed in decoding, and when decoding the conventional turbo code, it is dependent on the size of the input symbol and the number of memory of the component code.

[Technical problem to be achieved]

The technical problem to be achieved by the present invention is to provide.

An object of the present invention is to provide an encoding method for generating a turbo code having multiple tails by adding a tail to each block of input data divided into at least one block.

Another object of the present invention is to provide a decoding method for recovering a turbo code having a multi-tail encoded in the multi-tail turbo code encoder.

Another object of the present invention is to provide an encoder for generating a turbo code having a multi-tail.

Another object of the present invention is to provide a decoder for recovering a turbo code having a multi-tail encoded in the multi-tail turbo code encoder.

[Configuration and Function of Invention]

In order to achieve the above technical problem, at least one encoder generates a turbo code having a multi-tail for dividing input data into at least one block according to a timing control signal and then adding a tail to each block to encode the same. An encoding method is provided.

Another technical problem to be solved by the present invention is to divide the input data input to at least one encoder into at least one block according to the first timing control signals and to have a multi-tail generated by adding one tail to each block. A method of decoding a turbo code, the method comprising: selectively decoding input data and tail information according to a second timing control signal; And selectively decoding a value obtained by interleaving the decoded information and next sequential tail information, and deinterleaving the last decoded information to restore a turbo code having a multi-tail.

Another technical problem to be solved by the present invention is to divide input data into at least one block according to a timing control signal, add tail information to each block, encode the same, and divide the input data into at least one block, and then for each block. At least one encoder corresponding to the number of blocks for sequentially encoding and adding respective tail information to each interleaved input data; Selection means for selectively receiving the input data, the tail information and outputs of the at least one encoder; And a timing controller for supplying a timing signal to the at least one encoder and the selecting means.

Another technical problem to be solved by the present invention is generated by dividing the input data input to at least one encoder into at least one block according to the first timing control signals of the first timing controller and adding one tail to each block. A decoder for decoding a turbo code having multiple tails, wherein the decoder receives input data and tail information according to second timing control signals and selectively decodes the interleaved decoding data. At least one decoder to decode into; Deinterleaver / determination means for deinterleaving and discriminating the decoded input data and outputting recovered data; And a second timing controller configured to supply the second timing control signals to the at least one decoder and the deinterleaver / identification means.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows an encoder of a turbo code having a multi-tail according to an embodiment of the present invention. In the present embodiment, an encoder for dividing the input data into two blocks will be described. However, the present invention has two or more blocks. The encoder of the turbo code having multiple tails in the case of two blocks or more will be described.

The encoder of this embodiment includes a first encoder (encoder) 100, a first interleaver 11, a second encoder 110, a first timing controller 10, a third selector 18, a buffer 19, and An address calculator 20 is provided.

Input data of length N bits is sent to the first selector 12, the third selector 18, and the first interleaver 11. In the first encoder 100, the first selector 12 has input data and an output of the first tail generator 14 as inputs. The first selector 12 outputs the input data from time 0 to N-1 and then outputs the output of the first tail generator 14 from time N to N + M-1 according to the timing control signal C2. do. M is the number of memories that the first component encoder 13 has. The first component encoder 13 sequentially receives and encodes the bits output from the first selector 12 according to the timing control signal C3 and sequentially outputs N + M bits. The output of the first component encoder 13 is sent to the third selector 18. A method of encoding by the first component encoder 13 will be described in detail later with reference to FIG. 2. The first tail generator 14 generates a tail by inputting values of memories existing in the first component encoder 13 from time N to N + M-1 according to the timing control signal C4. The M bit output of the first tail generator 14 is sent to the first selector 12 and the third selector 18. A method of generating the tail by the first tail generator 14 will be described in detail later with reference to FIG. 3.

Referring to the operation of the second encoder 110, the interleaver 11 receives N bits of input data according to the timing control signal C1, and then reverses the order according to a predetermined interleaving rule to generate new N bits of data. The role of the second selector 15, the second component encoder 16, and the second tail generator 17 uses the output of the interleaver 11 instead of the input data and uses the timing control signals C5, C6, C7. Are identical to those of the first selector 12, the first component encoder 13, and the first tail generator 14. The second selector 15, the second component encoder 16, and the second tail generator 17 operate from time N + M to 2 (N + M) −1.

The third selector 18 has input data, outputs of the first component encoder 13, the first tail generator 14, the second component encoder 16, and the second tail generator 17 as inputs. The third selector 18 sequentially selects them according to the timing control signal C8 and sends them to the buffer 19.

The buffer 19 is composed of 3N + 4M memories. The output of the third selector 18 is stored in the memory of the buffer 19 indicated by the address calculated by the address calculator 20 in accordance with the timing control signal C9.

In this way, when the encoding into the turbo code is completed for the N bits of input data, the 3N + 4M bits stored in the buffer 19 are transferred to the next step. The buffer 19 and the address calculator 20 may be omitted and the output of the third selector 18 may be passed directly to the next step.

FIG. 2 is a block diagram of the constituent encoders 13 and 16 having M memories and whose generated polynomials G ¹ (x) and G ² (x) are defined as Equations 1 and 2 below.

[Equation 1]

[Equation 2]

Where g ¹ _i and g ² _i have the value 0 or 1.

That is, when G ¹ (x) = x ³ + x + 1, it is expressed as 1011 ₂ = 13.

In Figure 2 Means XOR Means AND. S ₀ to S _M-1 are memories that can store one bit. At time 0, the initial values of S ₀ to S _M-1 are all 0, and after encoding all the tails, the final values of S ₀ to S _M-1 are all 0.

3 is a block diagram of a tail generator in which the number of memories is M. FIG. here Means XOR Means AND. And G ¹ (x) is the same as G ¹ (x) of the encoder configuration. The input of the tail generator is the values of the memory S ₀ to S _M-1 of the component encoder. When the output of the tail generator is used as the input of the component encoder, after encoding, the value of S ₀ , which is the first memory of the component encoder, becomes zero. Therefore, operating the tail generator as many times as M can zero all memory in the component encoder.

Hereinafter, when N is the number of input bits and M is the number of memories of the constituent encoder, each block of each time zone according to the control signals C1-C10 of the first timing controller 10 during single tail turbo code encoding is performed. The operations are shown as in Table 1 below.

TABLE 1

As can be seen from Table 1, the multi-tail turbo code encoder according to the first embodiment of the present invention has a first tail and a first tail in one input block at a time period from 0 to 2N + 2M in the third selector 18. Two tails of two tails are added to an input bit and encoded.

Since the encoder of the second embodiment of the present invention divides the input bit into two blocks and then adds a tail bit, four tail bits are actually added. This is shown in Table 2. In Table 2, the number of blocks is 2, N is the number of input bits, M is the number of memories of the component encoder, the first block is N0, and the second block is N1. Here, N0 + N1 = N.

TABLE 2

As can be seen from Table 2, the multi-tail turbo code encoder has two first tails and two second tails in each subblock of the input block divided in the 0 to 2N + 4M time periods in the third selector 18. The tail is added to the input bits and encoded.

4 is a block diagram of a decoder of a turbo code according to the present invention. The inputs of the decoder of the turbo code are N input symbols corresponding to the input of the encoder of the turbo code and the N first parity symbols corresponding to the output of the first component encoder 13 and the first component encoder 13. M first tail symbols corresponding to the tail bits, M first tail parity symbols corresponding to the output of the tail bits of the first component encoder 13, and corresponding to the outputs of the second component encoder 16. N second parity symbols, M second tail symbols corresponding to the tail bits of the second component encoder 16, and M second tails corresponding to the outputs of the tail bits of the second component encoder 16. It is composed of parity symbols.

The input symbol and the first tail symbol are sent to a fourth selector 22. The fourth selector 22 outputs an input symbol from time 0 to N-1 and a first tail symbol from time N to N + M-1 according to the timing control signal T2 of the second timing controller 40. do. The first parity symbol and the first tail parit symbol are sent to a fifth selector 23. The fifth selector 23 outputs the first tail symbol from time 0 to N-1 and the first tail parity from time N to N + M-1 according to the timing control signal T3 of the second timing controller 40. Print a symbol. The output of the second interleaver 25 and the second tail symbol are sent to a sixth selector 26. The sixth selector 26 outputs the output of the interleaver 25 from time N + M + Δ to 2N + M-1 + Δ according to the timing control signal T6 of the second timing controller 40 and at time 2N + M +. A second tail symbol is output from? To 2 (N + M) -1 + △. Δ is a time required for the first MAP decoder (decoder) 24 to complete decoding in accordance with the timing control signal T4, which is equal to the time delayed by the first delayer 21. The second parity symbol and the second tail parrit symbol are sent to the seventh selector 27. The seventh selector 27 outputs the second tail symbol from the time N + M + △ to 2N + M-1 + △ by the timing control signal T7 of the second timing controller 40 and starts from the time 2N + M + △. Up to 2 (N + M) -1 + Δ, a second tail parity symbol is output.

The N current additional information is set equal to the next additional information calculated in the previous decoding step. In case of the first decoding, all current additional information is set to 0.

The first MAP decoder 24 obtains the sum of the output of the fourth selector 22 and the current additional information from the adder 32, has the addition result as an input for the information bits, and outputs the output of the second selector 23. Has as input to the parity bit. The first MAP decoder 24 decodes a portion corresponding to the first component encoder of the encoder of the turbo code. The operation of the first MAP decoder 24 will be described in detail later.

The first delayer 21 outputs the current additional information after the first MAP decoder 24 completes the decoding completely by the timing control signal T1 of the second timing controller 40. The difference between the output of the first MAP decoder 24 and the output of the first delayer 21 is obtained by the subtractor 33 and the result is sent to the second interleaver 25. The second interleaver 25 is the same interleaver as the first interleaver used in the encoder of the turbo code. The second interleaver 25 performs interleaving according to the timing control signal T5. The second MAP decoder 28 has the output of the sixth selector 26 as an input for the information bits and the output of the seventh selector 27 as an input for the parity bits. The operating principle of the second MAP decoder 28 is the same as the operating principle of the first MAP decoder 24. However, the second MAP decoder 28 uses the timing control signal T8. Since only the operation time of the second MAP decoder 28 and the operation time of the first MAP decoder 24 are different, the second MAP decoder 28 may reuse the first MAP decoder 24 without separately implementing it. The output of the second MAP decoder 28 is deinterleaved by the deinterleaver 29. The deinterleaver 29 serves to make the data in the original order changed by the interleaver 25 according to the timing control signal T9. The discriminator 31 outputs 1 when the output of the deinterleaver 29 is greater than 0 and 0 when it is less than 0 according to the timing control signal T11 of the second timing controller 40. The output of the discriminator 31 is a value obtained by decoding the data encoded by the turbo code.

The second delayer 30 determines the difference between the output of the first MAP decoder 24 and the output of the first delayer 21 according to the timing control signal T10 of the second timing controller 40. Output after delaying while 28 completely completes decoding. The difference between the output of the deinterleaver 29 and the output of the second delay unit 30 becomes the following additional information. If the next additional information is replaced with the current additional information and then newly decoded from the beginning, the decoder of the turbo code may correct more errors. This operation is called repetitive decoding. The MAP decoder is a decoder that implements a MAP algorithm that can minimize symbol errors.

The MAP algorithm is as follows.

In step 1, D _i (R _k , m) from time k = 0 to k = N + M−1 is calculated as in Equation 3 below.

[Equation 3]

Where i is 0 or 1 and sigma ² is the variance of noise. x _k is an information symbol at time k, and y _k is a parity symbol at time k. m means the state of the component encoder, and when the number of memory of the component code is M, it has a value from 0 to 2 ^M -1. Denotes the output bit of the component encoder when the state of the component encoder is m and the input bit is i at time k.

In step 2, if all the tail bits are encoded, the memories of the constituent encoder have all zeros. define i = 0, 1, We define m = 1, ... 2 ^M -1. here Means that when the input is i, the next state of the constituent encoder is m.

In step 3, k = N + M-2 to k = 0 Is calculated as in Equation 4 below.

[Equation 4]

here to be. And Means the next state of the constituent encoder when the input is i and the state of the constituent encoder is m.

In step 4, the initial values of the memory of the constituent encoder at time k = 0 are all 0, so A ⁱ ₀ = D _i (R ₀ , 0), i = 0, 1, and A ⁱ ₀ (m) = ∞, Let i = 0, 1, m = 1, ..., 2 ^M -1.

In step 5, k = 1 to k = N + M-1 Is calculated as in Equation 5 below.

[Equation 5]

In step 6, L (d _k ) from k = 0 to k = N-1 is calculated as in Equation 6 below.

[Equation 6]

The outputs of the MAP decoder are N L (d _k ), k = 0, ..., N-1.

The MAP algorithm, which is the decoding algorithm of the turbo code, is a decoding algorithm that can minimize symbol errors. The key steps of the MAP algorithm are divided into steps 1 through 6, which contain two key equations: step 3 and step 5. The two equations of step 3 and step 5 are recursive. Therefore, an initial value is required to be calculated recursively. Initial values are set in steps 2 and 4. Always use true to set the initial value. In other words, we take advantage of the fact that the state of the encoder is initially 0, and that the state of the encoder after the fully coded tail is 0. This is illustrated in Fig. 5.

As shown in Fig. 5, the output of the MAP decoder is calculated by the formula of step 6. As you can see, we can compute all of B, store it in memory, and compute A while calculating the output. Of course, the opposite is also possible. Therefore, the MAP algorithm requires a memory that is proportional to the size of the frame, and the decoding delay is also large. On the other hand, the multi-tail turbo code can be expressed as shown in FIG.

Where FS_i is the first encoder state of the i th block, LS_i is the last encoder state of the i th block, D_i is the input portion of the i th block, T_i is the tail portion of the i th block, A_i is the A calculation of the i th block, B_i Denotes the B calculation of the i-th block and L_i denotes the output calculation of the i-th block. 6 illustrates an example in which an input is divided into three blocks. Since each block has a tail, we can see that both FS_i and LS_i are zero. Using this, A_i and B_i can be initialized in steps 2 and 4 for each block. Once initialized, the remaining A_i and B_i can be calculated using the equations of steps 3 and 5. The values in the other blocks have no effect on calculating A_i and B_i. Thus, each block can be calculated independently. If there is only one decoder, first calculate A_0 and B_0 and then output L_0, then calculate A_1 and B_1 and then L_1, and finally calculate A_2 and B_2 and then L_2. Therefore, the memory required for this is proportional to the size of the block. If there are three MAP decoders, the first decoder can calculate the D_0 part, the second decoder can calculate the D_1 part, and the third decoder can calculate the D_2 part at the same time. This is called parallel decoding.

Next, when N is the number of input bits and M is the number of memories of the constituent encoder, each block described above for each time zone according to the timing control signals T1-T11 of the second timing controller 40 during multi-tail decoding. Are shown in Table 3 below. Here, D is a time delay for the first decoder to decode, and D 'is a time delay for the second decoder to decode.

TABLE 3

As can be seen from Table 3, the multi-tail turbo code decoder of the first embodiment according to another aspect of the present invention is used for the N to N + M time intervals in the fourth selector 22 and the fifth selector 23. One tail is selected, and the second tail is selected during the 2N + M + D to 2N + 2M + D time intervals in the fifth selector 26 and the sixth selector 27.

In the decoder of the second embodiment according to another aspect of the present invention, since four tail bits are actually decoded, they are shown in Table 4. In Table 4, the number of blocks is 2, N is the number of input bits, M is the number of memories of the component encoder, the first block is N0, and the second block is N1. Here, D is a time delay for the first decoder to decode, and D 'is a time delay for the second decoder to decode.

TABLE 4

As can be seen from Table 4, the multi-tail turbo code decoder selects the first tail in intervals N0 to (N0-1) and (N + M + D) to (N + 2M + D-1). Select the second tail in the interval (N + N0 + 2M + 2D) to (N + N0 + 3M + 2D-1) and (2N + 3M + 2D + D ') to (2N + 4M + 2D + D'). To decode the N-bit input.

The encoder and decoder of the multi-tail turbo code according to the present invention have been described above. As described above, the MAP decoder, which is a core part of the turbo code decoder, requires a memory proportional to the sum of the input length N and M, the number of memories of the constituent encoder. This means that communication services of different input lengths require the use of different types of MAP decoders.

The present invention relates to the use of multitail to process all services irrespective of the length of input data with a MAP decoder having an input symbol length of N _f .

Let the length of the input data be N> N _f . First, the N bit input data is divided into K blocks such that the length N _i <N _f of each block. then Satisfies. In the present invention, a tail is added after encoding N_i data for each block, whereas an encoder of an existing turbo code encodes all input data and adds a tail at the end. This can be implemented by changing only the time for operating each block of FIG. Similarly, the decoder of a turbo-tail having multiple tails can be implemented by changing only the time for operating each block of FIG.

The code rate of an existing turbo code whose length of input data is N and the number of memory of the configuration code is M is The code rate of a turbo code with K multi-tails is to be. This means that when the transmission power per input bit is the same, a symbol coded with a multi-tail turbo code has a smaller transmission power than a symbol coded with a conventional turbo code. In the case of encoding a turbo code having a multi-tail, it means that a wider bandwidth is used than when encoding a conventional turbo code. However, since N is much larger than M, there is little difference between a turbotail having a multiple tail and a conventional turbocode.

In communication systems, the specifications of input frames and transmission frames are often different. In this case, dummy frames are added to the input frame to meet the transmission frame specification. For example, let N = 104 be the length of input data. When the number of memories of the configuration code is encoded by a turbo code of M = 2, the length of the encoded data is 3N + 4M = 320. If the length of the transmission frame is 384, 64 bits are added to the 320 bits in a dummy to form a transmission frame.

The dummy bits added to match the transmission frame only waste power and bandwidth, except for the fact that the transmission frame is specified. In this case, a method of transmitting a multitail using a turbo code having a multitail instead of dummy bits may be considered. In the previous example, because there are 64 dummy bits, it is possible to use a turbo code having 9 multiple tails. In this case, decoding is possible using a MAP decoder having an input symbol size of 12. Therefore, wasteful resources can be effectively utilized by using a turbo code having multiple tails instead of unavoidable dummy bits.

Turbocodes with multiple tails can be decoded with a single MAP decoder no matter what size the input data has, and when decoding, the existing and final states of the constituent code for the entire input data in conventional turbocodes. Compared to using the fact that is 0, in the present invention, since the initial state and the last state of the component code can be used for each block, the performance is superior to that of the existing turbo code. However, as K increases, the distance distribution characteristic of a multi-tail turbo cord becomes worse. To some extent, the performance increases as K increases, but when K increases, performance decreases.

When the input data of length 104 is encoded with a turbo code of 2 memory codes, a turbo code having 8 multi-tails has a bit error rate of 10 ^-4 required in an AWGN channel compared to a conventional turbo code. 0.5 dB is excellent. When the length is 24, performance improvement of 1.0 dB or more is possible by using a turbo cord having four multi-tails.

Since the turbo code is decoded frame by frame, the decoding delay is very long. Therefore, if the decoding delay must be short, the turbo code cannot be used even though the performance of the turbo code is superior to other codes. However, since the turbo code having the multi-tail of the present invention can be decoded in blocks, M blocks can be decoded simultaneously using M decoders. In this case, since the decoding delay is 1 / M times, parallel decoding using a multi-tailed turbo code can use a turbo code having excellent performance even when a short decoding delay is required.

Multi-tailed turbocode has two characteristics in terms of bit error rate. The first characteristic is that when decoding, as described above, the initialization can be performed in several places using tails. Except for initialization, the decoder calculates A and B with the transmitted signal plus the error that occurred in the channel. In older turbocodes, we calculate A and B with inaccurate values except for two. However, many parts of multi-tail turbocode calculate (initialize) A and B with the correct values. Furthermore, in recursion, initialization plays a very important role. Experimental results show that the bit error rate at the beginning and end of the block is reduced by 1/10 compared with other parts. The second characteristic is that the free hamming distance varies. Looking at the distance distribution of the multi-tailed turbo code, the free hamming distance decreases as the block is divided into several blocks. This causes an increase in the bit error rate. Designing the turbocode interleaver for multi-tailed turbocode can help to some extent reduce the free hamming distance. As described above, the characteristics of reducing the bit error rate and increasing the bit error rate exist simultaneously in the multi-tail turbo code. Therefore, by dividing into appropriate blocks, the characteristic of reducing the bit error rate at the bit error rate of interest (10 ^-3 , 10 ^-4 , 10 ^-6, etc.) can be made stronger.

As described above, the present invention can be implemented not only by adjusting the operating time of each block in the encoder and the decoder of the existing turbo code, but also can obtain better decoding performance than the existing turbo code. In particular, when a large number of dummy bits are used to match a transmission frame, a very good performance improvement and hardware savings can be obtained. In addition, by using a multi-tailed turbo code, one MAP decoder can process services having various lengths. In addition, since the multi-tailed turbo code supports parallel decoding, it can be used for a service requiring a short decoding delay, in which the turbo code cannot be used.

[Effects of the Invention]

As described above, the existing turbo code encoder processes the input data into one block, but the present invention divides one input data into a plurality of blocks using a timing controller and adds a tail to each block to add one input. By processing data in parallel as a plurality of map decoders, it is possible to process data at a higher speed.

Claims (5)

An encoding method for encoding input data with at least one encoder, the method comprising: generating a turbo code having multiple tails by dividing the input data into at least one block and adding a tail to each block according to a timing control signal. Encoding Method. The method of claim 1, further comprising: dividing the input data into at least one block and sequentially interleaving each block, and then adding and encoding respective tail information to each interleaved input block; And And receiving and selectively outputting the input data, the tail information and the outputs of the encoders. A method of decoding a turbo code having a multi-tail generated by dividing input data input to at least one encoder into at least one block according to first timing control signals and adding one tail to each block, the method comprising: Selectively decoding the input data and tail information according to a second timing control signal, and Selectively decoding the interleaved value of the decoded information and the next sequential tail information, and deinterleaving the decoded information lastly and outputting the decoded information. According to the timing control signal, after dividing the input data into at least one block, adding tail information for each block, encoding the input data, dividing the input data into at least one block, sequentially interleaving each block, and then interleaving each input. At least one encoder corresponding to the number of blocks for adding and encoding respective tail information to a block; Selection means for selectively receiving the input data, the tail information and outputs of the at least one encoder; And And a timing controller configured to supply a timing signal to the at least one encoder and the selection means. Decode the turbo code having the multi-tail generated by dividing the input data input to the at least one encoder into at least one block according to the first timing control signals of the first timing controller and adding one tail to each block. Is a decoder, At least one decoders that selectively receive input data and tail information according to second timing control signals, and interleave the decoded input data and then selectively decode the sequential tail information together; Deinterleaver / determination means for deinterleaving and discriminating the decoded input data and outputting recovered data; And And a second timing controller for supplying the second timing control signals to the at least one decoder and the deinterleaver / identifying means.