KR101202582B1 - Multiple phase switching regulator with phase current sharing - Google Patents

Abstract

Phase current distribution network for current mode polyphase switching regulators. The polyphase switching regulator includes switching networks for generating phase currents of switching phase networks controlled by pulse control signals to convert the input voltage into an output voltage. The regulator generates pulse control signals based on current control values and at least one trigger value. The phase current distribution network includes conversion networks and phase current combining network. Each conversion network provides a phase current value based on the corresponding phase current, either directly or indirectly by measuring the actual current or by generating the phase current value. The phase current combining network generates an average phase current value based on the phase current values and subtracts the average phase current value from each phase current value to provide current control values used to control the switching networks.

Description

MULTIPLE PHASE SWITCHING REGULATOR WITH PHASE CURRENT SHARING}

This invention claims the benefit of priority of US Provisional Application No. 61 / 317,761, filed March 26, 2010, the contents of which are incorporated herein by reference in their entirety for various intents and purposes.

The present invention relates to a phase current distribution network for a current mode polyphase switching regulator, and a method for distributing current among phases of a current mode polyphase switching regulator, and a current mode polyphase switching regulator.

It is an object of the invention to provide a phase current distribution network for a current mode polyphase switching regulator, and a method of distributing current among the phases of the current mode polyphase switching regulator, and the current mode polyphase switching regulator.

According to the present invention, a plurality of pulse control signals are generated based on a plurality of current control values and at least one trigger value, each of which corresponds to a corresponding one of the plurality of pulse control signals for converting an input voltage to an output voltage. A phase current distribution network is provided for a current mode polyphase switching regulator comprising a plurality of switching networks for generating a corresponding one of a plurality of phase currents through respective inductances of a plurality of switching phase networks controlled by: The phase current distribution network comprises: a plurality of conversion networks each configured to provide a corresponding one of the plurality of phase current values based on the corresponding one of the plurality of phase currents; And generate an average phase current value based on the plurality of phase current values, and the average phase at each of the plurality of phase current values for providing a plurality of current control values used to control the plurality of switching networks. And a phase current coupling network that subtracts the current value.

Benefits, features, and advantages of the invention will be better understood with reference to the following description and the accompanying drawings, in which:
1 is a schematic diagram of a conventional multiple phase (or multiphase) switching regulator using synthetic ripple adjustment.
FIG. 2 is a schematic diagram of a multiphase switching regulator according to one embodiment using synthetic ripple adjustment with phase current distribution between two phases.
FIG. 3 is a timing diagram showing the inductor current of the output inductor for both of the polyphase switching regulators of FIGS. 1 and 2, individually during a transient event.
4 is a timing diagram showing the inductor current of the output inductor for both of the polyphase switching regulators of FIGS. 1 and 2 individually during steady state operation.
FIG. 5 is a simplified block diagram of a polyphase switch regulator according to one embodiment using synthetic ripple adjustment with phase current distribution between phases of any number “N”; FIG.
6 is a schematic diagram of an exemplary current distribution model, which may be used to implement any current distribution module of the polyphase switching regulator of FIG. 5; And
7 is a simplified schematic block diagram of a polyphase switching regulator according to another embodiment with phase current distribution between phases of arbitrary number " N ".

The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided within the context of certain applications and their requirements. However, various modifications to the preferred embodiment will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the specific embodiments shown and described herein, but it is in accord with the widest scope consistent with the principles and novel features disclosed herein.

1 is a schematic diagram of a conventional plurality of phase (or polyphase) switching regulators 100 using synthetic ripple adjustment. Where it can be appreciated that any suitable number of phases can be included, the switching regulator 100 is shown including two phase networks. The output node 101 generates an output voltage VOUT that is fed back to the inverting output of the error amplifier 103 through the first resistor R1. The voltage VDAC is provided via a second resistor R1 to the non-inverting input of the error amplifier 103, which has an output that generates a compensation voltage VCOMP at the compensation node 105. VDAC has a voltage level that represents the target voltage level of VOUT. The first and second resistors R1 have the same resistance. The first resistor R2 is coupled between the inverting input and the output of the error amplifier 103. The reference voltage VREF is provided at one end of the second resistor R2 having its other end coupled to the non-inverting input of the error amplifier 103. The first and second resistors R2 have the same resistance. The first current source 107 provides the window current IW at one end of the first window register RW at the positive window node 109 generating a positive window voltage VW +. The other end of the first window register RW is coupled to node 105 further coupled to one end of the second window register RW having the other end coupled to the negative window node 111 generating a negative window voltage VW-. do. The current sink 113 sinks the window current IW at the node 111. Each of the first and second window registers RW has the same resistance such that the window voltages VW + and VW− are offset from the compensation node 105 by the same amount in the balanced window voltage configuration.

The compensation node 105 is coupled to the non-inverting input of each of the pair of comparators 115 and 117. The non-inverting input of comparator 115 receives ripple voltage VR2, and the non-inverting input of comparator 117 receives another ripple voltage VR1. The output of the comparator 115 is coupled to the input of the edge detection module 119, and the output of the comparator 117 is coupled to the input of another edge detection module 121. The output of the edge detection module 119 is provided to the input of the set S of the reset reset flip-flop (SRFF) 123, and the output of the edge detection module 121 is the set of another SRFF 125. Is provided for input. SRFF 123 has a Q output providing a first pulse width modulation (PWM) signal PWM1, and SRFF 125 has a Q output providing a second PWM signal PWM2. PWM1 is provided at the input of the first switch driver module 127, and PWM2 is provided at the input of the second switch driver module 129. The first switch driver module 127 controls the first switch network including the electronic switches Q1 and Q2, and the second switch driver module 129 controls the second switch network including the electronic switches Q3 and Q4. . In one embodiment, electronic switches Q1-Q4 are each N-channel field effect transistor (FET) devices, although alternative types of switching devices, such as other N-type or P-type devices or the like, may be contemplated. (Eg metal oxide semiconductor FETs or MOSFETs). Driver modules 127 and 129 are configured according to the switch type. In one embodiment, the drains of Q1 and Q3 are coupled to the input voltage VIN, the sources of Q2 and Q4 are coupled to a reference node, such as ground (GND), and the source of Q1 and the drain of Q2 are first of the first phase network. Is coupled to the first phase node 131, and the source of Q3 and the drain of Q4 are coupled to the second phase node 133 of the second phase network. Gates of Q1 and Q2 are coupled to the first switch driver module 127, and gates of Q3 and Q4 are coupled to the second switch driver module 129. The first inductor L1 is coupled between the first phase node 131 and the output node 101, and the second inductor L2 is coupled between the second phase node 133 and the output node 101. Filter capacitor C is coupled between output node 101 and GND.

 VREF is provided to one end of the first ripple register RR and one end of the second ripple register RR. The first and second ripple resistors RR have the same resistance. The other end of the first ripple resistor RR is coupled to a first ripple node 135 that generates a first ripple voltage VR1, and the other end of the second ripple resistor RR is a second ripple node that generates a second ripple voltage VR2. 137 is combined. The first ripple capacitor CR is coupled between the first ripple node 135 and GND, and the second ripple capacitor CR is coupled between the second ripple node 137 and GND. The first and second ripple capacitors CR have approximately the same capacitance. The first current source 139 provides current gm1VIN to the first switch terminal of the first switch SW1 having the second switch terminal coupled to the first ripple node 135 (where the symbol point " Multiplication). The term "gm1" is a transconductance gain multiplied by the input voltage VIN to produce a current proportional to the input voltage VIN. The second current source 141 provides the same current gm1 · VIN to the first switch terminal of the second switch SW2, having a second switch terminal coupled to the second ripple node 137. PWM1 controls switch SW1 and PWM2 controls SW2. In each case, each switch is closed when the corresponding PWM signal is high and it is opened when the PWM signal is low. The first current sink 143 sinks the current gm1 · VIN from the first ripple node 135 to GND, and the second current sink 145 sinks the same current gm1 · VIN from the second ripple node 137 to GND. Sink it. Transconductance gain gm1 is multiplied by output voltage VOUT to produce a current proportional to output voltage VOUT. The first ripple node 135 is coupled to the non-inverting input of the first comparator 147 with an inverting input that receives a positive window voltage VW +. The output of the first comparator 147 provides the first reset signal R1 to the reset R of the SRFF 123. The second ripple node 137 is coupled to the non-inverting input of the second comparator 149 with an inverting input that receives a positive window voltage VW +. The output of the second comparator 149 provides a second reset signal R2 to the reset R of the SRFF 125.

In the operation of the switching regulator 100, each of the PWM1 and PWM2 signals toggles high and low individually to control the switching operation of the first and second phases. When SRFF 123 assumes that PWM1 is high, switch driver circuit 127 turns on switch Q1 and turns off switch Q2 so that VIN is effectively coupled to first phase node 131. When PWM1 goes low, the switch driver module 127 turns off switch Q1 and turns on switch Q2 so that VIN is effectively coupled to GND. As PWM1 toggles high and low for multiple switching cycles, switch driver module 127 and switches Q1 and Q2 convert input voltage VIN to output voltage VOUT through first output inductor L1 for the first phase network. To toggle between phase node 131 between VIN and GND. SRFF 125, switch driver module 129, switches Q3 and Q4 and output inductor L2 operate in a similar manner for the second phase network. The two phase networks alternate in activation in an attempt to distribute the current load evenly to the output node 101 for driving the load (not shown). The boost regulator is also contemplated when VOUT is greater than VIN, but when the input voltage VIN is greater than the output voltage, the switching regulator 100 acts as a buck regulator.

Each of the current sinks 143 and 145 individually draws charges from the first and second ripple capacitors CR, and individually draws a constant current gm1 · VOUT from the ripple nodes 135 and 137. When VR1 is greater than VREF, additional current flows from node 135 through first ripple resistor RR, and when VR1 falls below VREF, additional charging current flows from VREF through first ripple resistor RR. When PWM1 is high, the first phase network drives current to output node 101. Further, when PWM1 is high, the switch SW1 is closed in order for the current gm1VIN from the current source 139 to flow to the node 135 to charge the first ripple capacitor CR. While switch SW1 is closed, VR1 rises relatively quickly until it reaches the level of VW +. When VR1 rises above VW +, comparator 147 pulls R1 high to reset SRFF, which pulls PWM1 low. When PWM1 goes low, the switch SW1 is opened so that the ripple voltage VR1 starts ramping down at a relatively constant rate. When the voltage VR1 drops to the level of VCOMP, the comparator 117 asserts that its output is high to the edge detection circuit 121, which triggers to assert a high or positive pulse at the set input of the SRFF 125. In response to a pulse on its set input, SRFF 125 draws PWM2 high. When PWM2 is high, the second phase network drives current to the output node 101. Also, when PWM2 is high, the switch SW2 is closed so that the current gm1VIN from the current source 141 flows to the node 137 to charge the second ripple capacitor CR. The second phase operates in the same way as the first phase, so VR2 rises while SW2 is closed. When SW2 exceeds the VW + level, comparator 149 pulls R2 high to reset SRFF 125, which pulls PWM2 low again. Ripple voltage VR2 ramps down at a relatively constant rate until it falls below VCOMP, then comparator 115 pulses the aggregate input of SRFF 123 to edge detector module 119 to trim PWM1 back higher. Make the output high, causing it to do so. The operation repeats this method for the first and second phase networks to alternatively activate to drive current to the output node 101.

Switching regulator 100 is alternatively shown with only two phase networks while driving the output. As described above, additional phase networks may be included. For an additional phase network, each phase network causes activation up to the next final phase circuit, causing activation of the first phase network in a round robin fashion. Thus, if the final phase network causes activation of the first satellite network in a round robin fashion for a balanced configuration between the topology networks, the first phase network causes activation of the next or final phase network, or the like. Causes activation.

The switching regulator 100 has a balanced configuration if the loop compensation is reduced or eliminated, resulting in a significantly higher speed compared to the loop compensation based configuration. However, the increased speed results in a corresponding reduction or reduction of the natural phase current distribution between the phase networks. This is caused by a reduction in the resistance of the ripple resistor RR to achieve increased transient speed and reduced modulator output impedance. In particular, the resistance of RR is reduced to reduce the output impedance of the modulator and increase the transient response, which causes the composite current waveform to diverge from the inductor current. As described further below, the "synthetic current waveform" attempts to repeat the ripple current through the corresponding output inductor, and the ripple voltage generated for the corresponding ripple capacitor used to control the switching of the corresponding PWM signal. to be. Especially during transient events, this branching of the synthetically generated current causes a significant difference in the output current between the phase networks. Thus, the reduction in ripple resistance RR causes the alternating current (AC) information to lose part of its proportion to the inductor current. The mismatch is particularly evident during transient conditions, such as significant load changes. Thus, switching regulator 100 loses its inherent high frequency current balance as compared to a normal synthetic ripple regulator. Imbalance in current distribution means that one or more phase networks contribute more significantly to the load current than the rest of the phase networks, which effectively defeats the purpose and benefits of current distribution between the plurality of phases.

Various methods have been attempted to regain high frequency current balance between a plurality of phase circuits. One approach is to provide a very high bandwidth current balanced loop. The problem with this approach is that it is very difficult for very high bandwidth current balanced loops to stabilize. Another approach is to use an open loop algorithm for phase firing in an attempt to balance current. One problem with this approach is potential convergence because the algorithm is difficult to obtain and not flexible enough. Such algorithms may require tuning based on phase current and / or other system parameters, depending on the individual case.

Synthetic ripple adjustment is a method of synthetically generating a ripple voltage indicative of ripple current through an output inductor (eg, L1 or L2) rather than by direct or indirect measurement by other means. Thus, driving a "ripple" capacitor (eg CR) with a current proportional to the voltage for the output inductor provides the desired waveform shape. For example, the voltage at phase node 131 applied to one end of output inductor L1 is generally input voltage VIN when Q1 is on and Q2 is off (when PWM1 is high), and it is Q2 on and Q1 is It is zero (GND) when off. The current source 139 generates a VIN proportional current gm1 · VIN applied to the capacitor CR when PWM1 closes the switch SW1 and is high. When PWM1 is low, opening switch SW1, this current is removed from capacitor CR, so it is simulated at zero volts (V). The voltage at the output node 101 at the other end of L1 is VOUT. The current sink 143 generates VOUT proportional current gm1 · VOUT continuously applied to the capacitor CR. In this way, the ripple capacitor CR is driven with a collective current proportional to the voltage applied to the output inductor L1, so the ripple voltage VR1 generates the desired ripple waveform shape. Thus, the ripple voltage VR1 effectively repeats the waveform ripple current through the output inductor L1, and VR1 is used to control the toggling of the PWM1 signal controlling the first phase. Ripple voltage VR2 is generated in a similar manner to control the toggling of the PWM2 signal for the second phase. If provided, the additional phase network is controlled in a similar manner for composite ripple adjustment.

2 is a schematic diagram of a polyphase switching regulator 200 according to one embodiment using synthetic ripple adjustment with phase current distribution between two phases. Assuming similar devices or components have the same reference numerals, switching regulator 200 has some similar characteristics to polyphase switching regulators. As described further herein, the operation of switching regulator 200 is similar to that of switching regulator 100, except that switching regulator 200 includes improved current distribution between phase networks. Switching regulator 200 is also shown with two phase networks when it is understood that any suitable number of phase networks (ie, two or more) may be included. The first ripple register RR of the first phase network has a non-inverting input receiving VRFF, an inverting input receiving the first phase ripple voltage VR1 and an output coupled to the first ripple node 135. Is replaced by. As will be appreciated by those skilled in the art, transconductance amplifiers convert the input voltage into an output current. Transconductance amplifier 201 has a transconductance gain of gm2 when it amplifies the difference between input voltage VREF and VR1 by gm2 to provide an output current I1. The output current I1 is applied to the first ripple node 135. In this way, current I1 is generated according to equation I1 = gm2 (VREF-VR1), and current I1 is applied to the first ripple node 135. The output impedance of the transconductance amplifier 201 is necessarily constant. In one embodiment, the gain gm2 is tuned to match the value of the replaced ripple register RR. In this way, transconductance amplifier 201 effectively simulates the function of the first ripple resistor between voltages VREF and VR1 for the first phase network.

Another transconductance amplifier 203 having the same transconductance gain gm2 is provided and configured in the same way as the transconductance amplifier 201 except for its output coupled to the second ripple node 137. . In particular, the transconductance amplifier 203 has a non-inverting input receiving VREF, an inverting input receiving the first phase ripple voltage VR1 and an output coupled to the second ripple node 137. In this way, the output of the transconductance amplifier 203 generates the same current I1 applied to the second ripple node 137 for the purpose of current distribution between the first and second phase networks. In a similar manner, another transconductance amplifier 205 is provided having a non-inverting input receiving VREF, an inverting input receiving second phase ripple voltage VR2, and an output coupled to second ripple node 137. If it amplifies the difference between input voltages VREF and VR2 by gm2 to provide an output current I2 applied to the second ripple node 137, the transconductance amplifier 205 also has the same transconductance gain gm2. Has In this way, current I2 is generated according to equation I2 = gm2 (VREF-VR2), and current I2 is applied to the second ripple node 137. As before, in one embodiment, the gain gm2 is tuned to match the value of the replaced ripple resistor PR, so that the transconductance amplifier 205 is coupled between the voltage VREF and VR2 for the second phase network. Effectively simulates the function of the ripple register RR. Furthermore, another transconductance amplifier 207 still having the same transconductance gain gm2 is provided in the same manner as the transconductance amplifier 205 except that it has its output coupled to the first ripple node 135. And are constructed. In particular, transconductance amplifier 207 has a non-inverting input receiving VREF, an inverting input receiving second phase ripple voltage VR2, and an output coupled to first ripple node 135. In this way, the output of the transconductance amplifier 207 generates the same current I2 applied to the first ripple node 135 for the purpose of current distribution between the first and second phase networks.

FIG. 3 is a timing diagram showing inductor currents IL1 and IL2 of inductors L1 and L2, respectively, for both of the polyphase switch regulators 100, 200 during a transient event. The upper pair of curves shown at 301 show the inductor currents IL1 and IL2 for the polyphase switching regulator 100 before and after the transient event at time t1. As shown at 303, the inductor currents IL1 and IL2 track each other very closely before time t1. However, after the transient event at time t1, the inductor currents IL1 and IL2 diverge significantly from each other, as shown at 305. In this way, the first phase network of the switching regulator 100 provides significantly more current in response to transient events. Conversely, the lower pair of curves shown at 307 show the inductor currents IL1 and IL2 for the polyphase switching regulator 200 before and after the transient event at time t1. As shown at 309, inductor currents IL1 and IL2 track very closely to each other before time t1. After the transient event at time t1, the inductor currents IL1 and IL2 still track each other very closely as shown at 309. In this way, both phase networks of the switching regulator 200 distribute the current load during steady state operation and in response to transient events.

FIG. 4 is a timing diagram showing inductor currents IL1 and IL2 of inductors L1 and L2, separately, for the polyphase switching regulator 100 and the polyphase switching regulator 200, respectively, during steady state. The upper pair of curves shown at 401 show inductor currents IL1 and IL2 for the polyphase switching regulator 100, and the lower pair of curves shown at 403 for the polyphase switching regulator 200. Inductor currents IL1 and IL2 are shown. The current distribution is distributed for both regulator 100 and regulator 200 during steady state conditions. Although current distribution appears to be balanced and symmetrical for both switching regulator 100 and switching regulator 200, current distribution is particularly true for switching regulator 200 for the time after the transient event, as shown in FIG. It is significantly more balanced and symmetric over time.

5 is a simplified block diagram of a polyphase switching regulator 500 according to one embodiment using synthetic ripple adjustment with phase current distribution between any number "N" of phases. N is any positive integer greater than one. The polyphase switching regulator 500 receives the VOUT, VREF and VDAC voltages and provides a common error amplifier module 501 that provides the VCOMP voltage in a similar manner as described for the error amplifier 103 of the polyphase switching regulator 200. ). In fact, similar circuitry can be used as shown for the error amplifier 103. However, for N> 2, another trigger voltage VTRIG is determined based on N by VCOMP and phase control network 510. The window voltage range is represented by ΔVW = VW + −VW−, which is the historical window voltage when VCOMP is centered between VW + and VW−. In the general case, when ΔVW = 2 (VW +-VCOMP), VTRIG is determined as VTRIG = VCOMP + ΔVW (N-2) / N. When N = 2, VTRIG = VCOMP. The VTRIG is distributed to the N phase networks, shown as the first phase network 502, the second phase network 504, and subsequently up to the N or final phase network 506. Phase networks 502-506 generate an output voltage VOUT and are coupled to common output node 511 with output capacitor C between node 511 and ground in a manner similar to polyphase switching regulator 200.

The first phase network 502 includes a current distribution 1 module 503, a window comparator 1 module 505, a phase comparator 1 507, and a driver 1 module 509. The current distribution 1 module 503 receives VREF and ripple voltages VR1, VR2, ..., VRN (VR1-VRN), and has an output coupled to the node generating the first ripple voltage VR1. The current distribution 1 module 503 can be implemented in a similar manner to the transconductance amplifiers 201 and 207 of the polyphase switching regulator 200, except in the case of including N amplifiers. The window comparator 1 module 505 is coupled to the node generating VR1 and receives a first pulse width modulation (PWM) signal PWM1 and a window voltage VW +, and a first reset signal for the phase comparator 1 module 507. Provide R1. The window comparator 1 module 505 is similar to that shown for a multiphase switching regulator 200 including a current source 139, a current sink 143, a switch SW1, and a ripple capacitor CR and a comparator 147. Can be executed. The phase comparator 1 module 507 receives the final or Nth phase 506, the ripple voltage VRN of VTRIG and R1, and provides a first phase network (provided to the window comparator 1 module 505 and the driver 1 module 509). Generates a PWM1 signal for 502). The phase comparator 1 module 507 can be implemented in a similar manner as shown for the multiphase switching regulator 200 including the comparator 115, the edge detection circuit 119, and the SRFF 123. Driver 1 module 509 receives PWM1 and drives VOUT on output node 511 following multiphase operation. Driver 1 module 509 may be implemented in a similar manner as shown for polyphase switching regulator 200 including switch driver circuit 127, switches Q1, Q2 and inductor L1.

The second phase network 504 includes a current distribution 2 module 513, a window comparator 2 module 515, a phase comparator 2 module 517, and a driver 2 module 519. The current divider 2 module 513 is similar to the current divider 1 module 503, except when coupled to a node that generates a second ripple voltage VR2 for the second phase. The window comparator 2 module 515 is similar to the window comparator 1 module 505 except for receiving PWM2 and coupled to VR2 providing R2. Phase comparator 2 module 517 is similar to phase comparator 1 module 507 except for receiving the ripple voltage VR1 from R2 and the first phase network 502, and providing PWM2. Driver 2 module 519 is similar to driver 1 module 509 except that it responds to PWM2 to drive the VOUT voltage. Each phase network is similarly configured up to the final network 506 including the current distribution N module 523, the window comparator N module 525, the phase comparator N module 527, and the driver N module 529. As described above, each phase network causes activation to the next final satellite network, causing activation of the first satellite network in a round robin fashion. Thus, VR1 from the first phase network 502 activates the second phase network 504, and subsequently VRN-1 from the second to the final phase network provided to activate the final phase network 506. It is provided to make. In addition, the VRN from the final phase network 506 is provided to activate the first phase network 502 in a round robin fashion.

6 is a schematic diagram of an exemplary current distribution module 600, which may be used to implement any current distribution modules 503, 513,..., 523 of the polyphase switching regulator 500. VREF is provided to each non-inverting input of the series of N transconductance amplifiers 601, 603, ..., 605 (601-605). The output of the transconductance amplifiers 601-605 is a common ripple node that generates one of the corresponding ripple voltages VR1-VRN, typically shown as VRX, when "X" represents any phase number from 1 to N. Are joined together at 602. The first transconductance amplifier 601 has an inverting input that receives the first phase ripple voltage VR1, the second transconductance amplifier 603 has an inverting input that receives the second phase ripple voltage VR2, and subsequently the final As far as the final transconductance amplifier 605, which has an inverting input that receives the phase ripple voltage VRN. The output of the first transconductance amplifier 601 is a current for modifying the voltage of VRX on node 602 based on the voltage difference between VREF and VR1 multiplied by gain gm2, or I1 = gm2 * (VREF-VR1). Generates I1 and the output of the second transconductance amplifier 603 is a current for modifying the voltage of VRX based on the voltage difference between VREF and VR2 multiplied by gain gm2, or I2 = gm2 * (VREF-VR2). The final transconductance, generating I2, and subsequently generating a current IN to modify the voltage of VRX based on the voltage difference between VREF and VRN multiplied by gain gm2, or IN = gm2 * (VREF-VRN). So is the output of amplifier 603. This same circuit is repeated as the current distribution module for each phase.

The gain gm2 of each of the transconductance amplifiers 601, 603,..., 605 (601-605) may be adjusted to any suitable value following a given implementation. In one embodiment, the gain gm2 is configured to average the phase currents of all phases, where the average current value is effectively subtracted from the ripple voltage of each phase network. As shown in Fig. 2, for example, each ripple voltage, such as VR1, has a ripple capacitor CR, output voltage VOUT and input voltage when the corresponding pulse control signal (e.g. PWM1) is active (switch SW1 closed). It is first generated based on the value of VIN. Ripple voltage VR1 is adjusted based on the I1-IN current, collectively representing the average phase current through the output inductor. The ripple voltage VRX of each phase network is adjusted or modified in the same way based on the phase current, and the ripple voltages VR1-VRN are modified or adjusted ripple voltages. Each ripple voltage is a current control value used to control one switching of the corresponding phase network.

In alternative embodiments, duplicate transconductance amplifier circuits provided in other phases may be replaced with current mirror circuits or the like. In one embodiment, the circuit distribution module for each phase includes a single transconductance amplifier that compares VREF with the ripple voltage of phase VRX and provides a current regulation output IX to the corresponding ripple node. In addition, one or more current mirrors or the like are provided in the current distribution module of each phase for the mirror IX to the ripple node for each different phase of the polyphase switching regulator. For example, with reference to FIG. 2, the transconductance amplifier 203 outputs an input coupled to the output of the transconductance amplifier 201 for receiving current I1 and a current I1 for the second ripple node 137. It can be replaced with a current mirror circuit (not shown) having an output coupled to the second ripple node 137 for mirroring. Similarly, transconductance amplifier 207 is first ripple node 135 for mirroring current I2 to input and first ripple node 135 coupled to the output of transconductance amplifier 205 for receiving current I2. It can be replaced by a current mirror circuit (not shown) having an output coupled to it. In this way, each phase circuit includes one transconductance amplifier and a current mirror for each additional phase circuit in a multiphase configuration for mirroring current at different ripple nodes.

In summary, in a synthetic ripple regulator embodiment, the ripple resistor coupled between each ripple voltage node and reference voltage of every phase circuit must be replaced by a transconductance amplifier tuned to simulate or match the same current or otherwise ripple. It is generated through a register. This current is then mirrored and applied to the ripple node for every other phase circuit. Current mirroring is performed using an additional redundant transconductance amplifier or current mirror circuit or the like. In this way, each phase circuit has the same current distribution circuit coupled to its ripple node.

7 is a simplified schematic block diagram of a polyphase switching regulator 700 according to another embodiment with phase current distribution between any number "N" of phases, that is, where N is any positive integer greater than one. Yes it is. The polyphase switching regulator 700 may include a common error amplifier module 501 that receives the VOUT, VREF and VDAC voltages, and provides the VCOMP voltage in a manner similar to that described above. VCOMP can be used as the trigger voltage point for two phases. However, if N> 2, the other trigger voltage VTRIG is determined based on N by VCOMP and phase control network 510 in a similar manner as described above. The VTRIG is distributed to each of the N phase networks shown as the first phase network 702, the second phase network 704, and subsequently up to the last or Nth phase network 706. Phase networks 702-706 are coupled to common output node 708, which generates output voltage VOUT. Output capacitor C is coupled to node 708 and ground for filtering VOUT in a similar manner as described above. The phase networks 702-706 may be configured to operate in a similar manner as the polyphase switching regulator 200 and will not be described further. In one embodiment, separately, the phase currents IL1, IL2, ..., ILN through the output inductors L1, L2, ..., LN are individually corresponding to the corresponding current sense voltages VIL1, VIL2, ..., Measurements are made using current sensors 701, 702,... 705, as shown, which provide the VILN. Thus, VIL1 is a voltage value proportional to the phase current IL1, VIL2 is a voltage value proportional to the phase current IL2, and so on to VILN, which is a voltage value proportional to the phase current ILN. Current sensors 701, 702,... 705 may be combined with series coupled resistors or the like, or filter circuits coupled to an output inductor, or any other suitable method for measuring phase network current. May be implemented in any suitable manner as understood by those skilled in the art.

The polyphase switching regulator 700 includes a phase current distribution network 707 for distributing current among N phase networks. The phase current distribution network 707 includes a phase 1 current value module 709 for the first phase network 702, a phase 2 current value module 711 for the second phase network 704, and an Nth phase network ( A phase current value module for each phase network, including up to phase N current value module 713 for 706. Each of the phase current value modules 709, 711,... 713 carries a corresponding phase current value for each phase network according to some method of generating or otherwise determining the phase current. In one embodiment, the phase current value modules 709, 711, ..., 713 are individually configured to receive and deliver "real" current values VIL1-VILN, directly or indirectly, by current sensors. Sensors 701, 702,..., 705. In an alternative embodiment, the phase current value modules 709, 711, ..., 713 generate and provide a corresponding current waveform in a similar manner as described above for the polyphase switching regulator 200, corresponding synthesis. Generate current values. In any case, the polyphase current values from the phase current value modules 709, 711,... 713 add together the phase current values together to provide the phase current sum value, shown as VSUM. 715 (eg, adder). The VSUM output from the combiner 715 divides the VSUM by the number of phases, or N, and provides a mean phase current value corresponding to the filter 719, such as a low pass filter (LPF) or the like. To the input of the divider module 717. Filter 719 individually has an average phase current at each inverting input of the series of combiners 721, 723, ..., 725 for phase networks 702, 704, ..., 706. Provide the value VAVG. Each phase current value from the phase current value modules 709, 711,..., 713 is individually one of the combiners 721, 723,..., 725 that outputs VR1-VRN values. To a corresponding one non-inverting input. VR1-VRN values are provided to the non-inverting inputs of corresponding comparators for each of the phase networks in a similar manner as described above.

Although the invention has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and they are contemplated. In one example, although certain embodiments have been described with respect to hysteresis current mode regulators, the present invention applies to any type of current mode that controls the regulator. Those skilled in the art will recognize the concepts and specific implementations based on designing or modifying other structures to serve the same purpose of the present invention without departing from the spirit and scope of the present invention as defined by the following claims. It must be acknowledged that the examples are easy to use.

119, 121: edge detection
501 error amplifier
503, 513, 523: current distribution
505, 515, 525: window comparators
507, 517, 527: phase comparators
509, 519, 529: driver
510: phase control
709: phase 1 current value
711: phase 2 current value
713: phase N current value
719: filter

Claims (16)

Generate a plurality of pulse control signals based on the plurality of current control values and at least one trigger value, each of which is controlled by a corresponding one of the plurality of pulse control signals for converting an input voltage to an output voltage; A phase current distribution network comprising a plurality of switching networks for generating a corresponding one of a plurality of phase currents through each inductance of the switching phase networks:
A plurality of conversion networks each formed to provide a corresponding one of the plurality of phase current values based on the corresponding one of the plurality of phase currents; And
Generate an average phase current value based on the plurality of phase current values and at each of the plurality of phase current values to provide a plurality of current control values used to control the plurality of switching networks. A phase current distribution network for a current mode polyphase switching regulator, comprising: a phase current coupling network subtracting the voltage. The method of claim 1,
Each of the plurality of conversion networks comprises a synthetic ripple network that modifies the ripple voltage for a corresponding one of the plurality of ripple nodes by a corresponding one of the plurality of proportional values, each of the plurality of proportional values And is proportional to the phase current through an inductance of a corresponding one of the switching phase networks. The method of claim 2,
The synthetic ripple network is:
A ripple capacitor coupled between the reference node and a corresponding one of the plurality of ripple nodes;
A current sink for sinking current in proportion to the output voltage from the corresponding ripple node; And
And a current source for supplying a current proportional to an input voltage to a corresponding ripple node when a corresponding one of the plurality of pulse control signals is active. The method of claim 2,
The phase current combining network comprises a plurality of transconductance networks, each of the plurality of transconductance networks comprising a plurality of transconductance amplifiers, the plurality of transconductance amplifiers corresponding to one of a plurality of ripple nodes. Provide one of the plurality of proportional phase currents, each of the plurality of proportional phase currents proportional to a difference between a reference voltage and a corresponding one of the plurality of ripple nodes; . The method of claim 4, wherein
Wherein each of the plurality of transconductance amplifiers has a gain based on the number of the plurality of switching phase networks such that the plurality of transconductance amplifiers collectively generate the average phase current value. The method of claim 1,
And wherein the plurality of conversion networks comprise a plurality of current sensors each coupled to a corresponding one inductance of the plurality of switching phase networks. The method of claim 1,
The phase current coupling network is:
A first adder for adding the plurality of phase current values together to provide a phase current sum value;
A divider by an N module dividing the sum of the phase currents by the number of phases of a polyphase switching regulator to determine the average phase current value; And
And each of the plurality of second adders for subtracting the average phase current value from a corresponding one of the plurality of phase current values. 8. The method of claim 7,
The phase current combining network further comprises a low pass filter for filtering the average phase current value. A plurality of phase networks for converting an input voltage to an output voltage, the switching network operative to generate a corresponding one of the plurality of phase currents through an inductor controlled by a corresponding one of the plurality of pulse control signals, and A plurality of phase networks including a control network providing a corresponding one of the plurality of pulse control signals based on at least one trigger value and a corresponding one of the plurality of distributed phase current values;
An error network providing an error value based on an error in the output voltage;
A control network providing at least one trigger value based on the error value; And
A plurality of conversion networks each configured to provide a corresponding one of the plurality of phase current values based on the corresponding one of the plurality of phase currents, and an average phase current value based on the plurality of phase current values. And a phase current distribution network having a phase current combining network that generates and subtracts the average phase current value from each of the plurality of phase current values to determine the plurality of distributed phase current values. Current mode polyphase switching regulator. The method of claim 9,
Each of the plurality of conversion networks comprises a synthetic ripple network for adjusting a ripple voltage at a corresponding one of a plurality of ripple nodes by a corresponding one of a plurality of proportional values, wherein the plurality of proportional values comprise the plurality of phases A current mode polyphase switching regulator, characterized in that it is proportional to the phase current through a corresponding one inductor in the networks. The method of claim 10,
The synthetic ripple network is:
A ripple capacitor coupled between a reference node and a corresponding one of the plurality of ripple nodes;
A current sink for sinking current in proportion to the output voltage from the corresponding ripple node; And
And a current source for supplying a current in proportion to an input voltage to a corresponding ripple node when a corresponding one of the plurality of pulse control signals is active. The method of claim 10,
The phase current combining network includes a plurality of transconductance networks, each of the plurality of transconductance networks comprises a plurality of transconductance amplifiers, each of the plurality of transconductance amplifiers corresponding to one of the plurality of ripple nodes. Provide one of the plurality of proportional phase currents, wherein each of the plurality of proportional phase currents is proportional to a difference between a reference voltage and a corresponding ripple voltage of the plurality of ripple nodes. Currents are all multi-phase switching regulators. A plurality of switching for driving a corresponding one of the plurality of phase currents through each inductance of the plurality of switching phase networks controlled by the corresponding one of the plurality of pulse control signals for converting the input voltage to the output voltage A method of distributing current among phases of a current mode polyphase switching regulator comprising each of the networks and generating a plurality of pulse control signals based on a plurality of current control values and at least one trigger value:
Providing each of the plurality of phase current values based on a corresponding one of the plurality of phase currents;
Generating an average phase current value based on the plurality of phase current values; And
Subtracting the average phase current value from each of the plurality of phase current values to provide a plurality of current control values used to control the plurality of switching networks. Current distribution method between. The method of claim 13,
Providing the plurality of phase current values comprises generating a plurality of ripple voltages on a plurality of ripple nodes based on an input voltage, an output voltage, and the plurality of pulse control signals; And
Generating the average phase current value and subtracting the average phase current value in each of the plurality of phase current values:
Generating each of the plurality of proportional current signals based on a difference conversion between a reference voltage and a corresponding one of the plurality of ripple voltages; And
Adding a plurality of proportional current signals to each of said plurality of ripple nodes. The method of claim 13,
Providing the plurality of phase current values includes measuring a phase current through each inductor of each phase and converting a corresponding one of the plurality of voltages; And
Generating the average phase current value includes adding the plurality of voltages together to provide a voltage sum and dividing the voltage sum by the number of phases to provide an average voltage. Way. 16. The method of claim 15,
And a low pass filter for filtering the average voltage.

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