KR101201313B1 - Liquid Crystal Display Device And Method For Fabricating The Same - Google Patents

Abstract

According to the present invention, when forming a black matrix on a TFT array substrate, an alignment key for disposing crystallization equipment is formed simultaneously with the black matrix, and the alignment key is used to accurately control the position of grain boundaries during active layer crystallization through the alignment key. And a method of manufacturing the liquid crystal display according to the present invention, comprising simultaneously forming a black matrix and an alignment key on a first substrate, and forming a black matrix and an alignment key on the entire surface of the first substrate. Forming a buffer layer, depositing amorphous silicon over the buffer layer, and placing a crystallization device equipped with a CCD camera capable of recognizing the alignment key on the amorphous silicon, wherein the CCD camera is placed on the alignment key. After aligning the crystallization equipment to recognize the amorphous silicon polycrystalline Crystallizing with licon, patterning the polycrystalline silicon to form a semiconductor layer, forming a gate insulating film over the entire surface including the semiconductor layer, and forming a gate electrode on the gate insulating film over the semiconductor layer Doping an impurity into the semiconductor layer using the gate electrode as a mask, forming an interlayer insulating film on the entire surface including the gate electrode, and source / contacting the semiconductor layer on the interlayer insulating film. Forming a drain electrode, forming a passivation layer on the entire surface including the source / drain electrodes, forming a pixel electrode connected to the drain electrode on the passivation layer, and forming a second substrate on the first substrate; Opposingly bonding and forming a liquid crystal layer therebetween.

CMOS TFT, Black Matrix, Opening Ratio, Crystallization, Alignment Key

Description

Liquid Crystal Display Device and Method for Manufacturing the Same {Liquid Crystal Display Device And Method For Fabricating The Same}

1 is a cross-sectional view of a conventional CMOS liquid crystal display device.

2 is a cross-sectional view of a CMOS liquid crystal display device according to the present invention.

3A to 3G are cross-sectional views of a CMOS liquid crystal display device according to the present invention.

Figure 4 is a plan view showing the position of the align key according to the present invention.

* Explanation of symbols on the main parts of the drawings

111 substrate 112 gate electrode

112a: storage electrode 113: buffer layer

114: semiconductor layer 114a: channel layer

115a and 115b: source / drain electrodes 116: gate insulating film

117: pixel electrode 118: interlayer insulating film

119: protective film 122: black matrix

130: align key 150: crystallization equipment

160: photoresist

The present invention relates to a liquid crystal display device (LCD) having an LTPS TFT structure in which a black matrix is positioned on a lower layer of a lower substrate. In particular, the present invention provides an alignment key on the same layer as the black matrix and through the alignment key. The present invention relates to a liquid crystal display device and a method of manufacturing the same, which serve as a position reference point for the active layer crystallization.

Liquid crystal display devices have a high contrast ratio, are suitable for gray scale display and moving image display, and have low power consumption.

Such a liquid crystal display device includes a thin film transistor (TFT) for selectively applying a signal to a pixel electrode, and a storage capacitor for maintaining a state of charge until a unit pixel area is next addressed. A TFT array substrate having a capacitor, a color filter array substrate having a color filter layer for implementing color, and a black matrix to prevent light leakage, a liquid crystal layer encapsulated between the two substrates, and driving the TFT array substrate. A driver circuit is provided to display an image by various external signals.

Here, the driving circuit is formed on a separate PCB substrate and connected to the TFT substrate by TCP. Recently, however, a method of forming the driving circuit on the TFT array substrate without forming a separate PCB has been proposed.

Therefore, a pixel driving thin film transistor is formed in each display pixel of the TFT array substrate to drive each pixel, and a thin film transistor for driving the pixel is operated in a non-display area to operate a gate line and a gate line. A thin film transistor for a driving circuit for applying a signal to a data line is formed.

Recently, a thin film transistor for driving a pixel among the thin film transistors is an n-type TFT capable of high-speed operation, and a thin film transistor for a driving circuit is a p-type TFT having a high power consumption together with the n-type TFT. ) There is active research on thin film transistors.

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to the related art will be described in detail with reference to the accompanying drawings. In the following, a CMOS liquid crystal display device will be described as an embodiment.

1 is a cross-sectional view of a conventional CMOS liquid crystal display device.

The conventional LCD liquid crystal display device is composed of a TFT array substrate, a color filter array substrate opposing thereto, and a liquid crystal layer interposed between the two substrates. The TFT array substrate includes n-type TFTs in a plurality of pixel regions. An active region for displaying an image and a driver circuit portion region having an n-type TFT and a P-type TFT to drive the active region are defined, and the color filter array substrate is provided with a black matrix and a color filter layer.

Specifically, in the active region, unit pixels are defined by gate lines arranged in a line and data lines vertically intersecting the gate lines, and the turn-on or turn-off of voltage is controlled in the unit pixels. An n-type TFT, a pixel electrode that applies a signal voltage to the liquid crystal layer as a region for transmitting light, and a storage capacitor parallel to the gate wiring to further provide a level-shift voltage. It is made small and keeps the charge charged in the liquid crystal during the turn-off period of the thin film transistor (non-selection period).

In this case, as shown in FIG. 1, the n-type TFT is formed on the entire surface including the semiconductor layer 14 including the source / drain region and the channel layer doped with n-type impurities, and the semiconductor layer 14. A gate insulating film 16, a gate electrode 12 overlapping an upper portion of the channel layer of the semiconductor layer 14 on the gate insulating film, an interlayer insulating film 18 formed on the entire surface including the gate electrode 12, and the The source / drain electrodes 15a and 15b respectively contact the source / drain regions of the semiconductor layer 14 on the interlayer insulating layer, and the drain electrodes 15b are connected to the pixel electrodes 17 to supply voltage to the pixel electrodes. Is applied.

The storage capacitor includes a semiconductor layer 14 doped with impurities, a storage electrode 12a formed on the same layer as the gate electrode 12, and a gate insulating layer 16 interposed therebetween. In this case, the storage electrode 12a extends to the outside of the active area to receive a voltage from the outside of the active area.

Referring to FIG. 1, the method of manufacturing the CMOS liquid crystal display device is as follows.

First, a buffer layer 13 is formed on an insulating substrate 11, amorphous silicon is deposited on the buffer layer 13, and then the amorphous silicon is crystallized into polycrystalline silicon.

Thereafter, the first semiconductor layer 14 and the second semiconductor layer (not shown) are formed by patterning the polycrystalline silicon using a photolithography technique using a first mask. An n-type thin film transistor (TFT) and a storage capacitor are formed in the first semiconductor layer through a post-process, and a p-type thin film transistor (TFT) is formed in the second semiconductor layer.

Next, after applying a photoresist (not shown) on the entire surface of the insulating substrate 11, a second mask is applied to cover the first semiconductor layer 14 of the n-type TFT region and the second semiconductor layer of the p-type TFT region. After patterning, the doping of the first semiconductor layer 14 of the storage area is performed by doping the entire surface of the substrate with storage doping.

Subsequently, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface of the insulating substrate 11 by a plasma enhanced chemical vapor deposition (PECVD) method. 16).

The first gate electrode 12, the storage electrode 12a, and the second gate electrode 12 are deposited by depositing a low-resistance metal layer on the gate insulating layer 13 on the first and second semiconductor layers and using a photoetch technique using a third mask. Gate electrodes (not shown) and gate wirings (not shown) are formed.

In this case, the first and second gate electrodes are formed to extend to branch from the gate wiring so as to overlap the upper portions of the first and second semiconductor layers. It forms in a predetermined area so that it may overlap with 1st, 2nd channel layer. The storage electrode 12a is formed to be parallel to the gate line, but overlaps the storage doped first semiconductor layer 14 to form a storage capacitor.

Next, after the photoresist is applied to the entire surface including the first gate electrode 12, a photoetching technique using a fourth mask is used to completely block the p-type TFT region and the storage region, and to form the first semiconductor of the n-type TFT region. After the patterned layer 14 is exposed, a high concentration of n-type impurity ions are doped with phosphorus (P) on the entire surface of the insulating substrate 11 to n-type the first semiconductor layer 14 of the n-type TFT region. Source and drain regions are formed and activated.

Subsequently, the photoresist is stripped, a new photoresist is applied to the entire surface including the first gate electrode 12, and then a photo-etching technique using a fifth mask completely blocks the n-type TFT region and the storage region. And patterning the second semiconductor layer of the p-type TFT region to be exposed, and then doping a high concentration of p-type impurity ions using boron (B) or the like on the entire surface of the insulating substrate 11 to form the second semiconductor layer of the p-type TFT region. P-type source / drain regions are formed in and activated.

Thereafter, the photoresist is stripped and an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the first gate electrode 12 by PECVD to form an interlayer insulating film 18.

Subsequently, the gate insulating layer 16 and the interlayer insulating layer 18 are selectively removed to expose the source / drain regions of the first and second semiconductor layers by a photoetching technique using a sixth mask to remove the first contact holes. Form.

Thereafter, a low-resistance metal layer is deposited to fill the first contact hole and patterned by photolithography using a seventh mask, thereby connecting the source / drain region of the first semiconductor layer through the first contact hole. One source / drain electrodes 15a and 15b are formed to complete the n-type TFT, and a second source / drain electrode (not shown) connected to the source / drain regions of the second semiconductor layer is formed to form the p-type TFT. Then, a data line (not shown) perpendicular to the gate line is formed at the same time.

As a result, an n-type TFT composed of the first semiconductor layer 14, the first gate electrode 12, and the first source / drain electrodes 15a and 15b is formed for each pixel and drives the respective pixels; Although not illustrated, the p-type TFT includes a second semiconductor layer, a second gate electrode, and a second source / drain electrode and is formed in a driving circuit part to apply a signal to each gate wiring and data wiring, and the first semiconductor layer ( 14), a storage capacitor composed of the gate insulating film 16 and the storage electrode 12a is formed for each pixel. Here, the n-type TFT may be formed in the driver circuit portion together with the P-type TFT.

Thereafter, an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the entire surface including the first source / drain electrodes 15a and 15b or an organic insulating material such as benzocyclobutene (BCB) or an acrylic material is applied to the protective film 19. ).

Subsequently, the passivation layer 19 and the interlayer insulating layer 18 are etched to form the second contact hole by using a photolithography technique using an eighth mask to expose the first drain electrode 15b.

Finally, indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited to contact the first drain electrode 15b through the second contact hole, and then patterned by a photoetch technique using a ninth mask. The pixel electrode 17 is formed.

The CMOS liquid crystal display device thus formed typically uses an array of nine masks to form an array substrate including an n-type TFT and a p-type TFT.

In this way, the array substrate on which the various thin film transistors (TFT) are formed is bonded by a sealant with the color filter array substrate 21 and the spacer therebetween. The liquid crystal is injected between the two substrates to form the liquid crystal layer 31 and the liquid crystal inlet is sealed to complete the liquid crystal display device.

In this case, a black matrix 22 is formed on the edge of the unit pixel region and the thin film transistor to prevent light leakage on the color filter array substrate, and the color filter layers 23 of R, G, and B are formed in the opening where the black matrix is not formed. ).

However, the above-described conventional liquid crystal display device and its manufacturing method have the following problems.

That is, the black matrix of the color filter array substrate is formed to shield an area where undesired light leakage occurs due to unstable control of liquid crystal molecules, and is typically formed on the edge of the unit pixel area and on the thin film transistor.

Specifically, since light leakage occurs in the spaced space between the gate wiring and the data wiring and the pixel electrode, the light is shielded through the black matrix provided on the color filter array substrate, and light emitted from the outside passes through the protective film. In order not to affect the semiconductor layer, a black matrix is provided on the thin film transistor to block light.

However, since the portion forming the black matrix becomes a light shielding portion, the area of the opening (L in Fig. 1) where the image is displayed is relatively small, resulting in a decrease in the aperture ratio of the device.

Furthermore, when light leakage from the lower substrate (TFT array substrate) is shielded by the black matrix of the upper substrate (color filter array substrate), the black matrix must be designed by sufficiently securing the bonding margin between the upper substrate and the lower substrate. The size of the black matrix is large, there is a problem that the aperture ratio of the device is lowered.

On the other hand, after depositing amorphous silicon, crystallization immediately into polysilicon, since the amorphous silicon is the first layer formed on the substrate and crystallization is performed without patterning, it is necessary to set an accurate position in the process of crystallizing amorphous silicon. Since there is no inkey, the crystallization process is generally performed through basic alignment possible in the equipment itself, and thus, grain boundary position control is not easy.

 The present invention has been made to solve the above problems, and by forming the black matrix formed on the upper substrate on the lower substrate (TFT array substrate), it is not necessary to increase the area to secure the bonding margin, thereby improving the aperture ratio of the device. In the case of forming a black matrix on a TFT array substrate as described above, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which accurately control the position of grain boundaries during active layer crystallization through an alignment key formed simultaneously with the black matrix. have.

The liquid crystal display device of the present invention for achieving the above object is a black matrix formed on the first substrate, an alignment key which is provided on the same layer as the black matrix and used to align the crystallization equipment, and the black matrix A buffer layer formed on the entire surface of the semiconductor substrate, a semiconductor layer formed on the buffer layer, a gate insulating film formed on the entire surface including the semiconductor layer, a gate electrode and a gate wiring formed on the gate insulating film on the semiconductor layer, and the gate electrode. An interlayer insulating film formed on the entire surface, a source / drain electrode contacting the source / drain region of the semiconductor layer on the interlayer insulating film, a data line crossing the gate wiring, and a protective film formed on the entire surface including the source / drain electrode; A pixel electrode connected to the drain electrode on the passivation layer; And a liquid crystal layer provided between the first substrate and the second substrate opposite to the first substrate and provided with the color filter layer.

The liquid crystal display device is divided into an active area and a driving circuit area. When the liquid crystal display device is a CMOS liquid crystal display device, an n-type TFT capable of high-speed operation as a pixel driving thin film transistor is provided in the active area. In the region, n-type TFTs capable of high-speed operation and p-type TFTs having excellent power consumption are provided as thin film transistors for driving circuits.

In addition, a method of manufacturing a liquid crystal display device for achieving another object of the present invention comprises the steps of simultaneously forming a black matrix and an alignment key on the first substrate, forming a buffer layer on the front surface including the black matrix; Depositing amorphous silicon on the buffer layer, arranging crystallization equipment based on the alignment key to crystallize the amorphous silicon, patterning the amorphous silicon to form a semiconductor layer, and forming the semiconductor layer Forming a gate insulating film on the entire surface of the semiconductor layer, forming a gate electrode on the gate insulating film on the semiconductor layer, doping impurities into the semiconductor layer using the gate electrode as a mask, and Forming an interlayer insulating film on the entire surface of the interlayer insulating film; Forming a source / drain electrode in contact with the layer, forming a protective film on the entire surface including the source / drain electrode, forming a pixel electrode connected to the drain electrode on the protective film; And bonding the second substrate to the first substrate and forming a liquid crystal layer therebetween.

As described above, the liquid crystal display device according to the present invention improves the aperture ratio by forming a black matrix on the lower substrate, and finely aligns the crystallization equipment using an alignment key formed simultaneously with the black matrix, and then crystallizes the amorphous silicon into polycrystalline silicon. Of course, when the polysilicon is patterned to form a semiconductor layer, the patterning process is performed using the alignment key.

Hereinafter, a liquid crystal display and a method of manufacturing the same according to the present invention will be described with reference to the accompanying drawings. Hereinafter, the CMOS liquid crystal display device will be described as an embodiment.

2 is a cross-sectional view of a CMOS liquid crystal display device according to the present invention, FIGS. 3A to 3G are process cross-sectional views of a CMOS liquid crystal display device according to the present invention, and FIG. 4 is a plan view showing the position of an alignment key according to the present invention.

In the active region of the TFT array substrate 111 according to the present invention, as illustrated in FIG. 2, a black matrix 122 that shields light leakage from an edge of a unit pixel and a region provided with a thin film transistor, and the black matrix A buffer layer 113 formed on the entire surface of the substrate, a gate line (not shown) and a data line (not shown) defining a plurality of unit pixels perpendicularly intersecting with each other; An n-type TFT controlling turn-on or turn-off, a pixel electrode 117 connected to a drain electrode 115b of the n-type TFT through a contact hole to apply a signal voltage to the liquid crystal, and the n-type TFT A storage electrode 112a overlapping a portion extending from the semiconductor layer 114 of the semiconductor layer 114 to form a storage capacitor, and an alignment key is disposed on the same layer as the black matrix on the outer portion of the active region. It is used in the crystallization process and the patterning of the control semiconductor layer.

In this case, the n-type TFT is insulated from the semiconductor layer 114 having a source / drain region and a channel layer 114a doped with n-type impurities, and the semiconductor layer 114 is insulated from the channel of the semiconductor layer 114. A gate electrode 112 overlapping the layer 114a and a source / drain electrode 115a insulated from the gate electrode 112 and contacting the source / drain regions of the semiconductor layer 114 through contact holes, respectively; 115b). Although not shown, the p-type TFT includes a semiconductor layer doped with p-type impurities, a gate electrode, and a source / drain electrode.

In the above, the gate wiring, the gate electrode 112 and the storage electrode 112a are provided on the same layer, the data wiring and the source / drain electrode are provided on the same layer, and the semiconductor layer 114 and the gate electrode 112 are provided. A gate insulating film 116 is further formed on the front surface, and an interlayer insulating film 118 is further formed on the front surface between the gate electrode 112 and the source / drain electrodes 115a and 115b, and the source / drain electrode ( A passivation layer 119 is further formed on the entire surface between the 115a and 115b and the pixel electrode 117.

The color filter array substrate 121 facing the TFT array substrate 111 is provided with color filter layers 123 of R, G, and B for color realization. The TFT array substrate 111 and the color filter array substrate are formed. The liquid crystal layer 131 is formed between the 121. Although not shown, a common electrode is further provided on the color filter layer of the color filter array substrate to form an electric field for controlling the driving of the liquid crystal layer together with the pixel electrode.

That is, the liquid crystal display device according to the present invention is characterized in that the black matrix is formed on the TFT array substrate instead of the color filter array substrate.

As such, by forming a black matrix for preventing light leakage on the lower substrate, it is not necessary to consider the bonding margin, thereby reducing the area of the black matrix and consequently widening the opening of the device. As a result of comparing the conventional liquid crystal display device with the present invention, an opening was secured by L '(see FIGS. 1 and 2).

In addition, an alignment key (130 in FIG. 4) may be simultaneously formed on the same layer as the black matrix 122, and the alignment key is used when patterning amorphous silicon. When the semiconductor layer is patterned to form a semiconductor layer, the semiconductor layer is patterned by performing an exposure, development, and etching process after aligning an exposure mask based on the alignment key.

In addition, the alignment key may be used to crystallize the semiconductor layer. As illustrated in FIG. 4, the alignment key 130 may be recognized using the CCD camera 150 mounted on the crystallization equipment using the alignment key 130. After fine alignment through the function, the crystallization proceeds. Then, the crystallization position can be precisely found based on the alignment key, so that the grain boundary position can be controlled, and the grain boundary of the channel layer of the entire panel can be uniformly controlled. It becomes uniform with respect to the whole panel.

Specifically, the manufacturing method of the CMOS liquid crystal display device is as follows.

First, as shown in FIG. 3A, conductive graphite or a conductive organic polymer resin having low light reflectance on the insulating substrate 111, or Cr or Cr oxide (CrO) for reducing light reflectance by using interference of light. A metal material is deposited and patterned by photolithography using a first mask to form a black matrix 122 and an alignment key (130 in FIG. 4).

The alignment key is used to precisely and finely adjust the position to be patterned and the position to be crystallized when patterning the semiconductor layer and crystallizing the semiconductor layer in a later step.

Next, as shown in Figure 3b, a silicon oxide (SiO ₂₎ on the entire surface of the insulating substrate 111 including the black matrix and aligned inki by using a chemical vapor deposition to form a buffer layer (113). This buffer layer prevents the diffusion of foreign matter from the insulating substrate 111 and the black matrix 122 into the semiconductor layer 114, improves the contact characteristics of the semiconductor layer 114 with respect to the black matrix 122, and mutually It serves to insulate.

Thereafter, amorphous silicon (a-Si: H) is deposited on the entire surface including the buffer layer 113 by plasma chemical vapor deposition using SiH ₄ and H ₂ mixed gas, and then mounted on a crystallization device. After fine-aligning the crystallization equipment through an alignment key recognition function using a camera, the semiconductor layer, which is amorphous silicon, is crystallized into polycrystalline silicon by rapidly melting and solidifying the laser layer by irradiating or heat treating the semiconductor layer.

Subsequently, the second mask is disposed using the alignment key and then patterned by photolithography to form the semiconductor layer 114 of the n-type TFT and the semiconductor layer (not shown) of the p-type TFT. At this time, the semiconductor layer of the n-type TFT extends to the storage capacitor region to serve as a storage capacitor lower electrode.

Next, a photoresist (not shown) is applied on the semiconductor layer and patterned by photolithography using a third mask to open only the semiconductor layer 114 in the storage capacitor region and leave the photoresist in the remaining region. Thereafter, storage doping is performed on the entire surface of the substrate to dope impurities into the semiconductor layer 114 of the storage capacitor region.

Next, as illustrated in FIG. 3C, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface including the semiconductor layer 114 by a plasma enhanced chemical vapor deposition method to form a gate insulating film ( 116).

 After that, the low-resistance metal layer may be formed on the gate insulating layer 116, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), or tantalum ( Ta), molybdenum-tungsten (MoW), and the like are deposited and patterned by a photoetch technique using a fourth mask to form a gate wiring (not shown), a gate electrode 112, and a storage electrode 112a.

The gate electrode includes a gate electrode of an n-type TFT and a p-type TFT, is formed at a position corresponding to a channel layer of a semiconductor layer to be formed through a later process, and is integrally connected to the gate wiring to receive a scan signal. . The storage electrode 112a is formed to overlap the storage doped portion to form a storage capacitor together with the storage doped semiconductor layer 114 and the gate insulating layer 116 stacked thereon.

Subsequently, lightly doped drain (LDD) is doped on both sides of the gate electrode 112 by doping low concentration n-type impurity ions onto the entire surface of the insulating substrate 111 using the gate electrode 112 and the storage electrode 112a as a mask. A doping layer (not shown) is formed. At this time, the region where the n-type impurity is not doped becomes the channel layer 114a. The LDD doped layer, which is an n-doped layer, is formed inside the source / drain region, which is an n + doped layer adjacent to the gate electrode, and serves to reduce an off current by reducing an electric field applied to a junction.

Thereafter, after the photoresist is applied to the entire surface including the gate electrode 112, the photoetching technique using the fifth mask completely blocks the p-type TFT region and the storage region, and the semiconductor layer 114 of the n-type TFT region. ) And then doped with a high concentration of n-type impurity ions using phosphorus (P) on the entire surface of the insulating substrate 111 to form a source / drain region in the semiconductor layer 14 of the n-type TFT region. Activate it. At this time, the LDD doped layer is blocked with the photoresist to dope n-type impurities.

Subsequently, the photoresist is stripped and a new photoresist 160 is applied to the entire surface including the gate electrode 112, as shown in FIG. 3D. Blocking the type TFT region and the storage region completely, patterning the second semiconductor layer of the p type TFT region to be exposed, and then doping a high concentration of p type impurity ions using boron (B) on the entire surface of the insulating substrate 111. Source / drain regions are formed in a semiconductor layer (not shown) of the p-type TFT region and are activated.

Thereafter, the photoresist is stripped, and as shown in FIG. 3E, an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the gate electrode 112 by PECVD to form an interlayer insulating film 118. After forming the photoresist, a photoresist having a photosensitive characteristic is applied to the entire surface including the interlayer insulating layer 118, and the interlayer insulating layer 118 and the gate insulating layer 116 are selectively removed by a photoetching technique using a seventh mask. Thus, contact holes are formed to expose the source / drain regions of the n-type TFT and the p-type TFT.

Subsequently, the low-resistance metal layer is embedded such that copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum (Ta). Source / drain electrodes deposited on the source / drain regions of the semiconductor layer 114 by depositing molybdenum-tungsten (MoW), patterning the low-resistance metal layer using a photoetching technique using an eighth mask, and the like. Data lines (not shown) formed integrally with the source electrodes 115a and 115b are formed. The source / drain electrodes include source / drain electrodes of n-type TFTs and p-type TFTs.

As a result, an n-type TFT composed of the n-type semiconductor layer 114, the gate electrode 112, and the source / drain electrodes 115a and 115b and formed in each pixel region or the driving circuit unit is completed, but is not illustrated. A p-type TFT composed of a type semiconductor layer, a gate electrode, and a source / drain electrode, which is formed in the driving circuit portion, is completed. As a result, a CMOS thin film transistor is completed.

Thereafter, as shown in FIG. 3F, an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the entire surface including the source / drain electrodes 115a and 115b or an organic insulating material such as benzocyclobutene (BCB) or an acrylic material. The protective film 119 is formed to form a contact hole, and the protective film is patterned to expose the drain electrode 115b by a photoetching technique using a ninth mask to form a contact hole.

Finally, ITO or IZO is deposited to contact the drain electrode 115b through the contact hole, and patterned by photolithography using a tenth mask to form the pixel electrode 117 in the pixel region.

By forming the black matrix on the CMOS-TFT array substrate as described above, a total of 10 masks are used to complete the array substrate including the n-type TFT and the p-type TFT.

As described above, the TFT array substrate on which the various thin film transistors (TFT) are formed is bonded to the color filter array substrate 121 on which the color filter layer 123 and the common electrode (not shown) are formed, and then the liquid crystal layer is formed between the two substrates. 131 is formed and the liquid crystal inlet is sealed to complete the liquid crystal display element.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the liquid crystal display device and the manufacturing method thereof according to the present invention have the following effects.

That is, unlike the prior art in which the design margin of the black matrix is sufficiently secured due to the bonding margin of the upper and lower substrates, the design margin of the black matrix can be reduced by forming the black matrix on the TFT array substrate. Therefore, since the area shielded by the black matrix becomes smaller, the opening of the element becomes wider.

In addition, prior to crystallizing the amorphous silicon, by forming an alignment key in the process of forming a black matrix at the same time, during the crystallization of the amorphous silicon layer through the alignment key to precisely fine-align the crystallization equipment to a desired position and then crystallization You can do it. Therefore, grain boundary position control becomes possible, and as a result, the crystallization of the entire panel is uniform, resulting in uniform electrical characteristics of the device.

Claims (13)

delete delete delete delete delete delete Simultaneously forming a black matrix and an alignment key on the first substrate, Forming a buffer layer on the entire surface of the first substrate including the black matrix and an alignment key; Depositing amorphous silicon over the buffer layer; Place a crystallization device equipped with a CCD camera capable of recognizing the alignment key on the amorphous silicon, and after the CCD camera recognizes the alignment key to align the crystallization device, crystallization of the amorphous silicon into polycrystalline silicon To do that, Patterning the polycrystalline silicon to form a semiconductor layer; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming a gate electrode on the gate insulating layer on the semiconductor layer; Doping the semiconductor layer with impurities using the gate electrode as a mask; Forming an interlayer insulating film on the entire surface including the gate electrode; Forming a source / drain electrode contacting the semiconductor layer on the interlayer insulating film; Forming a protective film on the entire surface including the source / drain electrodes; Forming a pixel electrode connected to the drain electrode on the passivation layer; And attaching a second substrate to the first substrate so as to face each other and forming a liquid crystal layer therebetween. The method of claim 7, wherein Doping an impurity in the semiconductor layer, Implanting n + impurity into the first semiconductor layer, Masking the first semiconductor layer and injecting p + impurities into the second semiconductor layer. The method of claim 7, wherein In the patterning of the semiconductor layer, a method of manufacturing a liquid crystal display device, characterized in that for performing a photo-etching process based on the alignment key. The method of claim 7, wherein After patterning the semiconductor layer, And performing storage doping of a predetermined portion of the semiconductor layer. 11. The method of claim 10, In the forming of the gate electrode, And forming a storage electrode on the storage doped semiconductor layer. The method of claim 7, wherein And the black matrix is formed under the gate wiring and the data wiring, and under the thin film transistor including the semiconductor layer, the gate electrode, and the source / drain electrode. The method of claim 7, wherein And a plurality of alignment keys formed at an outer portion of an active region of the first substrate.

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