KR101195166B1 - Memory array circuit - Google Patents

Abstract

Provided is a memory array circuit that corresponds to a nonvolatile memory device that stores two bits of data in one memory cell and that enables high-speed read operations. One end of the sub bit line SBL is connected to the common power supply CDV via the drain selector DS, and the other end is connected to the main bit line MBL via the source selector SS. The select signal for the drain select line DSA for the drain selector DS and the source select line SSE for the source selector SS are switched, and the sub bit line SBL is switched to the drain line or the source line for the memory cell MC. This enables reading and writing of the 2-bit memory cell MC. In addition, two memory cells MC are selected, and in these memory cells, the sub bit line SBL from the memory cell to the main bit line MBL is sandwiched. This reduces the parasitic capacitance of the wiring path and enables a high speed read operation.

Memory cells, array circuits, bits, sources

Description

Memory array circuit {MEMORY ARRAY CIRCUIT}

1 is a configuration diagram of a memory array circuit according to the first embodiment of the present invention.

2 is a configuration diagram of a conventional memory array circuit.

FIG. 3 is a diagram illustrating a state when the memory cells MC6 and MC9 are selected in FIG. 2.

4 is an explanatory diagram of a memory element corresponding to two bits.

FIG. 5 is a diagram illustrating a state when memory cells MC4 and MC7 are selected in FIG. 1.

FIG. 6 is a diagram illustrating a state when memory cells MC7 and MC10 are selected in FIG. 1.

Fig. 7 is a configuration diagram of the memory array circuit showing the second embodiment of the present invention.

Fig. 8 is a configuration diagram of the memory array circuit according to the third embodiment of the present invention.

[Description of Symbols for Main Parts of Drawing]

20, 20A, 20B: subblock 30: multiplexer

CDV: Common power line DS: Drain selector

DSA to DSH: Drain select line MBL: Main bit line

MC: Memory cell SS: Source selector

SSE, SSK to SS0: Source select line SBL: Negative bit line

WL: word line

The present invention relates to a memory array circuit for a nonvolatile memory device that stores two bits of data in one memory cell.

[Patent Document 1] Japanese Unexamined Patent Publication No. Hei 11-203880

[Patent Document 2] Japanese Unexamined Patent Publication No. 2000-57794

[Patent Document 3] Japanese Unexamined Patent Publication No. 2004-335797

2 is a configuration diagram of a conventional memory array circuit described in Patent Document 1.

This memory array circuit has a plurality of subblocks SUBBLK 1 (only one is shown in the figure) and one multiplexer MPX 2. The subblock 1 is interposed between a plurality of word lines WL0, WL1, ... arranged in parallel, a plurality of selector lines SL0, SL1, ... arranged intersecting these word lines, and these selector lines, It has a plurality of sub bit lines SBL0, SBL1, ... arranged to intersect the word line.

At each intersection of the word line WL and the selector line SL, memory cells MC0, MC1, ... are provided (only memory cells corresponding to the word line WL0 are shown in the drawing). Each memory cell MC stores data with or without charge accumulated in the floating gate. The control electrode is connected to the word line WL, and the drain electrode is connected to the selector line SL. The source electrode of the memory cell MC is connected to the corresponding sub bit line SBL.

Each selector line SL0, SL1, ... is connected to the common power supply line CDV via drain selectors DS0, DS1, ... which are each composed of switching transistors. Gates of even-numbered drain selectors DS0, DS2, ... are commonly connected to drain select lines DSE, and gates of odd-numbered drain selectors DS1, DS3, ... are commonly connected to drain select lines DSO. On the other hand, each of the sub bit lines SBLO, SBL1, ... is connected to the main bit lines MBL0, MBL1, ... through the source selectors SS0, SS1, ... which are each composed of switching transistors.

Although not shown in the drawing, a plurality of subblocks, such as this subblock 1, are connected in parallel to the main bit lines MBL0, MBL1, ....

The main bit lines MBL0, MBL1, ... are connected to the data lines DL0, DL1 via the multiplexer 2. The multiplexer 2 selects two adjacent main bit lines MBL in accordance with the selection signals Y0, Y1, ..., and connects them to the data lines DL0, DL1. The sense amplifiers SA0 and SA1 are connected to the data lines DL0 and DL1, respectively, and a data input circuit (not shown) and the like are connected. The sense amplifiers SA0 and SA1 read the stored contents of the memory cell MC by detecting the presence or absence of a current flowing through the selected memory cell MC to the ground potential.

FIG. 3 is a diagram illustrating a state when the memory cells MC6 and MC9 are selected in FIG. 2, and the thick lines represent the selected drain select line DS, the word line WL, and the source select line SS and the current flowing through the selected memory cells MC6 and MC9. It shows the route.

As shown in Fig. 3, the source select line SS and the select signal Y3 are set to " H ", so that the path from the sub bit line SBL3 to the main bit line MBL3 and the data line DL0 to the sense amplifier SA0 and the sub bit, A path from the line SBL4 through the main bit line MBL4 and the data line DL1 to the sense amplifier SA1 is formed. By setting the word line WL0 and the drain select line DSO to " H ", the path from the common power supply line CDV to the drain bit line SBL3 through the drain selector DS3 and the memory cell MC6, through the drain selector DS5 and the memory cell MC9 The path to the sub bit line SBL4 is formed.

Thus, for example, when the stored content of the memory cell MC6 is "1", the read current flows from the main bit line MBL3 to the sense amplifier SA0. When the stored content of the memory cell MC9 is "1", the read current flows from the main bit line MBL4 to the sense amplifier SA1.

As can be seen from Fig. 2, when reading the memory cells MC6 and MC9, the sub bit lines SBL3 and SBL4 are connected via the on resistances of the memory cells MC7 and MC8. The potentials of the sub bit lines SBL3 and SBL4 are approximately coincidence by the sense amplifiers SA0 and SA1 regardless of the contents of the memory cells MC6 and MC9. However, when the contents of the memories of the memory cells MC6 and MC9 are different from each other, some potential difference occurs in the sub bit lines SBL3 and SBL4, so that the leakage current flows through the memory cells MC7 and MC8. Therefore, in order to use this memory array circuit, it is necessary that the leakage current is small enough to be neglected.

On the other hand, in the selected memory cells MC6 and MC9, the memory cells MC7 and MC8 are sandwiched in the middle, and the sub bit lines SBL3 and SBL4 used for reading are located inside these memory cells MC6 and MC9. Therefore, components of the main parasitic capacitance other than the read paths such as the sub bit lines SBL3 and SBL4 and the main bit lines MBL3 and MBL4 are composed only of the selector line SL4 and the memory cells connected to the selector line SL4, and the parasitics generated in the read path. The capacity is limited to the area sandwiched between the selected memory cells MC6 and MC9. For this reason, the parasitic capacitance becomes very small and a high speed reading operation is attained.

However, the memory array circuit is intended for a nonvolatile memory cell that stores data depending on the presence or absence of charges accumulated in the floating gate, and the drain electrode and the source electrode are fixed in each memory cell.

On the other hand, as the demand for large memory capacity increases recently, nonvolatile memory devices capable of storing two bits of data in one memory cell have emerged.

4 is an explanatory diagram of a memory element corresponding to two bits described in Patent Document 3 above.

As shown in the cross-sectional structure of FIG. 4A, the memory device has a gate electrode 13 formed on the surface of the P well region 11 via a gate oxide film 12, and the sidewall portion of the gate electrode 13 is formed. The memory functional bodies 14L and 14R by the silicon nitride film are formed. Further, on the surface of the P well region 11, N-type diffusion regions 15L and 15R are formed so that a part thereof is lower than the memory functional bodies 14L and 14R. These diffusion regions 15L and 15R are switched to be used as source or drain electrodes in accordance with the voltage to be applied.

4B is a diagram illustrating an input operation principle of a memory device. In this case, the input refers to the injection of electrons into the memory functional body.

In order to input to the memory functional body 14L on the left side of the figure, the right diffusion region 15R is used as the source electrode and the left diffusion region 15L is used as the drain electrode. For example, 0V is applied to the diffusion region 15R and the P-type well region 11, and + 5V is applied to the diffusion region 15L and the gate electrode 13. As a result, the inversion layer 16 grows from the diffusion region 15R, but does not reach the diffusion region 15L so that a pinch-off point occurs. The electrons are accelerated by the high electric field from the pinch-off point to the diffusion region 15L to become so-called hot electrons. This hot electron is injected into the memory functional body 14L, whereby input is performed. On the other hand, since no hot electrons are generated in the vicinity of the memory functional body 14R on the right side, no input is performed.

On the other hand, in order to input into the memory function body 14R on the right side, the diffusion region 15L on the left side is used as the source electrode and the diffusion region 15R on the right side is used as the drain electrode.

4C is a diagram illustrating a read operation principle of a memory device.

When reading the information stored in the memory functional body 14L on the left side of the figure, the transistor is operated with the diffusion region 15L on the left as the source electrode and the diffusion region 15R on the right as the drain electrode. For example, 0V is applied to the diffusion region 15R and the P-type well region 11, + 1.8V is applied to the diffusion region 15L, and + 2V is applied to the gate electrode 13. At this time, when electrons are not accumulated in the memory functional body 14L, the drain current easily flows. On the other hand, when electrons are accumulated in the memory functional body 14L, the inversion layer is hard to be formed in the vicinity of the memory functional body 14L, so that the drain current hardly flows. Therefore, by detecting the drain current, the storage information of the memory functional body 14L can be read. On the other hand, when reading the information stored in the memory functional body 14R on the right side of the drawing, the transistor is operated with the diffusion region 15R on the right side as the source electrode and the diffusion region 15L on the left side as the drain electrode.

4 (d) is a diagram illustrating an erase operation principle of a memory device.

When the information stored in the memory functional body 14L on the left side of the figure is erased, a constant voltage (for example, + 5V) is applied to the diffusion region 15L on the left side, and 0V is applied to the P-type well region 11. The reverse bias is applied to the PN junction between the diffusion region 15L and the P-type well region 11, and a negative voltage (for example, -5V) is applied to the gate electrode 13. As a result, in the vicinity of the gate electrode 13 during the PN junction, the inclination of the potential is particularly increased due to the influence of the gate electrode to which the negative voltage is applied. For this reason, hot holes are generated in the P-type well region 11 side of the PN junction by an interband tunnel. This hot hole is led in the direction of the gate electrode 13 having a negative potential, hole injection is performed to the memory functional body 14L, and the memory functional body 14L is erased. In this case, 0 V may be applied to the diffusion region 15R. At this time, when erasing information stored in the memory functional body 14R on the right side of the drawing, the potentials of the diffusion regions 15R and 15L may be replaced.

As described above, in the memory element corresponding to two bits, the memory functional bodies 14L and 14R are formed in the left and right sidewall portions of the gate electrode 13, and the left and right sides are formed corresponding to the two memory functional bodies 14L and 14R. By using the diffusion regions 15L and 15R so as to be source or drain electrodes, 2-bit information can be stored.

However, since the selector line SL to which the drain electrode of the memory cell MC is connected and the sub bit line SBL to which the source electrode is connected are completely distinguished, the memory array circuit cannot be adapted to the memory element corresponding to two bits.

SUMMARY OF THE INVENTION The present invention provides a memory array circuit that corresponds to a nonvolatile memory device that stores two bits of data in one memory cell, and that enables a high speed read operation.

The memory array circuit of the present invention includes a plurality of word lines arranged in parallel, a plurality of sub bit lines arranged in parallel to the word line, a main bit line provided for each of two adjacent adjacent bit lines, the word line and the Sub-bits provided at each intersection of the sub-bit lines, the control electrode is connected to the word line at the intersection, the first electrode is connected to the sub-bit line at the intersection, and the second electrode is adjacent to the sub-bit line. A nonvolatile memory cell connected to a line and capable of reading and writing two bits of information by changing a direction of a voltage applied between the first and second electrodes when selected by the word line, and one end of the sub bit line; A drain selector disposed between the common power supplies and connecting the sub bit line to the common power supply when a drain selection signal is provided; the other end of the sub bit line and the main A source selector provided between the bit lines and connecting the sub bit line to the main bit line when a source selection signal is applied; and a fourth n (where n is an integer of 0 or more) in the drain selector; First, second, third, and fourth drain select lines for providing the drain select signal to each of the first, fourth n + 2th, and fourth n + 3th drain selectors, and an even number within the source selector; And first and second source selection lines for imparting the source selection signal to each odd-numbered source selector.

When the number of memory cells to be inserted into two selected memory cells is m, n sets of sub bit lines arranged in parallel to the word line and paired with 2 m adjacent to each other, and adjacent to the sub bit lines. 2n main bit lines are installed every m. And a second mi in the drain selector provided between one end of each sub bit line and the common power source and connecting the sub bit line to the common power source (where i is an integer of 0 to n-1); The first, second, ..., and second m drain selection lines for providing a drain selection signal are respectively provided in the ... and second m (i + 1) -1th drain selectors. Further, the mj (where j is an integer of 0 to 2n-1) in the source selector which is provided between the other end of each sub bit line and the corresponding main bit line, and connects the sub bit line to the main bit line. In each of the first, ..., and m-th (j + 1) -1th source selectors, first, second, ..., and m-th source select lines for providing the source select signal are provided. do.

Example 1

1 is a configuration diagram of a memory array circuit according to the first embodiment of the present invention.

This memory array circuit has a plurality of subblocks (SUBBLK) 20 (only one is shown in the figure) and one multiplexer (MPX) 30. Each subblock 20 includes a plurality of word lines WLi (i = 0, 1, ...) arranged in parallel and a plurality of sub bit lines SBLj (j = 0, arranged in parallel to and intersect with these word lines WLi. 1, ...)

At each intersection of the word line WLi and the sub bit line SBLj, the memory cells MCj (j = 0, 1, ...) are provided (however, only the memory cells corresponding to the word lines WLO are shown in the figure). As shown in Fig. 4, each memory cell MCj forms a memory functional body on the left and right side wall portions of the gate electrode (control electrode), and the left and right diffusion regions formed corresponding to the two memory functional bodies are respectively drain or source electrodes. Is a nonvolatile memory element corresponding to two bits which is used as a first electrode and a second electrode that can be switched to use. The gate electrode of the memory cell MCj is connected to a corresponding word line WLi, and the first and second electrodes of this memory cell MCj are connected to adjacent sub bit lines SBLj and SBLj + 1, respectively.

One end of the sub bit line SBLj (upper side in the drawing) is connected to the common power supply line CDV via a drain selector DSj composed of a switching transistor. Of the drain selectors DSj, the gate of the 4n (n = 0, 1, 2, ...) th drain selector DSj is commonly connected to the drain select line DSA, and the gate of the 4n + 1th drain selector DSj is the drain select line. Common connection to DSB. The gate of the 4n + 2th drain selector DSj is commonly connected to the drain select line DSC, and the gate of the 4n + 3rd drain selector DSj is commonly connected to the drain select line DSD.

The other end of the sub bit line SBLj + 1 (lower side in the drawing) is connected to the corresponding main bit line MBL via a source selector SSj composed of a switching transistor. That is, adjacent odd-numbered and even-numbered sub-bit lines SBL2n + 1 and SBL2n + 2 (for example, SBL1, SBL2) pass through source selectors SS2n and SS2n + 1 (in this case, SS0, SS1), respectively. It is connected to the main bit line MBLn (MBL0 in this case). The gates of the even-numbered source selector SS2n are commonly connected to the source select line SSE, and the gates of the odd-numbered source selector SS2n + 1 are commonly connected to the source select line SSO. At this time, a plurality of subblocks, such as this subblock 20, are connected in parallel to the main bit lines MBL0, MBL1, ....

The main bit lines MBL0, MBL1, ... are connected to the data lines DL0, DL1 via the multiplexer 30. The multiplexer 30 selects two adjacent main bit lines MBL in accordance with the selection signals Y0, Y1, ..., and connects them to the data lines DL0, DL1. The sense amplifiers SA0 and SA1 are connected to the data lines DL0 and DL1, respectively, and a data input circuit (not shown) and the like are connected. The sense amplifiers SA0 and SA1 read the stored contents of the memory cell MC by detecting the presence or absence of a current flowing through the selected memory cell MC to the ground potential.

At this time, although not shown in FIG. 1, the selection signal for the source selection line SSE, the SSO and the drain selection lines DSA to DSD, the driving signal for the word line WLi, and the selection signal Yi for the multiplexer 30 are addressed by an address decoder. Obtained by decoding the signal. For example, selection signals for the source selection lines SSE and SSO for selecting the subblock 20 are obtained by decoding the upper digits of the address signal. Further, by decoding the lower digits of the address signal, the selection signal Yi for the multiplexer 30 is obtained. Further, by decoding the middle digits of the address signal, a drive signal for the word line WLi and a selection signal for the drain selection lines DSA to DSD are obtained.

FIG. 5 is a diagram illustrating a state when the memory cells MC4 and MC7 are selected in FIG. 1, in which the thick line represents the selected drain select line DSA, the word line WL0, the source select line SSE, and the select signal Y3, the selected memory cells MC4, The path of the current flowing through MC7 is shown.

As shown in Fig. 5, by setting the source select line SSE and the select signal Y3 to " H ", the sub bit lines SBL5 and SBL7 are connected to the data lines DL0 and DL1 via the main bit lines MBL2 and MBL3, respectively. By setting the word line WL0 and the drain select line DSA to "H", the path from the common power supply line CDV to the drain bit line DSL5 through the drain selector DS4, the negative bit line SB4, and the memory cell MC4, and the drain selector DS8, the negative bit line A path from SB8 and memory cell MC7 to sub bit line SBL7 is configured.

Thus, the electrode on the left side of the memory cell MC4 is connected to the common power supply line CDV, and the electrode on the right side is connected to the data line DL0. On the other hand, the electrode on the right side of the memory cell MC7 is connected to the common power supply line CDV, and the electrode on the left side is connected to the data line DL1.

Therefore, when 5 V is applied to the common power supply line CDV and word line WL0, and the data lines DL0 and DL1 are set to 0 V, inputs can be made to the memory functional body on the left side of the memory cell MC4 and the memory functional body on the right side of the memory cell MC7. have.

Further, when 2V and 1.8V are applied to the word line WL0 and the common power supply line CDV, respectively, and the sense amplifiers SA0 and SA1 are operated, the memory functional body on the right side of the memory cell MC4 and the memory functional body on the left side of the memory cell MC7 are stored. The contents can be read.

In this read operation, the read path is sandwiched between the memory cells MC5 and MC6 in the middle in accordance with the selected memory cells MC4 and MC7, and the sub bit lines SBL5 and SBL7 used for reading are placed inside these memory cells MC4 and MC7. It is located. Therefore, the main parasitic capacitance components other than the read paths such as the sub bit lines SBL5 and SBL7 and the main bit lines MBL2 and MBL3 are only the sub bit lines SBL6 and the memory cells connected to the sub bit lines SBL6. As a result, the parasitic capacitance generated in the read path is limited to the region sandwiched by the selected memory cells MC4 and MC7, similarly to the memory array circuit of FIG. 2, whereby the parasitic capacitance becomes very small, thereby enabling a high speed read operation.

FIG. 6 is a diagram illustrating a state when the memory cells MC7 and MC10 are selected in FIG. 1, in which the thick line represents the selected drain select line DSD, the word line WL0, the source select line SSO, and the select signal Y3 and the selected memory cells MC7 and MC10. The path of the current flowing in the flow path is shown. Also in FIG. 6, the read path is sandwiched between the memory cells MC8 and MC9 in the middle of the selected memory cells MC7 and MC10, and the sub bit lines SBL8 and SBL10 used for reading are placed inside these memory cells MC7 and MC10. It is located. Therefore, the parasitic capacitance becomes very small and a high speed read operation is possible.

6, the direction of the current flowing through the memory cell MC7 is opposite to the current flowing through the memory cell MC7 selected in FIG. 5. As a result, the stored contents of the memory functional body on the right side of the memory cell MC7 can be read. In the case of an input operation, input can be made to the memory functional body on the left side of the memory cell MC7.

As described above, the memory array circuit of the first embodiment is configured so that the drain selector DS and the source selector SS are provided across each sub bit line SBLj, and the connection between the common power supply line CDV and the main bit line MBL can be changed. . As a result, the first and second electrodes of the memory cells MC connected to the adjacent sub bit lines SBLj and SBLj + 1 can be switched between the source electrode and the drain electrode, or the drain electrode and the source electrode. Can correspond to a nonvolatile memory device that stores two bits of data.

In addition, according to the selected two memory cells MC, since the sub bit line SBL for reading is sandwiched, there is an advantage that the parasitic capacitance of the read path is reduced and a high speed read operation is possible.

[Example 2]

7 is a configuration diagram of a memory array circuit according to the second embodiment of the present invention.

This memory array circuit has a plurality of subblocks 20A and one multiplexer 30 similarly to the memory array circuit of FIG. 1. Each subblock 20A includes a plurality of word lines WLi (i = 0, 1, ...) arranged in parallel, and a plurality of sub bit lines SBLj (j = 0 arranged in parallel with and intersecting these word lines WLi. , 1, ...) At each intersection of the word line WLi and the sub bit line SBLj, the memory cell MCj as shown in Fig. 1 is provided, and the gate electrode of the memory cell MCj is connected to the word line WLi. The first and second electrodes of the memory cell MCj are connected to the negative bit lines SBLj and SBLj + 1, respectively. One end of the sub bit line SBLj is connected to the common power supply line CDV via the drain selector DSj. The configuration so far is the same as the memory array circuit of FIG.

On the other hand, in the drain selector DSj, the gate of the 6n (n = 0, 1, 2, ...) th drain selector is commonly connected to the drain select line DSA. Similarly, the gates of the 6n + 1, 6n + 2, 6n + 3, 6n + 4, and 6n + 5th drain selectors DS are commonly connected to the drain select lines DSB, DSC, DSD, DSE, and DSF, respectively.

The other end of the sub bit line SBLj + 1 is connected to the corresponding main bit line MBL via the source selector SSj. That is, three adjacent sub bit lines SBL3n + 1, SBL3n + 2, and SBL3n + 3 are connected to the main bit line MBLn via source selectors SS3n, SS3n + 1, and SS3n + 2, respectively. The gates of the source selectors SS3n, SS3n + 1, and SS3n + 2 are commonly connected to the source selector SSL, SSM, and SSN, respectively.

At this time, a plurality of subblocks, such as the subblock 20A, are connected in parallel to the main bit lines MBL0, MBL1, ..., and the main bit lines MBL0, MBL1, ... are connected via the multiplexer 30 to the data. 1 is connected to the lines DL0 and DL1, and the sense amplifiers SA0, SA1 and the data input circuit are connected to the data lines DL0 and DL1, respectively.

The thick line in Fig. 7 shows the current path when the memory cells MC3 and MC7 are uniquely selected by selecting the drain select line DSC, DSD, word line WL0, source select line SSL, and selection signal Y1 of the multiplexer 30. Indicates. Thus, three memory cells MC4 to MC6 are sandwiched between the two selected memory cells MC3 and MC7, and the sub bit lines SBL4 and SBL7 serving as current paths are located inside the selected two memory cells.

In this case, paying attention to the memory cell MC7, the sub bit line SBL8 becomes a drain line, the sub bit line SBL7 becomes a source line, and current flows through the memory cell MC7 from right to left in the figure.

On the other hand, when a current flows from left to right in the memory cell MC7, the drain select line DSA, DSB, word line WL0, source select line SSM, and select signal Y2 of the multiplexer 30 are selected. Accordingly, memory cells MC7 and MC11 are uniquely selected. For the memory cell MC7, the sub bit line SBL7 becomes a drain line, the sub bit line SBL8 becomes a source line, and current flows through the memory cell MC7 from left to right in the figure.

Also in this case, three memory cells MC8 to MC10 are sandwiched between two selected memory cells MC7 and MC11, and the sub bit lines SBL8 and SBL11 serving as current paths are located inside the selected two memory cells. .

As described above, in the memory array circuit 20A of the second embodiment, the drain selector DS and the source selector SS are provided across each of the sub bit lines SBLj so that the connection between the common power supply line CDV and the main bit line MBL can be changed. Consists of. As a result, it is possible to switch the first and second electrodes of the memory cell MC into a source electrode and a drain electrode, or a drain electrode and a source electrode, and to a nonvolatile memory device that stores two bits of data in one memory cell. Can match.

Further, according to the selected two memory cells MC, since the sub bit line SBL for reading is sandwiched, there is an advantage that the parasitic capacitance of the read path is reduced and the high speed read operation is possible. At this time, compared with the memory array circuit of Fig. 1, since the number of sub bit lines inserted into the sub bit line SBL for reading increases from one to two, the parasitic capacitance slightly increases, but the number of intervening memory cells MC is two. Since it increases to three, the leakage current can be reduced.

[Example 3]

8 is a configuration diagram of a memory array circuit according to the third embodiment of the present invention.

The memory array circuit has a plurality of subblocks 20B and one multiplexer 30, like the memory array circuit of FIG. Each subblock 20B includes a plurality of word lines WLi arranged in parallel (i = 0, 1, ..., but only WL0 is described in the drawing), and a plurality of word lines WLi arranged in parallel with each other. It has a negative bit line SBLj (j = 0, 1, ...). At each intersection of the word line WLi and the sub bit line SBLj, the memory cell MCj as shown in Fig. 1 is provided, and the gate electrode of the memory cell MCj is connected to the word line WLi. The first and second electrodes of the memory cell MCj are connected to the negative bit lines SBLj and SBLj + 1, respectively. One end of the sub bit line SBLj is connected to the common power supply line CDV via the drain selector DSj. The configuration so far is the same as the memory array circuit of FIG.

On the other hand, among the drain selectors DSj, the gate of the 8n (n = 0, 1, 2, ...) th drain selector is commonly connected to the drain select line DSA. Similarly, the gates of the drain selectors DS of the 8n + 1, 8n + 2, 8n + 3, 8n + 4, 8n + 5, 8n + 6, and 8n + 7th drains are the drain select lines DSB, DSC, DSD, DSE, and DSF, respectively. It is commonly connected to DSG, DSH.

The other end of the sub bit line SBLj + 1 is connected to the corresponding main bit line MBL via the source selector SSj. That is, the four adjacent sub bit lines SBL4n + 1, SBL4n + 2, SBL4n + 3, and SBL4n + 4 are connected to the main bit line MBLn via source selectors SS4n, SS4n + 1, SS4n + 2, and SS4n + 3, respectively. It is. The gates of the source selectors SS4n, SS4n + 1, SS4n + 2, and SS4n + 3 are commonly connected to the source select lines SSK, SSL, SSM, and SSN, respectively.

At this time, a plurality of subblocks, such as the subblock 20B, are connected in parallel to the main bit lines MBL0, MBL1, ..., and the main bit lines MBL0, MBL1, ... are connected to the data line through the multiplexer 30. 1 is connected to DL0 and DL1, and the sense amplifiers SA0, SA1, a data input circuit, and the like are connected to the data lines DLO and DL1, respectively.

In Fig. 8, the thick lines indicate the currents when the memory cells MC4 and MC9 are uniquely selected by selecting the drain select line DSC, DSE, word line WLO, the source select line SSK, and the selection signal Y1 of the multiplexer 30. It shows the route. Thus, four memory cells MC5 to MC8 are sandwiched between the two selected memory cells MC4 and MC9, and the sub bit lines SBL5 and SBL8 serving as current paths are located inside the selected two memory cells.

In this case, paying attention to the memory cell MC9, the sub bit line SBL9 becomes a drain line, the sub bit line SBL8 becomes a source line, and current flows through the memory cell MC9 from right to left in the figure. On the other hand, when a current flows from left to right in the memory cell MC9, the drain select line DSB, DSH, word line WL0, source select line SSL, and select signal Y2 of the multiplexer 30 are selected. Accordingly, memory cells MC9 and MC14 are uniquely selected. For the memory cell MC9, the sub bit line SBL8 becomes a drain line, the sub bit line SBL9 becomes a source line, and current flows from the left side to the right side of the figure in the memory cell MC9.

As described above, the memory array circuit of the third embodiment can correspond to the nonvolatile memory device that stores two bits of data in one memory cell as in the first and second embodiments, and the parasitic capacitance of the read path is reduced. There is an advantage that a high speed read operation is possible. At this time, compared with the memory array circuit of FIG. 7, since the number of sub bit lines inserted into the sub bit line SBL for reading increases from 2 to 3, the parasitic capacitance increases, but the number of intervening memory cells MC is increased from 3 to Since the number is increased to four, the leakage current can be further reduced.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.

(1) A configuration in which two, three, and four memory cells are sandwiched between two selected memory cells has been described. However, a configuration in which any number of memory cells can be inserted in the same manner.

That is, when m memory cells are fitted, n pairs of sub-pit lines are formed by pairing 2 m adjacent to each other, and one main bit line is provided for every m adjacent m sub-bit lines. Further, a drain selector controlled by a drain select signal is provided between one end of each sub bit line and a common power supply, and a source selector controlled by a source select signal is provided between the other end of each sub bit line and the corresponding main bit line. do.

The drain selectors are respectively selected from the drain selectors of the second mi (where i is an integer of 0 to n-1), the second mi + 1 th, ..., and the second m (i + 1) -1 th. First, second, ... and second m drain select lines for providing a signal are provided. Further, a source selection signal is supplied to each source selector of the mj's (where j is an integer of 0 to 2n-1), mj + 1's, ..., and m's (j + 1) -1's. Install first, second, ... and m-th source select lines to give. This results in a memory array circuit having a configuration in which any m memory cells are sandwiched.

(2) Although the circuit configuration of supplying the drain voltage of the memory cell to the common power supply line and grounding the source electrode of the memory cell through the sense amplifier has been described, the circuit configuration of grounding the common power supply line and supplying the drain voltage from the sense amplifier is described. It is also possible.

In the present invention, one end of the sub bit line is connected to the common power supply via the drain selector, and the other end of the sub bit line is connected to the main bit line through the source selector. Therefore, by changing the drain select signal for the drain selector and the source select signal for the source selector, the sub bit line can be switched to the drain line or the source line. This enables reading and writing of memory cells that store two bits of data in one memory cell. Also, select two of the memory cells connected to the selected word line, and select the drain selector and the source selector so that the selected two memory cells sandwich the sub-bits from these memory cells to the main bit line. By providing a drain selection signal and a source selection signal, the parasitic capacitance is reduced, thereby enabling the read operation at a high speed.

Claims (3)

A plurality of word lines arranged in parallel, A plurality of sub bit lines arranged parallel to and intersecting the word lines; A main bit line provided every two adjacent ones of the sub bit line; Provided at each intersection of the word line and the sub bit line, a control electrode is connected to the word line at the intersection, a first electrode is connected to the sub bit line at the intersection, and a second electrode is connected to the sub bit line. A nonvolatile memory cell connected to a sub bit line adjacent to the non-volatile memory cell that can read and write two bits of information by changing the direction of a voltage applied between the first and second electrodes when selected by the word line; A drain selector provided between one end of said sub bit line and a common power supply, said drain selector connecting said sub bit line to said common power supply when a drain select signal is applied; A source selector provided between the other end of the sub bit line and the main bit line, the source selector connecting the sub bit line to the main bit line when a source selection signal is applied; A first selector for providing the drain select signal to each of the drain selectors of a fourth nth (n is an integer greater than or equal to 0), a fourth n + 1 th, a fourth n + 2 th and a fourth n + 3 th of the drain selectors; Second, third and fourth drain select lines, And first and second source select lines for providing the source select signal to each of even and odd source selectors among the source selectors. A plurality of word lines arranged in parallel, N pairs (but m and n are plural) negative bit lines which are arranged in parallel to and intersect the word line and make a pair of adjacent 2 m pieces; 2n main bit lines provided for every m adjacent to the sub bit lines; Provided at each intersection of the word line and the sub bit line, a control electrode is connected to the word line at the intersection, a first electrode is connected to the sub bit line at the intersection, and a second electrode is connected to the sub bit line. A nonvolatile memory cell connected to a sub bit line adjacent to the non-volatile memory cell capable of reading and writing two bits of information by changing a direction of a voltage applied between the first and second electrodes when selected by the word line; A drain selector provided between one end of said sub bit line and a common power supply, said drain selector connecting said sub bit line to said common power supply when a drain select signal is applied; A source selector provided between the other end of the sub bit line and the main bit line corresponding to the sub bit line, the source selector connecting the sub bit line to the main bit line when a source selection signal is applied; The drain selector is selected to each of the drain selectors of the second mi (where i is an integer of 0 to n-1), the second mi + 1 th, ..., and the second m (i + 1) -1 th. First, second, ... and second m drain select lines for imparting a signal, The source selection signal to each of the source selectors of mj (where j is an integer of 0 to 2n-1), mj + 1, ..., and m (j + 1) -1; And a first source selection line, a second source selection line, a second source selection line, and a second source selection line. The method according to claim 1 or 2, The drain select signal and the source select signal may select two of the memory cells connected to the selected word line, and the sub select signal and the source select signal may be selected by the selected two memory cells until they reach the main bit line from these memory cells. And the drain selector and the source selector are selected so that a bit line is fitted in the memory array circuit.

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