CN102129884A - Method and device for increasing programming efficiency by utilizing dynamic bit line switching - Google Patents
Method and device for increasing programming efficiency by utilizing dynamic bit line switching Download PDFInfo
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- CN102129884A CN102129884A CN2010100046454A CN201010004645A CN102129884A CN 102129884 A CN102129884 A CN 102129884A CN 2010100046454 A CN2010100046454 A CN 2010100046454A CN 201010004645 A CN201010004645 A CN 201010004645A CN 102129884 A CN102129884 A CN 102129884A
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Abstract
The invention discloses a method and device for increasing programming efficiency by utilizing dynamic bit line switching. The method comprises the step of dynamically accessing an induction amplifier to a storage unit to be programmed through bit line switching. By means of the method, the number of the storage unit to be programmed simultaneously can be increased, thus the resources of the induction amplifier can be utilized to a most proper extent.
Description
Technical field
Embodiments of the invention are about semiconductor memory, also furthermore, are the methods about the programming semiconductor storer.
Background technology
Charge capturing memory also is called flash memory, applied to widely electronic installation in, such as camera, mobile phone, personal digital assistant etc., modulator-demodular unit, mobile computer etc.Charge capturing memory can be with relatively large data storing in little space.Be stored in the data in the charge capturing memory, supply with, still can keep the integrality of its data even if lack electric power.
By adjusting critical voltage, storage unit that can the programmed charges capturing memory.Then can finish with the present class of detecting by the storage unit reading of data by applying reference voltage.Be programmed for one of two different critical voltages,, be commonly referred to single-order storage unit (SLC) to store the storage unit of one information.For example, when storage unit can be supported the different critical class of four or eight, this storage unit can store two or four data bit.This kind can store the data more than a position in single memory cell, be called multi-level cell memory (MLC).
Compared to merely reading or write storage unit, the time of programmed charges capturing storage unit is relatively large.In the application that relates to electronic installation, data need be stored (for example: in digital camera) as soon as possible, and the tediously long programming time may influence the operating efficiency of storage unit, and then the overall efficiency of impairment device.
Therefore produce the demand that a kind of hope can be lowered the programming time of charge capturing memory.
Summary of the invention
The objective of the invention is to propose the scheme of head it off, a kind of method and apparatus that bit line dynamically switches increases programming efficiency that utilizes is provided for this reason.
For reaching described purpose, the present invention proposes a kind of method that bit line dynamically switches increases programming efficiency of utilizing, provide a charge capturing storage unit (CTMC) array and a plurality of induction amplifier configuration for this array is programmed, and the data that reception is about to be programmed enter in this array.The method also comprises a class that is about to be programmed according to more than first storage unit in this array of data decimation, and uses these a plurality of induction amplifiers that more than second storage unit in this array is programmed to the class that this is chosen then as far as possible.This array can be single-order or multistage charge capturing storage unit (CTMC), and can use the whole of these a plurality of induction amplifiers.
For reaching described purpose, the present invention proposes a kind of memory storage, comprise a charge capturing storage unit (CTMC) array, a plurality of induction amplifier configurations are for to programme to this array that is coupled, and multiple bit lines is arranged to these a plurality of induction amplifiers of connection to a plurality of storage unit; And one switch the array group attitude and maximize with use that will this a plurality of induction amplifiers when the programming for the connection of switching this bit line.According to another embodiment, this array can comprise the multiple row of this storage unit, and each row in this multiple row comprise a plurality of characters, and each character comprises a plurality of storage unit.
For reaching described purpose, the present invention proposes a kind of method that bit line dynamically switches increases programming efficiency of utilizing, and comprises: provide a charge capturing storage unit (CTMC) array and a plurality of induction amplifier configuration for this array is programmed; The multistage data that reception is about to be programmed enter in a charge capturing storage unit (CTMC) array, this array comprises multiple bit lines and is applicable to storage unit in this array of addressing, a plurality of induction amplifiers are applicable to programmes to this storage unit, and a switching array is applicable to these a plurality of induction amplifiers of connection and a plurality of storage unit; Choose a programming class; Count being about to be programmed to this storage unit of choosing programming class; And choose programming class to this according to a big or small memory cells of these a plurality of induction amplifiers.
Beneficial effect of the present invention: the programming time and increase programming operation efficient that can lower charge capturing memory.
Any feature described herein or characteristics combination all are positioned within the category of the present invention, and the literal in getting rid of this kind combination and instructions, embodiment reach and know this skill personage's the inconsistent feature of knowledge.Be explanatory memorandum the present invention, some purpose, advantage and new feature are unexposed in this.Certainly, being interpreted as all purposes of wind sheltering, advantage or feature all should be contained in the specific embodiment of the present invention.Following embodiment and claim will illustrate additional advantage of the present invention and purpose.
Description of drawings
The critical voltage that Fig. 1 illustrates single-order charge capturing storage unit (CTMC) distributes.
Fig. 2 is a process flow diagram, illustrates the prior art of programming single-order CTMC.
Fig. 3 prognostic chart, it predicts that the critical voltage among the multistage CTMC distributes.
Fig. 4 is a process flow diagram, illustrates the prior art of programming multi-level CTMC array.
Fig. 5 A and Fig. 5 B are chart, show the prior art of the array of programming multi-level CTMC.
Fig. 6 is a chart, shows according to a kind of embodiment of the present invention the method for programming multi-level CTMC array.
Fig. 7 is a process flow diagram, and summary is according to a kind of method of a kind of embodiment programming multi-level CTMC array of the present invention.
Fig. 8 A and 8B are process flow diagram, describe the required step of method of Fig. 7 in detail.
Fig. 9 is a calcspar, and it is the device of embodiments of the invention, and this device is according to the present invention programme single-order or multistage CTMC.
The synoptic diagram of Figure 10 for simplifying, it is the device of embodiments of the invention, this device can be according to the present invention programme single-order or multistage CTMC.
[main element symbol description]
110,115,125,200,205: critical voltage distributes
120,210,220,230: program verification class
Class distributed in 215: the 1
Class distributed in 225: the 2
Class distributed in 235: the 3
460: switching array
500: array
The 505:X code translator
The 510:Y code translator
515: induction amplifier
520: static RAM
525: record programming number square
530: address decoder
535: character decoder
540: bit line decoder
545: bit decoder
555: latch circuit
Embodiment
The preferred embodiment of the present invention of following foundation and description of drawings the present invention.Within the bounds of possibility, identical or similar elements all adopts the components identical symbol in accompanying drawing or instructions.Because accompanying drawing through simplifying, is not an accurate dimensions therefore all.In other words, it is only as the example of the multiple purpose of the present invention, and is equal proportion in the embodiment of some (but non-all).According to some embodiment, the structure in these accompanying drawings is an equal proportion, and is then non-so certain in other enforcement with spline structure.According to specific purpose of the present invention, same component symbol is meant the similar element that maybe can simulate in the accompanying drawing, but is not to be identical group or element.According to another purpose, use the components identical symbol will refer to be identical or essence in the accompanying drawing, and/or have assembly, the element of identical function.The following listed direction speech of explanation, such as top, bottom, left and right, upper and lower, be higher than, be lower than, be positioned at all usefulness of just illustrating of supplier only of below, rear, the place ahead, it is the corresponding accompanying drawing of reference simultaneously.In any case these direction speech all should not be regarded as any restriction of the present invention.
Some embodiment though following disclosed content is touched upon, these embodiment only for the example of explanation, do not limit category of the present invention.Adopt the purpose of these exemplary embodiment, at the embodiment that comprises its all variation, adjustment and equate; The variation of these a little embodiment all can fall into spirit of the present invention and category, promptly defines as claim.Should understand method step described herein and structure simultaneously is not the structure disclosed herein and the complete description of process step.The present invention may be in conjunction with multiple method of the prior art with co-operate, and this instructions only is disclosed as and understands the necessary prior art step of the present invention.The present invention semiconductor device with and the field of method have industry applications.Yet required for illustrating, the following description is about memory storage and a kind of relevant method.
The programming of charge capturing storage unit can utilize the storage unit that applies program voltage to finish, and it can produce the electronics with enough kinetic energy, and is regional with a part that reaches transistor gate, and is trapped in this, in order to influence the critical voltage of storage unit.Single-order charge capturing storage unit (CTMC) is programmed for one of two programming classes.Fig. 1 illustrates the critical voltage V of single-order CTMC
tDistribution plan.The V of distribution 110 and 115
tValue is little than the PV 120 of program verification class, and it can be described as class 0; The V of distribution 125
tValue is greater than the PV of program verification class 120, and it can be described as class 1.For example, program verification (PV) value can be between 3V to 5V.
Single-order CTMC with class 0 can be described as " programming " or " erasing ", and the single-order CTMC with class 1 can be described as " programming ".In other words, single-order CTMC can be a kind of in the two states: programmed or not programming.Therefore, the single-order CTMC that erases is programmed into class 0 need not anyly move, and should belong to obvious reason.
Method commonly used distributes for the critical voltage with class 0 and data value " 1 " is connected, and data value " 0 " then can distribute with the critical voltage of class 1 and link.In fact, programming single-order CTMC may comprise to class 1 and applies at least one program bias potential pulse to storage unit, carries out the sensing step then, whether has reached the class of program verification (PV) to learn this transistorized critical voltage.Can repeat above-mentioned steps, till the programming class that reaches program verification (PV).When carrying out the sensing step, can utilize induction amplifier (SA), it also can have the ability that applies program voltage, and this induction amplifier (SA) can be skipped when applying program voltage.When understand induction amplifier (SA) only the program verification in programming process (PV) step be used, in this instructions, will be described as induction amplifier (SA) " programming " storage unit.
For example, CTMC can be set at the device of 2K byte, and according to a kind of preferred embodiment of the present invention, it can comprise the byte that adds up to 2 * 1024=2048 or the position of 2048 * 8=16384.According to another embodiment, the row of the configurable one-tenth of CTMC device 8K byte, each row comprises four 2K byte programmed groups.A 2K byte programmed groups in the CTMC device (for example, 8K byte one row 1/4th) can be considered 128 128 " character ".That is, a 8K byte stream can comprise four 2K byte programmed groups, and each programmed groups comprises 128 characters, and each character comprises 128 storage unit, and each storage unit stores a data bit in these CTMC row.
Use the method for prior art programming single-order CTMC perhaps to comprise and choose row, choose the programmed groups in these row, choose the character in this programmed groups again.The some of one group of group that comprises 128 induction amplifiers writes to selected character according to 128 sample attitude.That is, for the position (for example, being set at data " 0 ") that is about in the character position be programmed, its bit line is connected to the correspondence position in the selected character, and it may have the corresponding program voltage that induction amplifier applied, in order to finish the programming of selected character.
Fig. 2 is a process flow diagram, illustrates the method for utilizing prior art programming single-order CTMC.In step 150, receive the data of 2K byte, it will be programmed to the 2K block of 2K CTMC array or big CTMC array.The sequence of the arrangement of this byte can be understood that first 128 will be programmed to first line (for example: character), and second 128 family will be programmed to second line, below analogize.This method continues at first character of selecting in the step 155 in the array.In step 160, select the part of 128 induction amplifier groups, wherein each induction amplifier all is connected to the storage unit that is about to be programmed in the character of selecting via a bit line.The data of first 128 groups can be used for starting each 128 induction amplifiers corresponding to data value " 0 ", and perhaps in first 128 groups, the CTMC that will be arranged in first character is programmed to class " 1 ", i.e. step 165.
Second character in the array (promptly in second line) is selected in step 170, and in second 128 group each 128 induction amplifiers that correspond to data value " 0 " in step 175 selected be activated.This startup is for setting to class 1 corresponding to the CTMC of second character of data value " 0 " in second character line in step 180.This method continues to carry out, and is selected in step 185 up to the 128th (at last) character, and then suitable induction amplifier can be activated according to " 0 " data bit in step 190, and the 128th character is programmed in step 195.
Should understand understanding, promptly in the employed prior art as Fig. 2, even if all just successes when carrying out for the first time of programming each time, the required program cycles fixed number of the whole array of programming is at 128 times.In other words, for example, both make in each character 127 of the inside, 128 positions need not be programmed, that is both made and in each character, only have one " 0 " position to be programmed, still needed to carry out minimum 128 times program cycles.Really, if the data that will be programmed distribute randomly, the data that then should be expected for about half are " 0 ", and the data of about half are " 1 ".Therefore, all need use 128 exclusive induction amplifiers during each program cycles, wherein approximately half is not used, and promptly relevant with data value " 1 " not needing programmed.Therefore in the prior art that Fig. 2 illustrates, the efficient of programming single-order CTMC is about 50%.
Similar problem also exists in multistage CTMC.For example, multistage CTMC may illustrate as Fig. 3, is programmable in three classes.As previously mentioned, class's 0 critical voltage distribution 200 or 205 may correspond to a multistage CTMC who does not programme, simultaneously, for example, may be relevant with a pair of two bit data value " 11 ".In the quadravalence embodiment that Fig. 3 illustrated, the distribution 215 of the 1st class may correspond to a pair of two bit data value " 01 ", and may have critical voltage value V
t, it is greater than first PV1210 of program verification class but less than second PV2220 of program verification class.Similarly, the distribution 225 of the 2nd class may correspond to a pair of two bit data value " 00 ", and may have critical voltage value V
t, it is greater than second PV2220 of program verification class but less than the 3rd PV3230 of program verification class.Distribution 235 scopes of the 3rd class may be greater than PV3230, and may correspond to a pair of data value " 10 ".
Fig. 4 illustrates the process flow diagram of the process step of programming multi-level CTMC in the prior art.In being similar to the described flow process of Fig. 2, step 250 receives the data of 4096 bytes, and it is corresponding to 4096 * 8=32,768 data bit.As previously mentioned, these data values can correspond to one of four programming classes, i.e. class 0, class 1, class 2, class 3; Wherein, class 0 corresponds to the multistage CTMC critical voltage distribution of not programming or erasing.Therefore, each CTMC can store two data, and thus 32,768/2=16,384 CTMC are enough to store 4096 data bytes.By 3 rank CTMC arrays are set in 128 lines and 128 stringers, sum 128 * 128=16 is promptly arranged, 384 CTMC can be programmed.
In this embodiment, finishing of programming is to be applicable to the individual characters of selecting in regular turn able to programme by 128 induction amplifiers, and it is to utilize the character line that starts corresponding to line in the CTMC array.The programming data value " 11 " that corresponds to class 0 then need not start.Be the data of programming class 1, class 2 and class 3, the prior art described in Fig. 4 in step 255 128 induction amplifiers of configuration with programming class 3 data, and in step 260 an initial character count, i is to 1.Therefore, in step 265,128 induction amplifiers that correspond to class's 3 data are addressed, and correspondence position can be programmed to class 3 in i character.In step 270, this i value and 128 relatively, if i＜128, then i increases progressively 1 in step 275, and character late " 01 " position in step 265, be programmed to class 3.Repeats this 265/270/275 loop and be programmed all, and the method proceeds to flow process that step 280,285,290,295 and 300 is similar to class 3 with use to 128 character groups up to 3 of the classes of all 128 characters " 00 " be programmed to class 2.Similarly, the class of 128 character groups is 1 " 10 " programme in step 305,310,315,320 and 325.
Can similarly observe the multistage CTMC in programming of the prior art 3 rank (as described in Figure 4).Even the group of each 128 value data only comprises a class will being programmed 3, class 2 and class's 1 numerical value, one of each 128 storage unit character to the three programming class that programmes still needs 3 steps.In other words, can expect in 1/4th storage unit correspond to one of four kinds of required programming classes.Therefore, in any program cycles, on average have only 1/4th induction amplifier relevant with the programmed method that utilizes Fig. 4 prior art.In view of this, the efficient of the programmed method of this kind prior art is about 25%.
Fig. 5 A is a prognostic chart, and it predicts the situation that a 4K byte (as the 32768) programmed groups in the one 4 rank CTMC arrays utilizes prior art shown in Figure 4 to programme.This programmed groups, the part that it can comprise longer entity row in the array comprises for example, 16384 storage unit, be divided into 128 characters in this routine formula, each character comprises 128 storage unit, and two data bit of each cell stores.First character in this programmed groups comprise label be 0,1 ..., 127 storage unit, wherein storage unit 0,1 ..., 126,127 soon be programmed to individually, class 3, class 2 ..., class 1 and class 1.Comprise label like second character type in this programmed groups and be 0 to 127 storage unit, wherein storage unit 0 and 1 is programmed to class 1 and class 0 respectively, and storage unit 126,127 all is programmed to class 0.Continue in a similar fashion storage unit 0,1 in last character (the 128th) ..., 126,127 soon be programmed to individually, class 0, class 1 ..., class 2 and class 3.
The alternate embodiment of programmed groups is shown in Fig. 5 B among Fig. 5 A, and wherein each character in this programmed groups is represented by a dummy column of 128 * 128 arrays of virtual 4 rank storage unit.The situation of utilizing prior art shown in Figure 4 to programme, first character is selected, and any class 3 data in this character can be programmed, then can choose character 2, character 3 ..., class's 3 data in the character 128 programme.Afterwards, first character is selected, and 2 data of the class in this character can be programmed, and then choose character 2, character 3 ..., class's 2 data in the character 128 programme.At last, utilize same sequence that class's 1 data are programmed.The programmed method of this prior art is noticed once more when using 128 induction amplifiers, and needs 3 * 128=384 program cycles just can be finished the programming to this 4K byte programmed groups.
Fig. 6 lists the method flow diagram that carries out efficient program according to the present invention.Embodiment shown in the foundation, step 350 accepts to comprise a set of 4096 byte datas, and is with the aforementioned three rank CTMC arrays that are arranged to 16,384 storage unit of 128 * 128 kenels that are programmed to of inciting somebody to action, described as Fig. 5 A and Fig. 5 B.In the step 355, class's 3 data in only should gathering are selected, and these class's 3 data utilizations, any induction amplifier has storage unit corresponding to the delegation of virtual array among Fig. 5 B for example need be programmed to class 3, the mode of dynamic assignment bit line to 128 induction amplifier is to be programmed to class 3 simultaneously.Typically, therefore, 128 storage unit programming for the first time by after be programmed to class 3.Repeat this program and 128 storage unit are programmed at every turn, class's 3 data in all these set all dispose.Proceed to step 360 in flow process, repeat the data of above-mentioned steps, and in step 365, repeat data with programming class 1 with programming class 2.Know promptly that thus step as shown in Figure 6 can effectively utilize available induction amplifier,, can promote the programming efficiency of CTMC array simultaneously compared to prior art shown in Figure 4.
Fig. 7 is a process flow diagram, the step 355 of each induction amplifier in the method for its shows in detail Fig. 6.This detailed content starts from step 400, then in step 405 with to each induction amplifier (SAj, j=0,1 ... 127) individual class's 3 storage unit that will will be programmed of specific certain numeral (Nj) in the set of reception 4096 data bytes.A digital N3 is chosen for the { maximal value among the Nj}.That is, N3 soon need be programmed to the number of class's 3 data of one or more induction amplifiers of class 3 by have the maximum number storage unit corresponding to the delegation that arranges among Fig. 5 B.In step 410, N3 and 0 is compared, if N3 is greater than 0, represent at least one storage unit need be programmed to class 3, then bit line is switched according to class's 3 storage unit (if the words that have) of next needs by each induction amplifier programming in step 415.Utilize in all 128 induction amplifiers and have each that at least one storage unit need be programmed to class 3 this moment, will chosen storage unit programme in step 420 in step 415.Step 425 can be carried out program verification and whether be surpassed special value with the critical voltage of checking storage unit, for example is PV3 class 230 as shown in Figure 3.Look the result that step 425 detects, but if be necessary this programming of repeating step 420.N3 can deduct 1 in step 430, and this flow process can begin repetition from step 410, till N3 is no longer greater than 0, represents all classes 3 storage unit to be programmed all.After finishing, this flow process can stop in step 450.
Fig. 8 A is a prognostic chart, 16384 storage unit programmed groups among its prediction and Fig. 5 A in the identical one 4 rank CTMC arrays.This array switches array 460 it is applicable to that connecting each induction amplifier improves with any one corresponding stored unit in forming 128 characters of this programmed groups by increasing by one.Base area one program cycles is first execution in step 415 and 420 among Fig. 7 for example, shows being connected between some induction amplifier and the storage unit in the illustration icon.For example, induction amplifier SA0 is connected to (for example be about to programming) storage unit 0 in first character to class 3.Similarly, induction amplifier SA1 configuration is about to memory cells 1 to class 3, by that analogy for connecting in the three-character doctrine.Usually, each induction amplifier can configuration be the storage unit with the class 3 that programmes in some character of entity row, and it can be with the utilization maximization of these induction amplifiers.
Fig. 8 B illustrates Fig. 8 A again, and wherein each character in Fig. 8 A one entity row is the dummy column in 128 * 128 dummy memory cell array.In first program cycles, the illustrated bit line switching of step 415 in Fig. 7 can cause, and for example the 0th storage unit in the 1st character, the 1st storage unit in the 3rd character, the 126th storage unit in the 5th character and the 127th storage unit in the 8th character are programmed to class 3.Second program cycles is programmed to class 3 with the 0th storage unit in the 7th character, the 1st storage unit, the 126th storage unit in the 8th character and the 127th storage unit in the 8th character in the 4th character.All class's 3 storage unit that this flow process may continue in each induction amplifier all are programmed.Should note: finish class 3 programming required round-robin greatest measures (being the N3 among Fig. 7), identical with maximum class 3 Number of Storage Units in any stringer of array among Fig. 8 B.Class 2 can be programmed with similar mode with the storage unit of class 1.
Fig. 9 is the calcspar according to a kind of embodiment of the present invention, and it illustrates a device, and it is applicable to programming one single-order or multistage storage array.This embodiment comprises storage array 500, and it can be the array of CTMC storage unit; X code translator 505 can be used to select the line of array, Y code translator 510 applicable to the bit line of array programming and to read, and static RAM (SRAM) 520 its can be when programming the temporary transient input data DIN[n:0 that stores].At DIN[n:0] in, " n " can represent the figure place in the programming unit (for example programming unit of 128 characters of 8A among the figure).This embodiment also comprises one square 525 of " record programming number ", it can be each DIN[n:0] each induction amplifier in block and the address decoder 530 stores the number of characters that will be programmed to class 3, class 2 and class 1.It is X address, Y address and SRAM address that this address code translator 530 receptions one address is deciphered this receiver address then, and links up and deliver to respectively among X code translator 505, Y code translator 510 and the SRAM 520.That is, because programming data DIN[n:0] can move with this programming address, a bit line can be by data decoding is got.One bit line perhaps can be opened to programme according to the SRAM address switchover that is produced by address decoder 530.Comprise in this embodiment an induction amplifier 515 set be applicable to carry out program verification and/or reading of data to/store since then in the array 500.
According to an embodiment, the Y code translator comprises the bit line decoder YS of a bias voltage and the Y code translator YG (not being shown among Fig. 9) of a ground connection.As what described, induction amplifier is that the Qualify Phase in when programming uses and skips can apply high programming voltage again the time.This Y code translator 510 can configuration for according to Fig. 6 and the described mode of Fig. 7 so that the communication between a corresponding storage unit of choosing in the character with of induction amplifier (according to this induction amplifier) to be provided.
Figure 10 illustrates the details of Fig. 9 embodiment.This embodiment as illustrating, comprises address decoder 530, and it can receive a storage address and present X address storage array 500 so far, to choose the entity row of this array.This address code translator 530 also can present the bit line decoder 540 that a Y address to comprises character decoder 535 and bit decoder 545.This character decoder 535 can be chosen a character that is about to be programmed, and this bit decoder 545 can be chosen the storage unit that is about to be programmed in the selected character.Latch circuit 555 can switch the specific induction amplifier of bit line to of kinds of characters when programming operation.For example, in Fig. 8 A, induction amplifier 0 (SA0) is switched to first character when first class, 3 programming operations, and is switched to the 7th character (in Fig. 8 B) when second class, 3 programming steps.
Step by above embodiment and device embodiment can know how understanding reduces programming CTMC array required averaging time.With reference to Fig. 5 A and Fig. 5 B, and, suppose that SA8 is the induction amplifier that has the storage unit (for example being 50) that is about to be programmed number at most according to class's 3 data with reference to an example wherein.Suppose also that in addition SA79 is the induction amplifier with the Number of Storage Units (for example 45) that is about to be programmed to class 2 at most, SA101 then is the induction amplifier with the Number of Storage Units (for example 51) that is about to be programmed to class 1 at most.When employing elder generation that Fig. 4 illustrated and technical method, need 128 program cycles to come indivedual classes 3 storage unit of 128 lines in the programmed array.Similarly, need 128 program cycles programme other class 2 and class's 1 storage unit.Minimum program cycles adds up to 384.Even individual storage unit all successfully just is programmed after the one-time programming circulation, this lowest numeric still remains unchanged.Yet, programme according to the present invention, only need 50 program cycles to finish the programming of class 3,45 program cycles are finished the programming of class 2, and 51 program cycles are finished the programming of class 1.Program cycles according to utilization required for the present invention adds up to 146, and prior art as shown in Figure 4 then need be utilized 384 circulations at least, knows promptly that thus the present invention has significantly promoted the efficient of programming.
By aforementioned, the people of skilled can understand the method that the present invention presents and can be used for forming read-only memory device at integrated circuit, especially has the memory storage of single-order and multiple-rank arrangement.The foregoing description is only as the usefulness of example, and category of the present invention is not subjected to the restriction of these examples.Know those skilled in the art after knowing above stated specification, can under situation about not getting rid of mutually, finish variation or change according to disclosed embodiment of this invention easily.In addition, any combination, delete, replace or change be those skilled in the art that must be according to aforementioned invention and finishing easily.Therefore, the present invention is subject to previous embodiment, and should be defined with claim.
Claims (20)
1. one kind is utilized the method that bit line dynamically switches increases programming efficiency, it is characterized in that this method comprises:
Provide a charge capturing storage unit (CTMC) array and a plurality of induction amplifier configuration for this array is programmed;
The data that reception is about to be programmed enter in this array;
A class that is about to be programmed according to more than first storage unit in this array of this data decimation; And
Use these a plurality of induction amplifiers that more than second storage unit in this array is programmed to the class that this is chosen as far as possible.
2. the method for claim 1 is characterized in that, this provides an array to comprise provides a multistage charge capturing storage unit array.
3. method as claimed in claim 2 is characterized in that, this provides a multistage charge capturing storage unit array to comprise provides a quadravalence charge capturing storage unit array.
4. the method for claim 1 is characterized in that, this use comprises uses the whole of these a plurality of induction amplifiers.
5. the method for claim 1 is characterized in that, also comprises:
Provide the bit line configuration for connecting these a plurality of induction amplifiers to a plurality of storage unit; And the connection of switching bit line maximizes with use that will this a plurality of induction amplifiers.
6. method as claimed in claim 5 is characterized in that, this switching comprises:
This induction amplifier that is used of configuration with this storage unit of programming to this class that chooses; And connect this induction amplifier that is used to this more than second storage unit.
7. method as claimed in claim 6 is characterized in that, also comprising with the unit of classifying as provides this array, and each row comprises a plurality of characters, and each character comprises a plurality of storage unit, and these a plurality of induction amplifiers are corresponding with these a plurality of storage unit.
8. method as claimed in claim 7 is characterized in that, this switch to allow these a plurality of induction amplifiers with being connected of these a plurality of storage unit with this storage unit position character have nothing to do.
9. a memory storage is characterized in that, comprises:
One charge capturing storage unit (CTMC) array;
A plurality of induction amplifier configurations are for to programme to this array that is coupled;
Multiple bit lines is arranged to these a plurality of induction amplifiers of connection to a plurality of storage unit; And
One switches the array group attitude maximizes with use that will this a plurality of induction amplifiers when the programming for the connection of switching this bit line.
10. memory storage as claimed in claim 9 is characterized in that, this array comprises a multistage charge capturing storage unit array.
11. memory storage as claimed in claim 10 is characterized in that, this multistage charge capturing storage unit array comprises quadravalence charge capturing storage unit array.
12. memory storage as claimed in claim 9 is characterized in that:
This array comprises the multiple row of this storage unit; And
Each row in this multiple row comprise a plurality of characters, and each character comprises a plurality of storage unit.
13. memory storage as claimed in claim 12 is characterized in that, also comprise an address decoder configuration for receive an address and according to this address to choose the row in this array.
14. memory storage as claimed in claim 13 is characterized in that, this address decoder also configuration is to choose a character in the row of choosing at this according to this address.
15. memory storage as claimed in claim 12 is characterized in that:
These a plurality of induction amplifiers comprise at least 128 induction amplifiers; And
The a plurality of storage unit of in each character this comprise at least 128 storage unit.
16. memory storage as claimed in claim 12 is characterized in that, each row in this multiple row comprise at least 128 characters.
17. one kind is utilized the method that bit line dynamically switches increases programming efficiency, it is characterized in that, comprises:
Provide a charge capturing storage unit (CTMC) array and a plurality of induction amplifier configuration for this array is programmed;
The multistage data that reception is about to be programmed enter in a charge capturing storage unit (CTMC) array, this array comprises multiple bit lines and is applicable to storage unit in this array of addressing, a plurality of induction amplifiers are applicable to programmes to this storage unit, and a switching array is applicable to these a plurality of induction amplifiers of connection and a plurality of storage unit;
Choose a programming class;
Count being about to be programmed to this storage unit of choosing programming class; And choose programming class to this according to a big or small memory cells of these a plurality of induction amplifiers.
18. method as claimed in claim 17 is characterized in that, also comprises when the Number of Storage Units of desire programming during greater than this sizes of this a plurality of induction amplifiers, uses all this a plurality of induction amplifier memory cells to choose the class that programmes to this.
19. method as claimed in claim 18 is characterized in that, also comprises:
When the Number of Storage Units of desire programming during greater than this sizes of this a plurality of induction amplifiers, the Number of Storage Units that reduces this desire programming is this size that deducts these a plurality of induction amplifiers, thereby a residue number of the storage unit of decision desire programming; And
When this residue number of the storage unit of desire programming during, each storage unit is used an induction amplifier this remainder purpose storage unit of programming less than this sizes of this a plurality of induction amplifiers.
20. method as claimed in claim 17 is characterized in that, this reception comprises reception quadravalence data.
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| CN2010100046454A CN102129884A (en) | 2010-01-20 | 2010-01-20 | Method and device for increasing programming efficiency by utilizing dynamic bit line switching |
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Application publication date: 20110720 |