KR101183184B1 - Chip On Flim Package and Fabricating Method of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process and structure of a chip on film package, and in particular, a step of forming a circuit pattern including a sprocket hole and an input / output terminal pattern on an insulating film, and an electronic device of the insulating film. Step 2 of forming at least one heat dissipation hole in the chip mounting region; and step 3 of mounting and molding an electronic device chip on a part of the circuit pattern surface; and 4 discharging the heat dissipation hole with a metal material to form a heat dissipation member. A step is made.
According to the present invention, when manufacturing a chip on film (Chip On Flim) package, forming a heat dissipation hole in the mounting portion of the electronic device chip, and provided with a heat dissipation member for filling the heat dissipation hole with a metal material, By efficiently dissipating the generated heat to the outside, the chip temperature is lowered, thereby significantly reducing the defective rate caused by the heat of the electronic device chip.

Description

Chip On Flim Package and Fabricating Method of the same

The present invention relates to a chip on film (COF) package and a method of manufacturing the same.

There are many types of semiconductor packages, but the tape automated bonding (TAB) technology is a technology that has been advanced in an independent mounting method, such as using an inner lead bonding (ILB) technology as an internal connection method. Among these tap technologies, COF (Chip On Flim) is developed in a new form to cope with the trend of light and short reduction of electronic equipment such as displays, and unlike TCP (Package Carrier Package), there is no device hole. With the structure, while applying the existing TCP manufacturing process as it is, the advantage that has the flexibility (flexiblity) than TCP is implemented, has been applied to various fields.

In the case of a chip on film (Chip On Flim) package, the device hole region formed in the TCP package is formed in the step tape 20 region D below the region where the semiconductor chip 10 surrounded by the molding material M is mounted. As it has a structure that is not formed, heat is generated in the semiconductor chip when an electric signal is applied after the assembly of the panel and the PCB after assembly, and this heat is not emitted to the outside, so that the malfunction of the semiconductor chip and the temperature of the PCB are increased. There is a problem that causes the equipment to fail. In particular, in the case of chip-on film, while attempting to release the heat generated in the chip while maintaining a flip chip bonding method in the COF and dissipating heat inside the chip, there are limitations due to technical difficulties. Is bumping.

The present invention has been made to solve the above-described problems, an object of the present invention is to form a heat dissipation hole in the mounting portion of the electronic device chip during the manufacture of a chip on film (Chip On Flim) package, the heat dissipation hole is a metal By providing a heat dissipation member filled with a material, by efficiently dissipating heat generated in the electronic device chip to the outside, thereby providing a chip-on film package that lowers the temperature of the chip and thereby significantly reduces the defective rate due to heat of the electronic device chip There is.

As a means for solving the above problems, the present invention comprises the steps of forming a circuit pattern including a sprocket hole and the input and output terminal pattern on the insulating film; Forming at least one heat dissipation hole in the electronic device chip mounting region of the insulating film; Mounting and molding an electronic device chip on a portion of the circuit pattern surface; Filling the inside of the heat dissipation hole with a metal material to form a heat dissipation member; to provide a method of manufacturing a chip on film (Chip On Flim) package comprising a.

In addition, the first step, a 1) a first punching step of forming a sprocket hole in the insulating film; a 2) forming a circuit pattern through photolithography after surface activation of the insulating film; It can be performed including.

In addition, the surface to form a plating layer in a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary, ternary alloy thereof on the circuit pattern surface formed in step a2) It may be configured to further comprise a processing step.

The step 3 may further include forming a solder resist layer on a circuit pattern other than a portion bonded to the electronic device chip.

In particular, the present invention in the above-described manufacturing process is to fill the metal paste formed of any one of Cu, Ni, Pd, Au, Sn, Ag, Co or binary, ternary alloys thereof into the heat dissipation hole Can be configured in steps.

The structure of the chip on film package implemented in the above-described manufacturing process is as follows.

Specifically, the electronic device chip having an input / output connection portion formed on at least one active surface; A tab tape having a circuit pattern that is an input / output terminal pattern corresponding to the input / output connector; At least one heat dissipation hole in the tab tape corresponding to the electronic device chip mounting area; And a heat dissipation member formed of a metal material filled in the heat dissipation hole.

In this case, the heat dissipation member in the above-described structure is formed of a plurality of heat dissipation blocks filled in the heat dissipation hole, or supports the heat dissipation block, and is formed on the bottom surface of the tape tape at a position corresponding to the chip mounting area. It may be configured to further include a heat radiation plate is formed.

In this case, the heat dissipation member may be formed of any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or ternary alloy thereof.

In addition, the circuit pattern may be configured to further include a plated layer in a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary, ternary alloy thereof.

Furthermore, the circuit pattern other than the portion bonded to the electronic device chip may further include a protective layer formed of a solder resist.

In addition, the space between the electronic device chip and the step tape may be filled with a molding material surrounding the chip, and the molding material may use a material including an epoxy resin and a curing agent.

According to the present invention, when manufacturing a chip on film (Chip On Flim) package, forming a heat dissipation hole in the mounting portion of the electronic device chip, and provided with a heat dissipation member for filling the heat dissipation hole with a metal material, By efficiently dissipating the generated heat to the outside, the chip temperature is lowered, thereby significantly reducing the defective rate caused by the heat of the electronic device chip.

1 is a conceptual diagram illustrating a problem of a conventional tab package.
Figures 2a and 2b, 3a and 3b shows a manufacturing process flow chart and process diagram of the chip on film (Chip On Flim) package according to the present invention.
4 is a cross-sectional conceptual view illustrating a structure of a chip on film package according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation according to the present invention. In the description with reference to the accompanying drawings, the same components are given the same reference numerals regardless of the reference numerals, and duplicate description thereof will be omitted. The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The chip on film package according to the present invention forms a fine heat dissipation hole in the step tape portion of the region in which the electronic device chip is mounted, and fills the heat dissipation member for heat transfer to increase the efficiency of heat transfer in the heat dissipation hole. It is an object of the present invention to have a structure capable of efficiently dissipating heat generated from an electronic device chip to an outside of a package. Hereinafter will be described in detail the configuration and operation of the present invention through the manufacturing process diagram of the chip on film (Chip On Flim) package according to the present invention.

2A and 2B illustrate a manufacturing flowchart and process diagram of a chip on film package according to the present invention.

The manufacturing process according to the present invention is largely the first step of forming a circuit pattern including a sprocket hole and the input and output terminal pattern on the insulating film and the second step of forming at least one heat dissipation hole in the electronic device chip mounting area of the insulating film, And a three step of mounting and molding an electronic device chip on a part of the circuit pattern surface and a four step of filling the inside of the heat dissipation hole with a metal material to form a heat dissipation member. In particular, the present invention induces the heat radiation of the primary electronic device chip through the heat dissipation hole, and to implement the second heat dissipation by implementing a heat dissipation member to fill the heat dissipation hole with a metal material in order to maximize the efficiency of heat dissipation. It is a feature of the process to implement the present technology.

Specifically, the first step may be made of the following detailed process.

First, in step S1, a functional whole sprocket hole 120 may be formed in the insulating film 110 to catch an exposure alignment through a first punching process. example

Although the process may be performed as a process of forming one package, it is generally performed as a process that can form a plurality of packages in the insulating film, the first punching process is the outer shell of one insulating film sheet for this purpose It is a process of forming the sprocket 120 of an area | region.

Next, the circuit pattern 130 is formed on the insulating film 110 in step S2.

The circuit pattern is formed by performing surface activation on the insulating film, then applying a photoresist, forming a necessary circuit through an exposure development, an etching process, and

It can be carried out by a process of peeling the resist. In this case, the circuit pattern is not formed in the portion of the mounting region P where the electronic device chip may be mounted in addition to the circuit pattern formation region.

Thereafter, the second step may be performed by the following process.

That is, the second punching process is performed as step S3, and a process of forming a fine heat dissipation hole 140 in the mounting region by punching. As described above, in the case where a plurality of package tapes are formed as described above, the mounting of the sprocket holes in the secondary punching process of forming the sprocket holes in the areas to be the respective tape tapes is performed simultaneously with the mounting. It may be performed by a process of forming a fine heat radiation hole in the region (P). Subsequently, the surface of the circuit pattern may be plated with a single layer or a multilayer by using any one of Cu, Ni, Pd, Au, Sn, Ag, and Co, or a binary or ternary alloy thereof. The process of performing may be further performed.

Subsequently, a process of applying the solder resist 150 to surfaces other than the circuit pattern surface 131 for bonding in step S4 may be performed (S 41), and in the assembly process, the electronic device chip 160 and the Bonding with the circuit pattern surface 131 is performed (S42) (step 3).

Thereafter, molding operation is performed around the electronic device chip with the molding material 170 (S 43). In this case, the molding material used is preferably a material having a viscosity that does not leak to the outside through the heat dissipation hole 140. For example, the molding material may be a liquid potting material having a constant viscosity including an epoxy resin and a curing agent.

Subsequently, a process of implementing a heat dissipation member by filling a metal material in the heat dissipation hole 140 is performed as the four step process.

3A and 3B, this is a process conceptual diagram illustrating a process of implementing a heat dissipation member by filling a metal material in a heat dissipation hole according to the present invention.

As shown in Figure 3a, the heat dissipation member according to the present invention is applied to the metal paste (P) through the screen mask (M) inside the heat dissipation hole 140, through the squeeze (S) heat dissipation hole ( 140 may be implemented by inserting the metal material into the inside. In this case, the metal material may be a metal paste formed of any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or ternary alloy thereof, and more preferably, silver paste. Alternatively, silver (Ag), Ag / Pd alloys may be used, or silver (Ag), chromium (Cr), a mixture of silver and chromium, copper (Cu), tin (Sn), beryllium (Be), nickel (Ni) And palladium (Pd), aluminum (Al), molybdenum (Mo), titanium (Ti), tungsten (W), cobalt (Co), gold (Au), or a binary or tertiary alloy thereof. .

Alternatively, as illustrated in FIG. 3B, the heat dissipation member may be implemented by a dot type process in which the metal material P is inserted into the heat dissipation hole using the ejector X. FIG.

4 is a schematic cross-sectional view illustrating a structure of a chip on film package according to the present invention implemented by such a process.

With reference to this will be described the structure of the chip on film (Chip On Flim) package according to the present manufacturing process.

The package according to the present invention includes an electronic device chip 160 having an input / output connection portion having at least one formed on an active surface of the step tape 110, which is an insulating film, and an input / output terminal pattern corresponding to the input / output connection portion. At least one heat dissipation hole 140 corresponding to the electronic device chip mounting region implemented in the tab tape 110 having a circuit pattern, and a heat dissipation member formed of a metal material filled in the heat dissipation hole ( It is formed into a structure containing H).

In particular, the heat dissipation member (H) is composed of only a plurality of heat dissipation block 141 filled in the heat dissipation hole 140, or supports the heat dissipation block 141, the position corresponding to the chip mounting area The heat dissipation plate 142 is formed on the lower surface of the tape tape may be implemented in a structure formed.

In the present invention, the heat dissipation hole serves to dissipate heat from the electronic device chip to the outside, and is provided with a heat dissipation member (H) for efficiently implementing heat transfer in the heat dissipation hole to greatly enhance the heat transfer efficiency. It becomes possible. In particular, the configuration of the heat dissipation plate 142 for supporting the heat dissipation block 141 can further enhance the heat transfer efficiency and perform the function of the support member for supporting the bottom of the chip.

The heat dissipation block 141 or the heat dissipation plate 142 may be formed of a metal material (metal paste), and may be formed of any one of Ni, Pd, Au, Sn, Ag, and Co, or a binary or ternary alloy thereof. have. Of course, the metal material is not limited thereto, and various materials may be applied in addition thereto.

For example, silver (Ag), Ag / Pd alloy may be used as the metal paste, or silver (Ag), chromium (Cr), a mixture of silver and chromium, copper (Cu), tin (Sn), beryllium (Be), Nickel (Ni) and palladium (Pd), aluminum (Al), molybdenum (Mo), titanium (Ti), tungsten (W) may be used. Alternatively, a paste in which only one or two or more kinds of aluminum (Al), gallium (Ga), and boron (B) are added to the aluminum or titanium fine powder may be used.

Alternatively, a conductive ceramic material may be used as another example of the metal paste. For example, an oxide ceramic material represented by the general formula XaY1-aZO b or (X1-aYa) 2ZO b, wherein 0 <a <1, 3 b <4, where X is added to the group of Ba, Ca, Sr and Mg. At least one element selected and Y is at least one element selected from the group of Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu And Z also means a titanium or silicon binder which is at least one element selected from the group of Cu, Ag and Au.

Alternatively, molybdenum (Mo) 44-68% by weight, tungsten (W) 12-36% by weight, manganese (Mn) 3-15% by weight, silicon oxide (SiO2) in order to improve the adhesion and sinterability inside the heat dissipation hole. Paste mixed at a ratio of 3 to 15% by weight and 0.5 to 2% by weight of titanium oxide (TiO 2) may be used.

Furthermore, in the above-described structure, the circuit pattern 131 further includes a plated layer as a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or binary or ternary alloys thereof. It is desirable to be able to protect the circuit. In addition, a circuit layer other than an area of the circuit pattern 131 bonded to the electronic device chip 160 may further include a protective layer formed of a solder resist 150.

In addition, the space between the electronic device chip and the step tape and the peripheral portion of the chip can be filled with a molding material 170, the molding material may be formed of a material containing an epoxy resin, a curing agent. For example, as an example of such a molding material, a mixture of a liquid epoxy resin and a curing agent and an accelerator containing an aromatic compound may be used. In this case, the curing agent may be a material consisting of a polyhydroxy aromatic compound having at least two hydroxyl groups and at least one carboxyl group, specifically, 2,3-dihydroxybenzoic acid; 2,4-dihydroxybenzoic acid ; 2,5-dihydroxybenzoic acid; 3,4-dihydroxybenzoic acid; Gallic acid; 1,4-dihydroxy-2-naphthoic acid; 3,5-dihydroxy-2-naphthoic acid; Phenolphthalin; It may consist of a composition selected from the group consisting of diphenolic acid and mixtures thereof.

In addition, the molding material according to the present invention may include an electrically non-conductive filler or an inorganic filler such as fused silica or crystalline silica in addition to the above-described curing agent. In another example, the molding material according to the present invention may be a liquid epoxy resin. A mixture of liquid alkylated diaminodiphenylmethane, epoxidized polybutadiene and inorganic filler can be used for the process.

COF having a heat dissipation hole of the above structure according to the present invention is to effectively dissipate heat generated from the chip to realize the advantage that can significantly reduce the malfunction and failure due to the heat of the entire electronic equipment.

In the foregoing detailed description of the present invention, specific examples have been described. However, various modifications are possible within the scope of the present invention. The technical idea of the present invention should not be limited to the embodiments of the present invention but should be determined by the equivalents of the claims and the claims.

110: insulating film (tap tape)
120: sprocket hole
130: circuit pattern
140: heat dissipation hole
141: heat dissipation block
142: heat dissipation plate
150: solder resist
160: electronic device chip
170: molding material
H: heat dissipation member
X: ejector
G, P: metal material or metal paste
S: Squeeze

Claims (15)

Forming a circuit pattern including a sprocket hole and an input / output terminal pattern on the insulating film;
Forming at least one heat dissipation hole in the electronic device chip mounting region of the insulating film through a punching process;
Mounting and molding an electronic device chip on a portion of the circuit pattern surface;
Filling the inside of the heat radiating hole with a metal material to form a heat radiating member;
Including;
Step 4 is a step of applying a metal paste to the inside of the heat dissipation hole via a screen mask (M),
Method of manufacturing a chip on film (Chip On Flim) package comprising the step of inserting the metal material into the heat dissipation hole through a squeeze.
The method according to claim 1,
The first step,
a 1) punching step of forming a sprocket hole in the insulating film;
a 2) forming a circuit pattern through photolithography after surface activation of the insulating film;
Method of manufacturing a chip on film (Chip On Flim) package is performed, including.
The method according to claim 2,
Surface treatment for forming a plating layer in a single layer or multiple layers using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or ternary alloy thereof on the circuit pattern surface formed in step a2) Method of manufacturing a chip on film (Chip On Flim) package further comprising a process.
The method according to claim 2,
The method may further include forming a solder resist layer on a circuit pattern other than a portion bonded to the electronic device chip.
5. The method according to any one of claims 1 to 4,
In the fourth step,
Method of manufacturing a chip on film (Chip On Flim) package which is filling the metal paste into the heat dissipation hole.
An electronic device chip having an input / output connection portion formed on at least one active surface;
A tab tape including a circuit pattern that is an input / output terminal pattern corresponding to the input / output connection unit;
At least one heat dissipation hole in a tab tape corresponding to a mounting area of the electronic device chip;
A heat dissipation member formed of a metal material filled in the heat dissipation hole;
Including;
The heat dissipation hole is formed through a punching process on the tab tape,
The heat dissipation member is a chip-on-film (Chip) is formed through the process of applying a metal paste to the inside of the heat dissipation hole through a screen mask (M), and inserting the metal material into the heat dissipation hole through a squeeze On Flim) package.
The method of claim 6,
The heat dissipation member,
A chip on film package formed of a plurality of heat dissipation blocks filled in the heat dissipation hole.
The method of claim 7,
The heat dissipation member,
And a heat dissipation plate supporting the heat dissipation block, the heat dissipation plate being formed on a lower surface of the tape tape at a position corresponding to the mounting area of the electronic device chip.
The method according to claim 7 or 8,
The heat dissipation member,
Silver (Ag), Ag / Pd alloys, or silver (Ag), chromium (Cr), mixtures of silver and chromium, copper (Cu), tin (Sn), beryllium (Be), nickel (Ni) and palladium A chip-on film formed of any one of (Pd), aluminum (Al), molybdenum (Mo), titanium (Ti), tungsten (W), cobalt (Co), gold (Au), or a binary or ternary alloy thereof ( Chip On Flim) package.
The method according to claim 9,
On the circuit pattern, a chip on film package further comprising a plating layer as a single layer or a multilayer using any one of Cu, Ni, Pd, Au, Sn, Ag, Co, or a binary or ternary alloy thereof. .
The method according to claim 9,
A chip on film (Chip On Flim) package, characterized in that the circuit pattern other than the portion bonded to the electronic device chip further comprises a protective layer formed of a solder resist.
The method according to claim 9,
A chip on film (Chip On Flim) package, characterized in that the separation space between the electronic device chip and the step tape and the chip surroundings are filled with a molding material.
The method of claim 12,
The molding material chip on film (Chip On Flim) package, characterized in that containing an epoxy resin and a curing agent.
The method of claim 6,
The metal paste is a chip on film (Chip On Flim) package, characterized in that formed of a conductive ceramic material.
The method of claim 6,
The metal paste is 44 to 68 wt% molybdenum (Mo), 12 to 36 wt% tungsten (W), 3 to 15 wt% manganese (Mn), 3 to 15 wt% silicon oxide (SiO2), and titanium oxide (TiO2) Chip On Flim package, characterized in that the paste is mixed in a proportion of 0.5-2% by weight.

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