KR101175261B1 - Memory device, non-volatile memory device and method for fabricating the same - Google Patents

Abstract

The present technology relates to a memory device, a nonvolatile memory device and a method of manufacturing the same. A nonvolatile memory device includes: a plurality of device isolation layers embedded in a substrate and extending in parallel in a first direction to define an active region; And a plurality of memory cells formed on at least two active regions while crossing the device isolation layer.

According to the present technology, the charge trap on the second active region for the read operation can be prevented by separating the active region for the read operation from the active region for the program / erase operation. Therefore, even if the number of cycling increases, it is possible to prevent the cell current value from decreasing due to the charge trap. That is, the cycling characteristics of the memory device can be improved.

Nonvolatile Memory Devices, Floating Gate Electrodes

Description

MEMORY DEVICE, NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a memory device, a nonvolatile memory device and a method of manufacturing the same.

A nonvolatile memory device is a memory device in which stored data is maintained even when a power supply is cut off. The nonvolatile memory device includes a gate pattern including a tunnel insulating layer, a floating gate electrode, a charge blocking layer, and a control gate electrode on a substrate, and includes a charge in the floating gate electrode. Save your data by injecting and releasing it.

Hereinafter, a structure and a problem of a nonvolatile memory device according to the related art will be described in detail with reference to the accompanying drawings.

1A is a layout diagram of a nonvolatile memory device according to the prior art.

As illustrated, the active region ACTIVE is defined by the device isolation layer ISO formed in a line region. The bit line BL is provided in the first direction I-I 'on the substrate, and the word line WL is provided in the second direction II-II' crossing the first direction.

Here, a plurality of island-like floating gate electrodes FG are formed on the active region ACTIVE where the bit line BL and the word line LW intersect. In this structure, each of the plurality of memory cells It is connected to one bit line BL.

1B is a plan view of a nonvolatile memory device according to the prior art.

As illustrated, the nonvolatile memory device includes a gate pattern including a tunnel insulating film 11, a floating gate electrode 12, a charge blocking film 13, and a control gate electrode 14 formed on a substrate 10. In addition, spacers 15 may be provided on both sidewalls of the gate pattern, and source / drain regions 16 may be provided in the substrate 10 on both sides of the gate pattern.

The tunnel insulation insulating film 11 is provided as an energy barrier film due to tunneling of charge, and is generally made of an oxide film.

The floating gate electrode 12 serves as a data store for storing charge, and data is stored / erased by charge injection / emission by Fowler-Nordheim tunneling. The floating gate electrode 12 is generally made of a polysilicon film.

The charge blocking film 13 is for preventing charge from moving through the floating gate electrode 12 in the direction of the control gate electrode 14. In general, the charge blocking film 13 includes an ONO film in which an oxide film, a nitride film, and an oxide film are stacked.

According to the prior art as described above, there is a problem that the reliability decreases as the number of cycling increases. Looking at this in more detail as follows.

In the process of repeating the program / erase operation by F-N tunneling, electric charges may be trapped at the interface between the tunnel insulating film 11 and the tunnel insulating film 11 and the substrate 10 (see reference numeral “①” in FIG. 1B). In particular, as the number of cycling increases, the amount of trapped charge increases, thereby causing the source / drain regions 16 to be pushed to the side (see reference numeral “2”) of the memory cells and the source / drain regions 16. The overlapped area is reduced. Therefore, the threshold voltage of the memory cell is increased, thereby causing a problem that the cell current is reduced.

In addition, when the cell current decreases, the cell transistor cannot be turned on by the conventional turn-on voltage during the read operation. Thus, a problem arises in that the cycling characteristics of the memory device are degraded.

FIG. 1C is a graph illustrating a variation of threshold voltages as the number of cycling increases. FIG. Here, the X axis represents the number of cycling, and the Y axis represents the variation value of the threshold voltage.

Through the graph, it can be seen that as the number of cycling increases, the threshold voltage Vt increases. As described above, charges may be trapped at the interface between the tunnel insulating film 11 and the tunnel insulating film 11 and the substrate 10 during the program / erase operation. As the amount increases, the threshold voltage value also increases.

FIG. 1D is a graph showing variation of threshold voltage and cell current as the number of cycling increases. FIG. Here, the X axis represents a threshold voltage value and the Y axis represents a cell current value.

As shown in the graph, as the threshold voltage increases, the cell current value increases and saturates at a predetermined value. However, it can be seen that the cell current value decreases as the number of cycling increases. That is, as the number of cycling increases, the threshold voltage value increases, and accordingly, the cell current value decreases.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a memory device, a nonvolatile memory device, and a method of manufacturing the same, including memory cells formed on at least two active regions.

According to an aspect of the present invention, there is provided a nonvolatile memory device, comprising: a plurality of device isolation layers embedded in a substrate and extending in parallel in a first direction to define an active region; And a plurality of memory cells formed on at least two active regions while crossing the device isolation layer.

In addition, the present invention provides a method of manufacturing a nonvolatile memory device, comprising: forming a plurality of device isolation films in a substrate extending in parallel in a first direction and defining active regions; And forming a plurality of memory cells formed on at least two active regions while crossing the device isolation layer.

The present invention also provides a memory device comprising: a memory cell for storing data; A first bit line connected to the memory cell to perform a program operation on the memory cell; And a second bit line connected to the memory cell for reading data stored in the memory cell.

According to the present invention, memory cells are formed on at least two active regions. In particular, a memory cell is formed on a first active region for performing a program operation and an erase operation and a second active region for performing a read operation. In this manner, by separating the active region for the read operation from the active region for the program / erase operation, the charge trap on the second active region for the read operation can be prevented. Therefore, even if the number of cycling increases, it is possible to prevent the cell current value decrease due to the charge trap. That is, the cycling characteristics of the memory device can be improved.

In the following, the most preferred embodiment of the present invention is described. In the drawings, thicknesses and intervals are expressed for convenience of description and may be shown to be processed compared to actual physical thicknesses. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

2A illustrates a layout diagram of a nonvolatile memory device according to an embodiment of the present invention, and FIG. 2B illustrates a circuit diagram of the nonvolatile memory device.

As shown in FIG. 2A, the active region ACTIVE is defined by the device isolation layer ISO formed in a line form in the field region. A plurality of bit lines are provided in the first direction I-I 'on the substrate, and a plurality of word lines WL are provided in the second direction II-II' crossing the first direction.

The memory cell may be formed on at least two active regions ACTIVE while crossing the device isolation layer ISO. For example, the floating gate electrode FG may be formed of a first active region A1 and a second active region. It is formed on (A2). According to this structure, each of the plurality of memory cells is connected to at least two bit lines BL1 and BL2.

The plurality of active areas ACTIVE included in one memory cell may be distinguished from each other. For example, the first active area A1 may be used to perform a program operation and an erase operation of a memory cell. The area A2 may be used to perform a read operation of the memory cell. That is, the first active region A1 is connected to the first bit line BL1 for performing the program operation and the erase operation, and the second active region A2 is the second bit line BL2 for performing the read operation. It is preferable to connect with).

Of course, the second active region A2 may also be used when performing a verify operation. Here, the verify operation is an operation of reading data stored in a memory cell to confirm whether a program operation or an erase operation is completed. In general, the verify operation is performed by the same method as the read operation. Accordingly, the first active area A1 may be used to perform a program / erase operation, and the second active area A2 may be used to perform a read / verify operation.

As described above, when the active regions A1 and A2 of one memory cell are separated into a first active region A1 performing a program / erase operation and a second active region A2 performing a read operation, reads are performed. The trapping of charges on the second active region A2 for operation can be prevented. That is, even when charge is trapped at the interface between the tunnel insulating film or the tunnel insulating film and the substrate in the FN tunneling process, the charge is trapped in the second active area A2 because it is limited to the first active area A1 performing the program / erase operation. It can be kept fresh without charge.

That is, the charge trap on the second active region A2 for performing the read operation may be prevented, thereby reducing the cell current, thereby improving the cycling characteristics of the memory device.

Hereinafter, referring to FIG. 2B, a method of operating a nonvolatile memory device when one memory cell is connected to two bit lines will be described. In particular, a memory cell is formed on a first active region A1 for performing a program operation and an erase operation and a second active region A2 for performing a read operation, and has a first active region A1 in the first active region A1. The case where the bit line BL1 is connected and the second bit line BL2 is connected to the second active region A2 will be described.

First, when the read operation is performed, a current flowing through the second bit line BL2 is sensed. That is, among the plurality of bit lines connected to one memory cell, a read operation is performed by selecting a bit line for performing a read operation. In this case, since the read operation is performed using the second active region A2 by selecting the second bit line BL2, even if the number of cycling increases, the cell current decrease due to the charge trap is not induced.

Second, when performing a program operation, the program voltage V _PGM is applied to the corresponding word line WL, the ground voltage is applied to the first bit line BL1, and the operating voltage is applied to the second bit line BL2. Apply (Vcc). In this case, a charge is injected into the floating gate electrode by the FN tunneling on the first active region A1 to perform a program operation, and the second active region A2 is boosted so that the program operation is not performed. That is, no charge is trapped on the second active region A2.

Third, in the case of performing the erase operation, the ground voltage is applied to the word line, and the positive erase voltage V _ERS is applied to the bulk. In this case, the charge stored in the floating gate electrode is released into the channel by FN tunneling. Of course, since both of the first active region A1 and the second active region A2 are connected in bulk, charges may be emitted to the second active region A2, but the second active region A2 is on the second active region A2. By forming a tunnel insulating film thicker than the first active region A1, the erase operation may be performed only in the first active region A1.

Alternatively, a negative erase voltage V _ERS is applied to the word line, a ground voltage is applied to the first bit line BL1, and an operating voltage is applied or floated to the second bit line BL2. In this case, the charge stored in the floating gate electrode is released only by the FN tunneling only in the first active region A1, and the erase operation is not performed in the second active region A2. That is, no charge is trapped on the second active region A2.

3A to 3C are perspective views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

As shown in FIG. 3A, after the pad oxide layer 31 and the hard mask layer 32 are formed on the substrate 30, a photoresist pattern for device isolation (not shown) is formed on the hard mask layer 32. To form.

Subsequently, the hard mask layer 32 and the pad oxide film 31 are etched using the device isolation photoresist pattern as a mask, and then the substrate 30 is etched a predetermined depth to extend in parallel in the first direction (I-I '). A plurality of device isolation trenches are formed.

Subsequently, after forming an isolation layer for the isolation layer on the resultant device isolation trench is formed, the planarization process is performed until the surface of the hard mask layer 32 is exposed, parallel to the first direction (I-I ') A plurality of device isolation layers 33 are formed to extend.

As a result, a plurality of active regions A1 and A2 extending in parallel in the first direction I-I 'are defined. In the present specification, for convenience of description, the plurality of active areas A1 and A2 are alternately defined as the first active area A1 and the second active area A2. As described above, the first active area A1 is defined. ) May be used in the program / erase operation, and the second active region A2 may be used in the read operation.

Here, the plurality of device isolation layers 33 may be formed such that the device isolation layer 33 having the first width W1 and the device isolation layer 33 having the second width W2 are alternately formed. In other words, the memory cell formed by the subsequent process may cross the device isolation layer 33 having the second width W2 and be adjacent to the device isolation layer 33 having the second width W2. It is preferably formed on the active region A2.

In particular, the ratio of the first width W1 and the second width W2 is preferably 1: 1 to 2: 1. As such, the interval between the memory cells, that is, the interval between the active regions A1 and A2 included in one memory cell than the first width W1, that is, the second width W2 is formed to have a relatively smaller value. The degree of integration of the memory device can be further improved.

As shown in FIG. 3B, the hard mask layer 32 and the pad oxide layer 31 remaining on the active regions A1 and A2 are removed. In this case, in the process of removing the hard mask layer 32 and the pad oxide layer 31, the surface of the device isolation layer 33A may be removed together with a predetermined thickness.

Subsequently, an oxidation process is performed to form the tunnel insulating layer 34 on the surfaces of the active regions A1 and A2.

Here, the tunnel insulating film 34 formed on the second active region A2 for performing the read operation is formed on the first active region A1 for performing the program operation and the erase operation. It is preferred to have a thicker thickness, and it is preferred to be formed with a thickness of 10 to 20% thicker.

For example, after forming the tunnel insulating film 34 according to the thickness of the tunnel insulating film 34 to be formed on the second active region A2, a mask pattern is formed on the second active region A2. Subsequently, by partially etching the tunnel insulation layer 34 formed on the first active region A2 using the mask pattern as an etching barrier, the tunnel insulation layer 34 having a relatively thick thickness is formed on the second active region A2. can do.

Alternatively, after forming the tunnel insulating film 34 in accordance with the thickness of the tunnel insulating film 34 to be formed on the first active region A1, a protective film is formed on the resultant. Here, it is preferable that a protective film contains a nitride film. Subsequently, after selectively removing the passivation film formed on the second active region A2, the tunnel insulating layer 34 on the exposed second active region A2 is further grown to thereby increase the relative thickness on the second active region A2. As a result, a thick tunnel insulating film 34 may be formed.

Subsequently, after forming the conductive film for the floating gate electrode on the resultant product in which the tunnel insulating film 34 is formed, the plurality of floating gate patterns extending in parallel in the first direction (I-I ') by patterning the conductive film for the floating gate electrode ( 35).

Here, the floating gate pattern 35 extends in the first direction I-I 'while covering at least two active regions A1 and A2. For example, the floating gate pattern 35 may include an isolation layer disposed between the adjacent first active region A1 and the second active region A2 and between the first active region A1 and the second active region A2. 33A) are formed to cover together.

As shown in FIG. 3C, a material film for a charge blocking film and a conductive film for a word line are formed on the resultant formed with the floating gate pattern 35. Here, the material film for charge blocking film preferably includes an ONO film, and the conductive film for word line preferably includes a polysilicon film or a metal film.

Subsequently, after the word line photoresist pattern (not shown) is formed, the word line conductive layer, the charge blocking material layer, and the floating gate pattern 35 are etched using the word line photoresist pattern as an etching barrier. As a result, a plurality of word lines 37 and a charge blocking layer 36 extending in parallel in the second direction II-II 'are formed, and the first active region A1 and the first isolation region 33A cross the device isolation layer 33A. A plurality of island-like floating gate electrodes 35A covering the second active region A2 are formed.

As a result, memory cells are formed on at least two active regions A1 and A2, and one memory cell is connected to at least two bit lines. That is, memory cells are formed on the first active region A1 for performing program and erase operations and the second active region A20 for performing read operations, and one memory cell includes two bit lines BL1, Connected to BL2).

In the present specification, as an example, a structure and a manufacturing method of a nonvolatile memory device have been described. However, the present invention is not limited thereto. The present invention is applicable to all memory devices including memory cells and bit lines, and by connecting one memory cell with at least two bit lines, the characteristics of the memory device can be improved.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a layout diagram of a nonvolatile memory device according to the prior art.

1B is a plan view of a nonvolatile memory device according to the prior art.

Figure 1c is a graph showing the variation of the threshold voltage with increasing number of cycling

1D is a graph showing variation of cell current according to a threshold voltage

2A is a layout diagram of a nonvolatile memory device according to an embodiment of the present invention.

2B is a circuit diagram of a nonvolatile memory device

3A to 3C are perspective views illustrating a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

[Description of Symbols for Main Parts of Drawing]

A1: first active region A2: second active region

BL1: first bit line B2: second bit line

30 substrate 31 pad oxide film

32: hard mask layer 33: device isolation film

34: tunnel insulation layer 35: floating gate pattern

35A: floating gate electrode 36: charge blocking film

37: Wordline

Claims (15)

A plurality of device isolation layers embedded in the substrate and extending in parallel in the first direction to define an active region; A plurality of memory cells formed on the substrate, Each of the plurality of memory cells, A floating gate electrode that overlaps the device isolation layer and overlaps at least two active regions simultaneously; Nonvolatile Memory Device. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, A plurality of word lines extending in parallel in a second direction crossing the first direction Further comprising: Each of the plurality of word lines, Overlapping the floating gate electrode arranged in the second direction Nonvolatile Memory Device. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, A plurality of bit lines extending in parallel in the first direction, Each of the plurality of memory cells is connected to at least two bit lines. Nonvolatile Memory Device. Claim 4 has been abandoned due to the setting registration fee. The memory cell, A first active region for performing a program operation and an erase operation and a second active region for performing a read operation; Nonvolatile Memory Device. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The first active region is connected to a first bit line for performing a program operation and an erase operation. The second active region is connected to a second bit line for performing a read operation. Nonvolatile Memory Device. Claim 6 has been abandoned due to the setting registration fee. The method of claim 1, In the plurality of device isolation layers, a device isolation layer having a first width and a device isolation layer having a second width having a value less than or equal to the first width are alternately formed. The memory cell is formed on two active regions adjacent to the device isolation film of the second width while crossing the device isolation film of the second width. Nonvolatile Memory Device. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The ratio of the first width and the second width, 1: 1 to 2: 1 Nonvolatile Memory Device. Forming a plurality of device isolation films in the substrate, the plurality of device isolation films extending in parallel in a first direction and defining active regions; And Forming a plurality of memory cells on the substrate, Each of the plurality of memory cells, A floating gate electrode that overlaps the device isolation layer and overlaps at least two active regions simultaneously; Method for manufacturing nonvolatile memory device. Claim 9 has been abandoned due to the setting registration fee. 9. The method of claim 8, The memory cell forming step, Forming a tunnel insulating film on the surface of the active region; Forming a plurality of floating gate patterns extending in parallel in the first direction while covering at least two of the active regions on the resultant product in which the tunnel insulating layer is formed; Forming a material layer for a charge blocking layer and a conductive layer for a word line on the resultant product on which the floating gate pattern is formed; And Etching the word line conductive layer, the charge blocking material layer, and the floating gate pattern to form the floating gate electrode while forming a plurality of word lines extending in parallel in a second direction crossing the first direction; Nonvolatile memory device manufacturing method comprising a. A plurality of device isolation layers embedded in the substrate and extending in parallel in the first direction to define an active region; A plurality of memory cells formed on at least two active regions while crossing the device isolation layer; A first bit line connected to the memory cell to perform a program operation on the memory cell; And A second bit line connected to the memory cell to read data stored in the memory cell Memory device comprising a. Claim 11 was abandoned upon payment of a setup registration fee. 11. The method of claim 10, The memory cell includes a floating gate electrode Memory elements. Claim 12 is abandoned in setting registration fee. 11. The method of claim 10, In lead operation, Sensing current flowing through the second bit line Memory elements. Claim 13 was abandoned upon payment of a registration fee. 11. The method of claim 10, In program operation, Applying a ground voltage to the first bit line, and applying an operating voltage to the second bit line. Memory elements. Claim 14 has been abandoned due to the setting registration fee. 11. The method of claim 10, In the erase operation, A ground voltage is applied to the word line and a positive erase voltage is applied to the bulk. Memory elements. Claim 15 is abandoned in the setting registration fee payment. 11. The method of claim 10, In the erase operation, A negative erase voltage is applied to a word line, a ground voltage is applied to the first bit line, and an operating voltage is applied or floated to the second bit line. Memory elements.

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