KR101160821B1 - Panel and multi-domain liquid crystal display including the same - Google Patents

Abstract

  The liquid crystal display according to the exemplary embodiment of the present invention includes a gate line including a gate line having a gate electrode, a gate insulating film covering the gate line, a semiconductor layer formed on the gate insulating film, a bent portion and a gate line formed on the semiconductor layer, A data line having an orthogonal portion, a drain electrode facing the source electrode on the gate electrode, a passivation layer formed on the data line, and a passivation layer formed on the data line, electrically connected to the drain electrode, and adjacent to the data line. A thin film transistor array panel including pixel electrodes bent along a line and a common electrode display panel on which a common electrode is formed. At this time, the common electrode has a cutout which is a domain regulating means, and slits are formed at edges of the common electrode or the pixel electrode. In this way, the response speed of the liquid crystal molecules can be improved as a whole through the slits when the liquid crystal molecules are partially oriented through the cutout.

LCD, Domain, Curved Data Line, Thin Film Transistor, Response Time

Description

A display panel and a multi-domain liquid crystal display including the same {PANEL AND MULTI-DOMAIN LIQUID CRYSTAL DISPLAY INCLUDING THE SAME}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

2 is a layout view of a common electrode display panel of the liquid crystal display according to the first exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to a first exemplary embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV ′ of FIG. 3,

5 is a cross-sectional view taken along line V-V 'and line V'-V' 'of FIG. 4;

6A and 6B are cross-sectional views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention.

7A and 7B are cross-sectional views at the next stage of FIGS. 6A and 6B,

8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

9 is a layout view of a common electrode panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view taken along line X-X ′ of FIG. 8 including the thin film transistor array panel and common electrode display panel of FIGS. 8 and 9;

FIG. 11 is a cross-sectional view taken along lines XI-XI ′ and XI′-XI ″ of FIG. 8 including the thin film transistor array panel and common electrode display panel of FIGS. 8 and 9;

12A and 12B are cross-sectional views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

13A and 13B are cross-sectional views at the next stage of FIGS. 12A and 12B,

14 is a layout view of a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along line XV-XV ′ of the liquid crystal display of FIG. 14;

FIG. 16 is a cross-sectional view of an XVI-XVI 'line and an XVI'-XVI' 'line of the liquid crystal display of FIG. 14;

17 is a layout view of a common electrode display panel for a liquid crystal display according to a fourth exemplary embodiment of the present invention.

FIG. 18 is a layout view of a liquid crystal display including the common electrode display panel of FIG. 17.

19 is a cross-sectional view taken along the line XIX-XIX ′ of the liquid crystal display of FIG. 18;

20 is a cross-sectional view of the liquid crystal display of FIG. 18 taken along lines XX-XX 'and XX'-XX' '.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display panel and a liquid crystal display including the same, and more particularly, to a vertically aligned liquid crystal display for dividing a pixel into a plurality of domains to obtain a wide viewing angle.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower substrates, and a method of forming a constant incision pattern or protrusion on the pixel electrode and the common electrode opposite thereto is performed. This is becoming potent.

However, in the method of forming the protrusions or the incision pattern, the opening ratio is lowered due to the protrusions or the incision pattern portion. In order to compensate for this, an ultra-high-aperture structure that forms the pixel electrode as wide as possible has been devised. However, since the distance between adjacent pixel electrodes is very close, a lateral field formed between the pixel electrodes is strongly formed. Accordingly, the liquid crystals positioned at the edges of the pixel electrodes are affected by the lateral electric field, and thus the alignment is disturbed, resulting in texture or light leakage.                         

In addition, in order to secure a response speed of the liquid crystal, when the projections or the incision patterns are arranged in a large number and the area in which the liquid crystal is divided or more is designed to eight or more, the aperture ratio is lowered due to the incision patterns or the projections.

An object of the present invention is to provide a display panel for forming a stable multi-domain and a liquid crystal display including the same.

Another object of the present invention is to provide a display panel capable of securing a response speed of a liquid crystal without lowering an aperture ratio and a liquid crystal display device including the same.

In order to solve this problem, the present invention provides the following thin film transistor array panel and liquid crystal display device.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a first signal line extending in a first direction on the insulating substrate, and a second signal line having a curved portion and a portion extending in the second direction are insulated from and cross the first signal line. It is. Each pixel defined by the intersection of the first signal line and the second signal line includes a pixel electrode and a thin film transistor connected to the first signal line, the second signal line, and the pixel electrode. Domain regulation support means are formed at the edge of the pixel along the shape of the pixel. In this case, the bent portion of the second signal line and the portion extending in the second direction repeatedly appear in units of the length of the pixel.                     

The domain regulation support means may be composed of slits formed in the pixel electrodes, or stepped portions of the projections.

The bent portion of the second signal line includes two straight portions, one of the two straight portions making up substantially 45 degrees with respect to the first signal line and the other making up substantially -45 degrees with respect to the first signal line. Do.

The thin film transistor array panel further includes a third signal line extending in the first direction, and terminals of the thin film transistor connected to the pixel electrode overlap with the third signal line to form a storage capacitor.

In the thin film transistor, a terminal connected to the second signal line is connected to a portion extending in the second direction, and the first signal line crosses the second signal line at the portion extending in the second direction.

The thin film transistor array panel according to another exemplary embodiment of the present invention may include an insulating substrate, a gate line having a gate electrode and having a gate electrode, a gate insulating film formed over the gate line, a semiconductor layer formed over the gate insulating film, and a semiconductor layer. A data line having a source electrode and having a bent portion and a portion orthogonal to the gate line, a drain electrode facing the source electrode on the gate electrode, a protective film covering a portion of the semiconductor layer, and electrically connected to the drain electrode; And a pixel electrode having a slit formed at an edge thereof, wherein a side adjacent to the data line is bent along the data line.

The curved portion of the data line preferably includes a first portion that forms a 45 degree angle with the gate line and a second portion that forms a −45 degree angle with the gate line.

And a storage electrode connected to the storage electrode line and the storage electrode line formed in parallel with the gate line, and having a wider width than the storage electrode line, wherein the drain electrode has an extended width of a portion connected to the pixel electrode, and the portion is connected to the storage electrode line. Nesting

The color filter may further include a color filter formed on the upper or lower portion of the passivation layer. The color filter may be formed to have red, green, and blue color filters long along the pixel columns separated by the data lines, respectively. It is preferable that this appears repeatedly.

The semiconductor layer may include a data line portion formed under the data line and having substantially the same planar pattern as the data line, and a channel portion formed under and around the source electrode and the drain electrode.

The liquid crystal display according to the exemplary embodiment of the present invention may include a first insulating substrate, a first signal line formed on the first insulating substrate, a first signal line formed on the first insulating substrate, insulated from and intersecting the first signal line, and having a refractive portion. A pixel electrode formed for each pixel defined by the intersection of the second signal line, the first signal line and the second signal line, the thin film transistor connected to the first signal line, the second signal line, and the pixel electrode, and the second insulating substrate facing the first insulating line. An insulating substrate, a common electrode formed on the second insulating substrate, a domain regulating means formed on at least one side of the first insulating substrate and the second insulating substrate, and formed on at least one side of the first insulating substrate and the second insulating substrate; A domain regulating support means which is adjacent to the domain regulating means, and a liquid crystal layer injected between the first insulating substrate and the second insulating substrate. In this case, the pixel is divided into a plurality of domains by domain dividing means, and two long sides of the domain are substantially parallel with the refraction portions of the adjacent second signal lines.

It is preferable that the liquid crystal contained in the liquid crystal layer has negative dielectric anisotropy and the long axis of the liquid crystal is vertically aligned with respect to the first and second substrates.

The domain regulating means may be an incision that the common electrode has, and the width of the incision is preferably between 9 μm and 12 μm.

The domain regulation support means may be a slit that the common electrode or the pixel electrode has, and the width of the domain regulation support means is preferably between 2 μm and 5 μm.

The domain regulation means may be a protrusion formed on the common electrode or the pixel electrode, and the domain regulation support means may be formed as a stepped portion of the protrusion.

In the case of classifying the domains according to the direction in which the main directors of the liquid crystal contained in the domains are arranged upon application of the electric field, the domains may be classified into four types, each of which is disposed outside the first and second insulating substrates. It further comprises a first polarizing plate and a second polarizing plate, one of the transmission axis of the first polarizing plate and the transmission axis of the second polarizing plate is preferably parallel to the first signal line and the other one is made vertical.

The common electrode display panel according to an exemplary embodiment of the present invention includes an insulating substrate, a common electrode formed on the insulating substrate, a domain regulating means formed on the insulating substrate, a domain regulating portion formed on the insulating substrate and adjacent to the domain regulating means. Support means.

The domain regulating means may be a cutout formed in the common electrode or a protrusion formed on the common electrode, and the domain regulating support means may be formed of a step portion of the slit or the projection formed in the common electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

Next, a multi-domain liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention, FIG. 2 is a layout view of a common electrode display panel of a liquid crystal display according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV 'of FIG. 3, and FIG. 5 is taken along lines V-V ′ and V′-V ″ of FIG. 3. This is a cross section.

The liquid crystal display according to the first exemplary embodiment of the present invention is a liquid crystal molecule injected into and included between the thin film transistor array panel 100, the common electrode panel 200 facing the thin film transistor panel 100, and the two display panels 100 and 200. The major axis of the pixel 310 is formed of the liquid crystal layer 300 which is oriented perpendicular to the display panels 100 and 200.

First, the thin film transistor array panel will be described in more detail with reference to FIGS. 1, 4, and 5.

The gate line 121 is formed on the insulating substrate 110 in the horizontal direction, the gate line 121 has the gate electrode 123 in the form of a protrusion, and one end 125 of the gate line 121 is formed. The width is extended for connection with external circuits.

The storage electrode line 131 and the storage electrode 133 are formed on the insulating substrate 110. The storage electrode line 131 is connected to the storage electrode 133 extending in the horizontal direction, and the storage electrode 133 has a rhombus shape or a rectangular shape and is inclined at 45 degrees with respect to the storage electrode line 131. This is designed along the shape of the pixel defined by the gate line 121 and the data line 171.

The gate lines 121, 123, and 125 and the sustain electrode wirings 131 and 133 have a first layer 211, 231, 251, 311, and 331 made of Cr or Mo alloy having excellent physicochemical properties and low resistivity. The branches are formed of a double layer of second layers 212, 232, 252, 312, 332 made of Al, Ag, or an alloy thereof. These gate lines 121, 123, 125 and sustain electrode wirings 131, 133 may be formed in a single layer or triple layers or more, as necessary.

The gate insulating layer 140 is formed on the gate lines 121, 123, and 125 and the storage electrode wirings 131 and 133.

Semiconductor layers 151 and 154 made of a semiconductor such as amorphous silicon are formed on the gate insulating layer 140. The semiconductor layers 151 and 154 include a channel part semiconductor layer 154 forming a channel of the thin film transistor and a data line part semiconductor layer 151 positioned under the data line 171.

On the semiconductor layers 151 and 154, ohmic contacts 161, 163 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed. The ohmic contacts 161, 163, and 165 also have a data line contact layer 161 positioned below the data line, a source contact layer 163 and a drain positioned below the source electrode 173 and the drain electrode 175, respectively. And a secondary contact layer 165.

The data line 171 and the drain electrode 175 are formed on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140. The data line 171 extends long and crosses the gate line 121 to define a pixel, and the data line 171 has a source electrode 173 branched and extended to the top of the ohmic contact layer 163. The drain electrode 175 is separated from the source electrode 173 and positioned above the ohmic contact layer 165 opposite to the source electrode 173 with respect to the gate electrode 123. One end 179 of the data line 171 is extended in width to connect to an external circuit.                     

Here, the data line 171 is formed such that the repeatedly bent portion and the vertically extending portion appear with a length of the pixel. At this time, the curved portion of the data line 171 consists of two straight portions, one of the two straight portions forms 45 degrees with respect to the gate line 121, and the other portion is formed on the gate line 121. To -45 degrees. The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121 and the storage electrode line 131. The storage electrode wires 131 and 133 may be disposed between the two bent portions to cross the center of the pixel.

At this time, the ratio of the lengths of the bent portion and the vertically extending portion of the data line 171 is between 1: 1 and 9: 1 (that is, the ratio of the bent portion of the data line 171 is between 50% and 90%). )to be.

Therefore, the pixel formed by the intersection of the gate line 121 and the data line 171 is formed in a band shape.

In addition, the drain electrode 175 overlaps with the storage electrode 133 because the portion connected to the pixel electrode 190 extends in a rectangular shape. As described above, the drain electrode 175 overlaps only the storage electrode 133 and the gate insulating layer 140 to form a storage capacitor sufficiently.

A passivation layer 180 made of an organic insulating layer is formed on the data line 171 and the drain electrode 175. The passivation layer 180 is formed by exposing and developing the photosensitive organic material. If necessary, the passivation layer 180 may be formed by applying a photosensitive organic material and performing a photolithography process, but the forming process is more complicated than forming the passivation layer 180 using the photosensitive organic material.

In the passivation layer 180, a contact hole 181b exposing the drain electrode and a contact hole 183b exposing the end portion 179 of which the width of the data line is extended are formed. The contact hole 182b exposing the end portion 179 of which the width of the gate line is extended is formed through the gate insulating layer 140 together with the passivation layer 180.

At this time, the sidewalls 181a, 182a, and 183a of these contact holes 181b, 182b, and 183b have a gentle slope between 30 and 85 degrees with respect to the substrate surface, or have a stepped profile.

In addition, these contact holes (181b, 182b, 183b) may be formed in a variety of angles or circular shape, the area is not more than 2mm x 60㎛, preferably 0.5mm x 15㎛ or more.

Meanwhile, the passivation layer 180 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

The pixel electrode 190 is formed on the passivation layer 180 through a contact hole 181b and is connected to the drain electrode 175 and has a band shape that is bent along the shape of the pixel. At this time, the pixel electrode 190 is formed so wide that the edge overlaps the data line, thereby ensuring the maximum aperture ratio.

In addition, contact auxiliary members 95 and 97 are formed on the passivation layer 180 and are connected to the end portion 125 of the gate line and the end portion 179 of the data line through contact holes 182b and 183b, respectively. The pixel electrode 190 and the contact assistants 95 and 97 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

Next, the common electrode display panel will be described with reference to FIGS. 2, 4, and 5.

On the lower surface of the upper substrate 210 made of a transparent insulating material such as glass, a black matrix 220 and red, green, and blue color filters 230 are formed to prevent light leakage. An overcoat film 250 made of an organic material is formed. On the overcoat layer 250, a common electrode 270 made of a transparent conductive material such as ITO or IZO and having a cutout 271 is formed. In addition, the common electrode 270 is formed with slits 276 disposed on both sides of the cutout 271, and both ends of the slit 276 may be connected to both ends of the cutout 271, or may not be. have.

At this time, the cutout 271 serves as domain regulating means for dividing and aligning the liquid crystal molecules into a plurality of regions, and the width thereof is preferably between 8 µm and 13 µm. In the case of forming the organic protrusions instead of the cutouts 271 by the domain regulating means, it is preferable to set the width between 5 μm and 10 μm. The slit 276 acts as a domain regulatory support means for improving the response speed of the liquid crystal molecules by extending the fringe fields formed through the cutouts 271 to the entire divided regions when the liquid crystal molecules are oriented in a plurality of regions. The width is preferably between 2 μm and 5 μm.

The black matrix 220 includes a linear portion corresponding to the curved portion of the data line 171, a vertically extending portion of the data line 171, and a triangular portion corresponding to the thin film transistor portion.

The color filter 230 is formed vertically long along the pixel column defined by the black matrix 220, and is periodically bent along the shape of the pixel.

The cutout 271 and the slit 276 of the common electrode 270 are also bent to form a shape that bisects the curved pixel from side to side. Both ends of the cutout 271 are bent once more so that one end is parallel to the gate line 121 and the other end is parallel to the vertically extending portion of the data line 171.

When the liquid crystal layer 300 is formed by combining the thin film transistor array panel 100 and the common electrode panel 200 having the above structure and injecting liquid crystal therebetween, the liquid crystal display according to the first exemplary embodiment of the present invention The panel is made.

The liquid crystal molecules included in the liquid crystal layer 300 have their directors perpendicular to the lower substrate 110 and the upper substrate 210 when no electric field is applied between the pixel electrode 190 and the common electrode 270. Oriented so as to achieve negative dielectric anisotropy. In this case, the arrangement of the liquid crystal molecules 310 is mainly determined by the alignment force of the alignment layers 11 and 21 formed on the inner surfaces of the two display panels 100 and 200, but may not be the case.

The lower substrate 110 and the upper substrate 210 are aligned such that the pixel electrode 190 accurately overlaps the color filter 230. In this way, the pixel is divided into a plurality of domains by the cutout 271. At this time, the pixels are divided into left and right sides by the cutouts 271, but the pixels are divided into four types of domains in which the alignment directions of the liquid crystals are different from each other in the vertical direction.                     

Here, domain division is performed by a fringe field formed at the boundary between the cutout 271 and the pixel electrode 190. In this case, the liquid crystal molecules arranged adjacent to the boundary between the edge cutout 271 of the pixel and the pixel electrode 190 have a high response speed of the liquid crystal due to the direct influence of the fringe field. In the embodiment of the present invention, the slits 276 disposed on both sides of the cutout 271 are formed by the cutout 271 to the center between the cutout 271 and the boundary line of the pixel electrode 190. By extending the fringe field or its influence, the response speed of the liquid crystal molecules disposed in the center portion of the divided pixel may be improved, thereby increasing the amount of luminance in the center portion of the divided pixel. However, when the slit is not applied, the liquid crystal molecules positioned at the center between the two boundary lines are almost unaffected by the fringe field, and thus the response speed is almost slow. As a result, the luminance is decreased at the center of the divided pixel.

At this time, the distance between the two long sides of the domain, that is, the width of the domain is preferably between 10㎛ 30㎛.

The number of domains included in one pixel is four if the size of the pixel is less than 100 µm X 300 µm, and four or eight if the size of the pixel is 100 µm X 300 µm or more.

The liquid crystal display is formed by disposing elements such as polarizing plates 12 and 22, a backlight, and a compensating plate on both sides of the basic panel. In this case, the polarizing plates 12 and 22 are disposed on both sides of the basic panel, respectively, and the transmission axis thereof is disposed so that one of them is parallel to the gate line 121 and the other is perpendicular to the gate line 121.

When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the long side of the domain. However, since the direction is perpendicular to the data line 171, the direction coincides with the direction in which the liquid crystal is inclined by the lateral electric field formed between two adjacent pixel electrodes 190 with the data line 171 therebetween. As a result, the lateral electric field assists the liquid crystal alignment of each domain.

Since the liquid crystal display generally uses inversion driving methods such as point inversion driving, thermal inversion driving, and two-point inversion driving, which apply voltages having opposite polarities to pixel electrodes positioned on both sides of the data line 171, the lateral electric field is Almost always occurs and the direction is the direction that helps the liquid crystal alignment of the domain.

In addition, since the transmission axis of the polarizing plate is disposed in a direction perpendicular to or parallel to the gate line 121, the polarizing plate can be manufactured at low cost, and the alignment direction of the liquid crystal is 45 degrees with the transmission axis of the polarizing plate in all domains, thereby obtaining the highest luminance. Can be.

However, since the length of the wiring increases because the data line 171 is bent, the length of the wiring increases by about 20% when the bent portion of the data line 171 occupies 50%. When the length of the data line 171 increases, the resistance and the load of the wiring increase, thereby increasing the signal distortion. However, in the ultra-high opening ratio structure, the width of the data line 171 can be formed sufficiently wide, and since the thick organic protective film 180 is used, the load of the wiring is also small enough so that the signal distortion problem caused by the increase in the length of the data line 171 can be ignored. Can be.

A method of manufacturing a thin film transistor array panel in a liquid crystal display device having such a structure will be described.

6A and 6B are cross-sectional views in an intermediate step of manufacturing a thin film transistor array panel for a liquid crystal display device according to a first embodiment of the present invention, and FIGS. 7A and 7B are cross-sectional views in a subsequent step of FIGS. 6A and 6B. .

First, as shown in FIGS. 6A and 6B, the first metal layers 211, 231, 251, 311, and 331 made of Cr or Mo alloys, etc., and Al or Ag having low specific resistance, or alloys containing them, or the like are formed. The second metal layers 212, 232, 252, 312, and 332 are successively stacked by a method such as sputtering, and dry or wet etched by a first photolithography process using a mask to maintain the gate line 121 on the substrate 110. A sustain wiring including the electrode line 131 and the sustain electrode 133 is formed. (First mask)

Next, the gate insulating layer 140, the hydrogenated amorphous silicon layer, and the amorphous silicon layer doped with a high concentration of n-type impurities such as phosphorus (P) are respectively 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa using chemical vapor deposition. , The resistive contact layer and the amorphous silicon layer 151 and 154 having the channel portion connected by successively depositing a thickness of 300 300 to 600 Å and patterning the doped amorphous silicon layer and the amorphous silicon layer in a photolithography process using a mask. (Second mask)

Subsequently, conductor layers such as the first metal layers 711, 731, 751, 791 made of Cr or Mo alloys, and the second metal layers 712, 732, 752, 792 made of Al, Ag, or an alloy containing them, and the like. Is deposited to a thickness of 1,500 mV to 3,000 mV by a sputtering method, and then patterned by a photolithography process using a mask to form the data line 171 and the drain electrode 175. (Third mask)

Subsequently, the ohmic contact layer that is not covered by the source electrode 173 and the drain electrode 175 is etched to expose the semiconductor layer 154 between the source electrode 173 and the drain electrode 175, and the ohmic contact layer separated on both sides. (163, 165).

Next, as shown in FIGS. 7A and 7B, a photosensitive organic insulating material is coated to form a passivation layer 180, and exposed through an optical mask 500 having a slit portion 501.

At this time, the slit portion 501 of the photomask smoothes the inclination of the contact sidewalls 181a, 182a, and 183a or reduces the stepped profile to alleviate the problem of the steps of the contact holes 181b, 182b, and 183b. In order to have it, it arrange | positions so that it may correspond to the part used as the side wall 181a, 182a, 183a of a contact hole.

When the passivation layer 180 is exposed through the photomask having the slit portion 501 as described above, as shown in FIGS. 7A and 7B, all portions of the passivation layer 180 to be contact holes 181b, 182b, and 183b are exposed to light. And portions to be sidewalls 181a, 182a, and 183a of the contact holes are partially exposed. Photosensitive means that the polymer is decomposed by light.

Next, the passivation layer 180 is developed to form contact holes 181b, 182b, and 183b and sidewalls 181a, 182a, and 183a.

Next, as shown in FIGS. 4 and 5, the second metal layers 252, 752, and 792 of the wiring exposed through the contact holes 181b, 182b, and 183b are etched and removed, and the ITO or IZO is 400 kV. To a thickness of 500 kHz and photo-etched to form contact auxiliary members 95 and 97 with the pixel electrode 190. (Fifth Mask)

Although the first embodiment has been described with a thin film transistor array panel completed through a manufacturing method using five masks, the thin film transistor array panel may be completed even with four masks to reduce manufacturing costs. Also, the common electrode may have two or more slits on both sides of the cutout. This will be described in detail with reference to FIGS. 8 to 13B.

FIG. 8 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 9 is a layout view showing a structure of a common electrode display panel for a liquid crystal display according to a second exemplary embodiment of the present invention. FIG. 10 is a cross-sectional view taken along line X-X 'and X'-X' 'of FIG. 8, and FIG. 11 is a cross-sectional view taken along line XI-XI' and XI'-XI '' of FIG. FIG. 10 is a diagram illustrating a liquid crystal display in which the thin film transistor array panel and the common electrode panel are aligned.

The thin film transistor array panel for a liquid crystal display according to the second exemplary embodiment is manufactured by a four-sheet mask process, and has the following characteristics as compared with the thin film transistor array panel manufactured by a five-sheet mask process.

The ohmic contact layers 161, 163, 165, and 169 are formed under the data line 171 and the drain electrode 175 in a substantially identical pattern, and a channel between the source electrode 173 and the drain electrode 175 is provided. The amorphous silicon layers 151, 154, and 159 also have substantially the same pattern as the data lines except for the additional connection.                     

9 and 10, a common electrode 270 having an opening 271 is formed in the common electrode display panel 200 for a liquid crystal display according to the second embodiment of the present invention. Unlike the embodiment, two slits 276 are formed.

Next, a method of manufacturing a thin film transistor array panel having such structural features will be described.

12A and 12B are cross-sectional views at an intermediate stage of manufacturing a TFT panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 13A and 13B are cross-sectional views at a next stage of FIGS. 12A and 12B. .

First, as shown in FIGS. 12A and 12B, a first metal layer 211, 231, 251, 311, 331 made of Cr or Mo alloy or the like and Al or Ag having a low specific resistance or an alloy containing the same or the like are made. 2 metal layers 212, 232, 252, 312 and 332 are successively stacked by a sputtering method and dry or wet etched by the first photolithography process using a mask, and the gate lines 121 and 125 on the substrate 110 and A gate wiring including the gate electrode 123 and a storage wiring including the storage electrode line 131 and the storage electrode 133 are formed. (First mask)

Next, the gate insulating layer 140 made of silicon nitride, the amorphous silicon layer 150, and the contact layer 160 made of amorphous silicon doped with a high concentration of n-type impurities were respectively used in a chemical vapor deposition method of 1,500 kPa to 5,000 kPa, Continuous deposition with a thickness of 500 kPa to 2,000 kPa, 300 kPa to 600 kPa, followed by a first metal layer 701 made of Cr or Mo alloy or the like and Al or Ag having a low specific resistance or an alloy containing the same The metal layer 702 is continuously laminated by a method such as sputtering, and the photosensitive film PR is applied thereon with a thickness of 1 µm to 2 µm.

Thereafter, the photoresist film PR is exposed through a mask to form the photoresist pattern PR having a portion where the entire thickness is exposed and a portion where only a part of the thickness is exposed, as shown in FIGS. 12A and 12B.

Subsequently, when the photoresist film PR is developed, the channel portion of the thin film transistor, that is, the portion located between the source electrode 173 and the drain electrode 175 has a smaller thickness than the portion located at the portion where the data wiring is to be formed (data wiring portion). All other parts of the photoresist are removed. At this time, the ratio of the thickness of the photoresist remaining on the channel portion to the thickness of the photoresist remaining on the data wiring portion should be different depending on the process conditions in the etching process, which will be described later. It is preferable to set it as this, for example, it is good that it is 4,000 Pa or less. (2nd mask)

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and as shown in FIGS. 12A and 12B, a slit, a lattice pattern, or a translucent film are used.

At this time, it is preferable that the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slit is smaller than the resolution of the exposure apparatus used in exposure. In the case of using a translucent film, Or a thin film having a different thickness can be used.

When the photosensitive film is irradiated with light through such a mask, the polymers are completely decomposed in the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small in the part where the slit pattern or the translucent film is formed. In the part covered by the light shielding film, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.

This thin photoresist film is applied using a conventional mask that is coated with a photoresist film made of a reflowable material and divided into a part that can completely transmit light and a part that can't completely transmit light, and then develop and ripple. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.

Subsequently, etching is performed on the photoresist pattern PR and the lower layers thereof, that is, the first and second metal layers 701 and 702, the contact layer 160, and the semiconductor layer 150. In this case, the data line and the layers under the data line remain in the data line part, only the semiconductor layer should remain in the channel part, and all three layers 150, 160, 701, and 702 are removed from the gate part. The insulating layer 140 should be exposed.

First, the exposed first second metal layers 701 and 702 are removed to expose the lower intermediate layer 160. In this process, both a dry etching method and a wet etching method may be used. In this case, the first and second metal layers 701 and 702 may be etched and the photoresist pattern PR may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the metal layers 701 and 702 are etched and the photoresist pattern PR is not etched, so that the photoresist pattern PR may also be etched together. In this case, the thickness of the channel photoresist film is thicker than that of the wet etching so that the channel photoresist film is removed in this process so that the second metal layer 702 beneath it is not exposed.

In this way, only the first and second metal layers 701 and 702 of the channel portion and the data wiring portion remain, and the first and second metal layers 701 and 702 of the other portions are all removed to expose the underlying contact layer 160. .

Subsequently, the other portions of the exposed contact layer 160 and the lower portion of the amorphous silicon layer 150 are simultaneously removed by the dry etching method together with the channel portion photoresist. At this time, the etching is performed under the condition that the photoresist pattern PR, the contact layer 160 and the semiconductor layer 150 (the semiconductor layer and the contact layer have almost no etching selectivity) are simultaneously etched and the gate insulating layer 140 is not etched. In particular, the etching ratio of the photoresist pattern PR and the semiconductor layer 150 is preferably equal. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched at almost the same etching rate. When the etch rates for the photoresist pattern PR and the semiconductor layer 150 are the same, the thickness of the channel portion photoresist should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 150 and the intermediate layer 160.

In this way, the photoresist of the channel portion is removed to expose the second metal layer 702, and the contact layer 160 and the semiconductor layer 150 of the other portions are removed to expose the gate insulating layer 140 below. On the other hand, since the photoresist of the data wiring portion is also etched, the thickness becomes thinner. In this step, the semiconductor layer patterns 151, 154, and 159 are completed.

Subsequently, ashing of the photoresist film remaining on the surface of the second metal layer 702 of the channel part C is removed through ashing.

Next, as shown in FIGS. 13A and 13B, the first and second metal layers 701 and 702 and the contact layer 160 under the channel portion are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the first and second metal layers 701 and 702 and the contact layer 160, and by wet etching with respect to the first and second metal layers 701 and 702. The layer 160 may be performed by dry etching. In the former case, the etching is preferably performed under the condition that the etching selectivity of the first and second metal layers 701 and 702 and the contact layer 160 is large. This is because it is difficult to find the etching end point when the etching selectivity is not large, and thus it is not easy to adjust the thickness of the semiconductor pattern 154 remaining in the channel portion. In the latter case of alternating between wet etching and dry etching, the first and second metal layers 701 and 702 which are wet etched have undercuts, but the dry-etched contact layer 160 has almost no undercut. Is made. Examples of the etching gas used to etch the contact layer 160 and the semiconductor (151, 154) may be a mixed gas of the mixed gas of CF ₄ and HCl and CF ₄ and O _2, the CF ₄ and O ₂ In this case, the channel portion semiconductor pattern 154 may be left in a uniform thickness.

In this way, the source electrode 173 and the drain electrode 175 are separated to complete the data lines 171, 173, 175, and 179 and the contact layer patterns 161, 163, 165, and 169 thereunder.

The subsequent manufacturing process is the same as in the first embodiment.

In the manufacturing method of the TFT panel for the liquid crystal display according to the second exemplary embodiment, the manufacturing cost can be minimized by patterning the data line 171, the drain electrode 175, and the semiconductor layer by a photolithography process using one mask. have.

In the above first and second embodiments, the color filter is formed on the common electrode display panel. Alternatively, the color filter may be formed on the thin film transistor substrate, and the slit extending the area of the fringe field may be disposed on the pixel electrode. This structure will be described as a third embodiment.

14 is a layout view illustrating a structure of a liquid crystal display according to a third exemplary embodiment of the present invention. FIG. 15 is a cross-sectional view taken along line XV-XV ′ of the liquid crystal display of FIG. 14, and FIG. 16 is XVI of FIG. 14. Sectional drawing of the -XVI 'line and the XVI'-XVI' 'line.

First, the thin film transistor array panel will be described in detail.

The gate line 121 is formed in the horizontal direction on the insulating substrate 110, and the gate line 121 includes a gate electrode 123 having a protrusion shape. One end 125 of the gate line 121 is extended in width for connection with an external circuit.

The storage electrode line 131 and the storage electrode 133 are formed on the insulating substrate 110. The storage electrode line 131 extends in the horizontal direction and the storage electrode 133 is connected to the storage electrode line 131 in a shape in which a rhombus or a rectangle is inclined at 45 degrees with respect to the storage electrode line 131.

The gate line 121 and the sustain electrode wirings 131 and 133 are formed of a first alloy 211, 231, 251, 311 and 331 made of Cr or Mo alloy having excellent physicochemical properties and Al or Ag having a low specific resistance. Or a double layer of second layers 212, 232, 252, 312, 332 made of an alloy or the like containing them. These gate wirings 121, 123, 125 and sustain electrode wirings 131, 133 may be formed in a single layer or triple layers or more as needed.

The gate insulating layer 140 is formed on the gate line 121 and the storage electrode wirings 131 and 133.

Semiconductor layers 151 and 154 made of a semiconductor such as amorphous silicon are formed on the gate insulating layer 140. The semiconductor layers 151 and 154 may include a channel portion semiconductor layer 154 forming a channel of the thin film transistor and a data line portion semiconductor layer 151 disposed under the data line 171.

On the semiconductor layers 151 and 154, ohmic contacts 161, 163 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed. The ohmic contacts 161, 163, and 165 also have a data line contact layer 161 positioned below the data line, a source contact layer 163 and a drain positioned below the source electrode 173 and the drain electrode 175, respectively. And a secondary contact layer 165.

The data line 171 and the drain electrode 175 are formed on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140. The data line 171 extends long and crosses the gate line 121. And has a source electrode 173 extending in the form of a branch to the top of the ohmic contact layer 163. The drain electrode 175 is separated from the source electrode 173 and with respect to the gate electrode 123. It is positioned above the ohmic contact layer 165 opposite to the source electrode 173. One end portion 179 of the data line 171 is extended in width to connect to an external circuit.

Here, the data line 171 is formed such that the repeatedly bent portion and the vertically extending portion appear with a length of the pixel. At this time, the curved portion of the data line 171 is composed of two straight portions, one of the two straight portions is substantially 45 degrees with respect to the gate line 121, the other portion is the gate line 121 Is substantially -45 degrees relative to The source electrode 173 is connected to a vertically extending portion of the data line 171, and the portion crosses the gate line 121 and the storage electrode line 131.

Therefore, the pixel formed by the intersection of the gate line 121 and the data line 171 is formed in a band shape.

In addition, the drain electrode 175 overlaps with the storage electrode 133 because the portion connected to the pixel electrode 190 extends in a rectangular shape. As such, the drain electrode 175 overlaps the storage electrode 133 with only the gate insulating layer 140 interposed therebetween to form the storage capacitor.

A first passivation layer 801 made of an inorganic insulating material such as silicon nitride is formed on the data line 171 and the drain electrode 175.

Red, green, and blue color filters 230R, 230G, and 230B are formed on the first passivation layer 801. The color filters 230R, 230G, and 230B are formed to be vertically long along the pixel columns partitioned by the data lines 171, and are periodically bent along the shape of the pixels. In the color filters 230R, 230G, and 230B, neighboring color filters 230R, 230G, and 230B partially overlap each other on the data line 171 to form a hill on the data line 171.

A second passivation layer 802 made of a photosensitive organic material is formed on the color filters 230R, 230G, and 230B. The second passivation layer 802 also forms a hill while crossing the hill formed by the overlap of the color filters 230R, 230G, and 230B. As described above, the organic film hill acts as a kind of domain regulation means by adjusting the inclined surface of the alignment layer, thereby enhancing the direction control force of the liquid crystal in each domain.

On the drain electrode 175 and on the end portion 179 where the width of the data line is extended, the drain electrode 175 and the end portion 179 of the data line are exposed through the first and second passivation layers 801 and 802, respectively. Contact holes 181b and 183b are formed. In addition, the contact hole exposing the end portion 125 of the gate line through the gate insulating layer 140 along with the first and second passivation layers 801 and 802 is formed on the end portion 125 where the width of the gate line is extended. 182b) is formed.

At this time, the sidewalls 181a, 182a, and 183a of these contact holes 181b, 182b, and 183b have a gentle slope between 30 and 85 degrees with respect to the substrate surface, or have a stepped profile.

In addition, these contact holes (181b, 182b, 183b) may be formed in a variety of angles or circular shape, the area is not more than 2mm x 60㎛, preferably 0.5mm x 15㎛ or more.

On the other hand, the color filters 230R, 230G, and 230B are removed from the drain electrode 175, so that the contact hole 181b exposing the drain electrode 175 penetrates only the first and second passivation layers 801 and 802. have. Also, the color filters 230R, 230G, and 230B are not formed at the end portion 125 of the gate line and the end portion 179 of the data line which do not constitute the pixel.

The second protective film 802 may also be formed of an inorganic insulating material such as silicon nitride or silicon oxide.

The pixel electrode 190 is formed on the second passivation layer 802 to be connected to the drain electrode 175 through a contact hole 181b and is bent along a shape of the pixel.

In addition, contact auxiliary members 95 and 97 are formed on the passivation layer 180 and are connected to the end portion 125 of the gate line and the end portion 179 of the data line through the contact holes 182b and 183b, respectively. The pixel electrode 190 and the contact assistants 95 and 97 are made of indium tin oxide (ITO) or indium zinc oxide (IZO). At this time, a slit 196 having a shape bent along the shape of the pixel is formed at the edge of the pixel electrode 190. In this case, the slit 196 serves as a domain regulation support means for extending the fringe field formed at the edge of the pixel electrode 190 to the center portion of the divided pixel as in the first embodiment, thereby improving the response speed of the liquid crystal. It can have more than one.

The common electrode display panel will now be described.

A black matrix 220 is formed on the lower surface of the transparent insulating substrate 210 such as glass to prevent light leakage. The black matrix 220 is formed of a transparent conductive material such as ITO or IZO on the black matrix 220, and has an incision 271. The common electrode 270 having the () is formed.

The black matrix 220 includes a linear portion corresponding to the curved portion of the data line 171, a vertically extending portion of the data line 171, and a triangular portion corresponding to the thin film transistor portion.

The cutout 271 of the common electrode 270 is also bent to form a shape that bisects the curved pixel from side to side. Both ends of the cutout 271 are bent once more so that one end is parallel to the gate line 121 and the other end is parallel to the vertically extending portion of the data line 171.

When the liquid crystal layer 300 is formed by combining the thin film transistor array panel and the common electrode panel having the above structure and injecting liquid crystal therebetween, a basic panel of the liquid crystal display according to the third exemplary embodiment of the present invention is formed.

In addition to the advantages of the first embodiment, the liquid crystal display having the above structure has the color filters 230R, 230G, and 230B formed on the thin film transistor substrate, thereby increasing the alignment margin of the two display panels and omitting the overcoat layer 250. And additional advantages.                     

In the method for manufacturing a thin film transistor array panel for a liquid crystal display device having such a structure, in the method for manufacturing a thin film transistor array panel according to the first embodiment, a photosensitive organic layer is coated to form a passivation layer 180 and contact holes 181b, 182b, and 183b. Forming red, green, and blue color filters 230R, 230G, and 230B by repeating a process of depositing a first passivation layer; and applying, exposing, and developing a photosensitive material to which a dye is added. And forming a contact hole penetrating the second passivation layer 802 by applying the photosensitive organic layer and a first passivation layer exposed through the contact hole penetrating the second passivation layer 802. 801) is replaced by a process of etching and removing.

In the third embodiment of the present invention, the second protective film 802 can be omitted, which is possible when the color filters 230R, 230G, 230B which emit little foreign substances such as dyes are used.

In addition, in another embodiment of the present invention, the first passivation layer 801 may be omitted in the third embodiment.

Meanwhile, in the first to third embodiments of the present invention, only the embodiment using the cutout as the divisional alignment means for dividing and aligning the liquid crystal molecules into a plurality of domains has been described, but a projection may be used as the divisional alignment means. It will be described in detail with reference to the drawings.

FIG. 17 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to a fourth exemplary embodiment of the present invention, and FIG. 18 is a layout view illustrating a structure of a liquid crystal display including the common electrode display panel of FIG. 17. 19 and 20 are cross-sectional views of the liquid crystal display of FIG. 18 taken along lines XIX-XIX ', XX-XX', and XX'-XX ''.

Here, the structure of the thin film transistor array panel is omitted in the same manner as in FIG. 1.

As shown in FIGS. 17 to 19, the common electrode display panel of the liquid crystal display according to the fourth exemplary embodiment includes a black matrix 220 for preventing light leakage on the lower surface of the transparent insulating substrate 210 such as glass. ), Red, green, and blue color filters 230 are sequentially formed for each pixel on the black matrix 220, and an overcoat layer 250 made of an organic material or silicon nitride is formed on the color filters 230. ) Is formed. The overcoat layer 250 is formed of a transparent conductive material such as ITO or IZO, and has a common electrode 270 formed thereon, and a protrusion having a stepped sidewall formed of a photosensitive organic insulating material on the common electrode 270. 281 is formed. The projection 281 is located in the center portion and includes a first portion 281b having a first thickness and a stepped portion of the second portion 281a positioned at both the first portion and having a second thickness thinner than the first thickness. do.

At this time, the projections 281 act as domain regulating means for dividing and aligning the liquid crystal molecules into a plurality of regions, such as cutouts. That is, the alignment force is formed perpendicular to the inclined surface of the alignment film 21 formed along the inclined surface of the projection 281, and the liquid crystal molecules are divided and aligned in a plurality of regions by the alignment force.

In the liquid crystal display according to the fourth exemplary embodiment of the present invention, the second portion 281a, which is a stepped portion of the protrusion 281, extends the alignment force for aligning the liquid crystal molecules to the center portion of the divided pixels, thereby extending the first to third portions. It acts as a domain regulatory support means, like the slit 276 in the embodiment. When dividing the liquid crystal molecules into a plurality of regions, the inclined surface of the alignment film 21 by the projections 281 extends to the center of the pixel, and serves as a means for improving the response speed of the liquid crystal molecules due to the alignment force.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, when the data lines are refracted to form pixels in an angled band shape, the lateral electric field between adjacent pixels acts in a direction to assist the formation of the domains, thereby stably forming the domains. Since the polarizers can be manufactured inexpensively, the alignment directions of the liquid crystals are 45 degrees with the transmission axis of the polarizers in all domains, so that the highest luminance can be obtained. In addition, by adding domain regulating support means to protrusions of the slit or the stepped portions at the edges of the divided pixels, the response speed of the liquid crystal molecules can be improved while ensuring the aperture ratio.

Claims (24)

First insulating substrate, A first signal line formed on the insulating substrate and extending in a first direction, A second signal line formed on the insulating substrate and insulated from and intersecting the first signal line, the second signal line having a curved portion and a portion extending in a second direction; A pixel electrode formed for each pixel defined by the crossing of the first signal line and the second signal line; A thin film transistor connected to the first signal line, the second signal line, and the pixel electrode; A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, Domain regulation means formed in the pixel, Domain regulation support means formed at the edge of the pixel along the shape of the pixel Including, The bent portion and the portion extending in the second direction of the second signal line repeatedly appear in units of the length of the pixel, And a width of the domain regulation support means is narrower than a width of the domain regulation means. In claim 1, And said domain regulation support means is a slit formed in said pixel electrode. In claim 1, The curved portion of the second signal line includes two straight portions, one of the two straight portions making up substantially 45 degrees with respect to the first signal line and the other substantially -45 degrees with respect to the first signal line. Liquid crystal display device. In claim 1, And a third signal line extending in the first direction, wherein a terminal of the thin film transistor connected to the pixel electrode overlaps the third signal line to form a storage capacitor. In claim 1, The thin film transistor has a terminal connected to the second signal line connected to a portion extending in the second direction, and the first signal line crosses the second signal line at a portion extending in the second direction. First insulating substrate, A gate line formed on the insulating substrate and having a gate electrode, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A data line formed on the semiconductor layer, defining a pixel to cross the gate line, having a source electrode, and having a bent portion and a portion orthogonal to the gate line and opposing the source electrode on the gate electrode; Drain electrode, A protective film covering a portion of the semiconductor layer, A pixel electrode electrically connected to the drain electrode and having a side adjacent to the data line bent along the data line; A second insulating substrate facing the first insulating substrate, A common electrode formed on the second insulating substrate, Domain regulation means formed in the pixel, A domain regulation support means formed of a slit at an edge of the pixel electrode, And a width of the domain regulation support means is narrower than a width of the domain regulation means. In claim 6, And a curved portion of the data line includes a first portion at 45 degrees with the gate line and a second portion at -45 degrees with the gate line. In claim 6, And a sustain electrode line formed to be parallel to the gate line and the sustain electrode line and wider than the sustain electrode line, wherein the drain electrode has an extended width of a portion connected to the pixel electrode. A liquid crystal display device whose portion overlaps with the sustain electrode. In claim 6, And a color filter formed above or below the passivation layer. The method of claim 9, The color filter includes a plurality of red, green, and blue color filters, each of which is formed along a pixel column separated by the data lines, and the red, green, and blue colors repeatedly appear. In claim 6, And the semiconductor layer includes a data line part formed under the data line and having a substantially same planar pattern as the data line, and a channel part formed under and around the source electrode and the drain electrode. delete delete delete delete delete delete delete delete delete delete Insulation board, A common electrode formed on the insulating substrate, Domain regulating means formed on the insulating substrate, Domain regulating support means formed on the insulating substrate and parallel to the domain regulating means / RTI > The domain regulating means is a cutout formed in the common electrode or a protrusion formed on the common electrode, The domain regulation support means is made of a slit formed in the common electrode or a stepped portion of the protrusion, The width of the slit is narrower than the width of the incision, The common electrode display panel of which the protrusion and the stepped portion of the protrusion are integrally formed. delete delete

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