KR101159693B1 - Method for Manufacturing Semiconductor Device - Google Patents

Method for Manufacturing Semiconductor Device Download PDF

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KR101159693B1
KR101159693B1 KR1020100065185A KR20100065185A KR101159693B1 KR 101159693 B1 KR101159693 B1 KR 101159693B1 KR 1020100065185 A KR1020100065185 A KR 1020100065185A KR 20100065185 A KR20100065185 A KR 20100065185A KR 101159693 B1 KR101159693 B1 KR 101159693B1
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South Korea
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forming
contact plug
etching
insulating film
abandoned
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KR1020100065185A
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Korean (ko)
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KR20120004606A (en
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윤석영
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

본 발명은 금속 배선 사이의 절연막을 식각한 다음에 콘택플러그를 형성하고, 인접한 금속 배선과 쇼트되지 않도록 콘택플러그의 양측벽을 식각하여 보잉(bowing)을 형성함으로써 금속 배선과 콘택플러그 간의 쇼트 불량을 방지할 수 있는 반도체 소자의 제조 방법을 제공한다. The present invention forms a contact plug after etching an insulating film between metal wirings, and forms a bowing by etching both sidewalls of the contact plugs so as not to short with adjacent metal wirings, thereby forming a short fault between the metal wirings and the contact plugs. Provided is a method of manufacturing a semiconductor device that can be prevented.

Description

반도체 소자의 제조 방법{Method for Manufacturing Semiconductor Device}Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 금속 배선과 콘택플러그의 불량을 개선할 수 있는 반도체 소자의 제조 방법에 관련된 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving defects in metal wiring and contact plugs.

반도체는 전기 전도도에 따른 물질의 분류 가운데 하나로 도체와 부도체의 중간 영역에 속하는 물질로서, 반도체에 불순물을 첨가하고 도체를 연결하여 트랜지스터와 같은 반도체 소자를 생성하는데 사용된다. 이러한 반도체 소자를 이용하여 데이터 저장 등의 여러 가지 기능을 수행하는 장치를 반도체 장치라 한다.A semiconductor is a class of materials according to electrical conductivity, and is a material belonging to an intermediate region of a conductor and a non-conductor. The semiconductor is used to add semiconductor impurities and connect conductors to create semiconductor devices such as transistors. A device that performs various functions such as data storage using such a semiconductor device is called a semiconductor device.

이러한 반도체 장치가 점점 고집적화되면서 반도체 칩 크기가 감소하고, 이에 따라 칩 내에 형성되는 다수의 반도체 소자의 크기도 감소하게 되었다.As the semiconductor devices are increasingly integrated, semiconductor chip sizes are reduced, and thus, the size of a plurality of semiconductor devices formed in the chip is also reduced.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체 기판(100)상에 금속 배선(110)을 형성한다. 이때, 금속 배선(110)은 라인 타입으로 형성한다.Referring to FIG. 1A, a metal wire 110 is formed on a semiconductor substrate 100. At this time, the metal wiring 110 is formed in a line type.

다음에는, 금속 배선(110)을 포함한 전면에 제 1 절연막(120)을 형성한다. 제 1 절연막(120) 상부에 감광막(미도시)을 형성한 후, 콘택홀 형성용 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(미도시)을 형성한다.Next, the first insulating film 120 is formed on the entire surface including the metal wiring 110. After forming a photoresist film (not shown) on the first insulating film 120, a photoresist pattern (not shown) is formed by an exposure and development process using a contact hole forming mask.

다음에는, 감광막 패턴을 식각마스크로 이용하여 제 1 절연막(120) 및 반도체 기판(100)을 식각하여 콘택홀(130)을 형성한다.Next, the first insulating layer 120 and the semiconductor substrate 100 are etched using the photoresist pattern as an etching mask to form the contact hole 130.

도 1b를 참조하면, 콘택홀(130)을 포함한 전면에 스페이서용 물질(140)을 형성한다. 이때, 스페이서용 물질(140)은 질화막(Nitride)을 포함한다.Referring to FIG. 1B, the spacer material 140 is formed on the front surface including the contact hole 130. In this case, the spacer material 140 may include a nitride film.

도 1c를 참조하면, 제 1 절연막(120)의 상부 및 반도체 기판(100)이 노출될 때까지 스페이서용 물질(140)을 에치백(Etchback)하여 콘택홀(130) 측벽에만 잔류하는 스페이서(150, Spacer)를 형성한다. 이때, 스페이서(150)를 형성할 때, 콘택홀(130)의 측벽에 스페이서(150)가 일정하게 형성되지 않거나 스페이서(150)를 형성하기 위하여 스페이서용 물질(140)을 식각할 때 스페이서(150)의 일부가 식각되어 인접한 금속배선(110)이 노출되는 문제가 있다. 이러한 콘택홀(130)의 측벽에 스페이서(150)가 일정하게 형성되지 않으면 후속 공정에서 콘택플러그의 폴리머(Polymer)와 인접한 금속 배선(110)이 'A' 와 같이 쇼트(short) 되는 불량이 발생한다.Referring to FIG. 1C, the spacer 150 remaining only on the sidewalls of the contact hole 130 by etching back the spacer material 140 until the upper portion of the first insulating layer 120 and the semiconductor substrate 100 are exposed. , Spacer. In this case, when the spacer 150 is formed, the spacer 150 is not uniformly formed on the sidewall of the contact hole 130 or when the spacer material 140 is etched to form the spacer 150. A portion of) may be etched to expose adjacent metal wires 110. If the spacer 150 is not formed on the sidewall of the contact hole 130 constantly, a defect occurs in which the metal wire 110 adjacent to the polymer of the contact plug is shorted as 'A' in a subsequent process. do.

도 1d를 참조하면, 콘택홀(130)에 도전물질 또는 폴리머(Polymer)를 증착하여 콘택플러그(160)를 형성한다.Referring to FIG. 1D, a contact plug 160 is formed by depositing a conductive material or a polymer in the contact hole 130.

전술한 반도체 소자의 제조 방법에서, 반도체 소자가 고집적화되어 감에 따라 금속 배선과 콘택플러그 사이의 마진(Margin)이 좁아져 쇼트 불량이 발생하는 문제점이 있다.In the above-described manufacturing method of the semiconductor device, as the semiconductor device is highly integrated, a margin between the metal wire and the contact plug is narrowed, resulting in a short defect.

전술한 종래의 문제점을 해결하기 위하여, 본 발명은 금속 배선 사이의 절연막을 식각한 다음에 콘택플러그를 형성하고, 인접한 금속 배선과 쇼트되지 않도록 콘택플러그의 양측벽을 식각하여 보잉(bowing)을 형성함으로써 금속 배선과 콘택플러그 간의 쇼트 불량을 방지할 수 있는 반도체 소자의 제조 방법을 제공한다. In order to solve the above-mentioned problems, the present invention forms a contact plug after etching the insulating film between the metal wires, and forms the bowing by etching both sidewalls of the contact plug so as not to short the adjacent metal wires. Thereby, the manufacturing method of the semiconductor element which can prevent the short defect between a metal wiring and a contact plug is provided.

본 발명은 반도체 기판상에 제 1 금속 배선을 형성하는 단계, 상기 제 1 금속 배선 사이에 콘택 플러그를 형성하는 단계, 상기 콘택 플러그의 양측벽을 식각하는 단계 및 양측벽이 식각된 상기 콘택 플러그를 포함한 전면에 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법을 제공한다.The present invention provides a method for forming a first metal wire on a semiconductor substrate, forming contact plugs between the first metal wires, etching both sidewalls of the contact plug, and etching the contact plugs with both sidewalls. It provides a method for manufacturing a semiconductor device comprising the step of forming an insulating film on the entire surface.

바람직하게는, 상기 제 1 금속 배선을 형성하는 단계와 상기 콘택 플러그를 형성하는 단계 사이에 식각 정지막(Etch Stop Layer)을 형성하는 단계를 더 포함하는 것을 특징으로 한다.Preferably, the method may further include forming an etch stop layer between the forming of the first metal wire and the forming of the contact plug.

바람직하게는, 상기 콘택 플러그를 형성하는 단계는 상기 제 1 금속 배선을 포함한 전면에 희생 절연막을 형성하는 단계 및 콘택 플러그 마스크를 식각 마스크로 상기 희생 절연막 및 상기 반도체 기판을 식각한 후, 플러그 물질을 매립하는 단계를 포함하는 것을 특징으로 한다.Preferably, the forming of the contact plug may include forming a sacrificial insulating film on the entire surface including the first metal wire and etching the sacrificial insulating film and the semiconductor substrate using the contact plug mask as an etching mask, and then plug material. It is characterized in that it comprises a step of embedding.

바람직하게는, 상기 플러그 물질은 도전물질 또는 폴리머(Polymer)를 포함하는 것을 특징으로 한다.Preferably, the plug material is characterized in that it comprises a conductive material or a polymer (Polymer).

바람직하게는, 상기 콘택 플러그를 형성하는 단계와 상기 콘택 플러그의 측벽을 식각하는 단계 사이에 상기 희생 절연막을 제거하는 단계를 포함하는 것을 특징으로 한다.Preferably, the step of removing the sacrificial insulating film between the step of forming the contact plug and the etching of the side wall of the contact plug.

바람직하게는, 상기 콘택 플러그의 양측벽을 식각하는 단계는 습식(wet) 식각 방법을 이용하여 실시하는 것을 특징으로 한다.Preferably, the etching of both side walls of the contact plug may be performed by using a wet etching method.

바람직하게는, 상기 습식 식각 방법에서 식각 용액은 질산계 혼합물을 이용하되, 질산(HNO3)을 주성분으로 하고, 불산(HF) 등의 활성제를 포함하는 것을 특징으로 한다.Preferably, the etching solution in the wet etching method is characterized in that it uses a nitric acid-based mixture, the nitric acid (HNO 3 ) as the main component, and comprises an active agent such as hydrofluoric acid (HF).

바람직하게는, 상기 식각 용액은 0℃ ~ 50℃의 온도에서 사용하는 것을 특징으로 한다.Preferably, the etching solution is characterized in that used at a temperature of 0 ℃ ~ 50 ℃.

바람직하게는, 상기 절연막을 형성하는 단계 후, 상기 절연막 상에 제 2 금속 배선을 형성하는 단계를 더 포함하는 것을 특징으로 한다.Preferably, the method may further include forming a second metal wire on the insulating film after the forming of the insulating film.

본 발명은 금속 배선 사이의 절연막을 식각한 다음에 콘택플러그를 형성하고, 인접한 금속 배선과 쇼트되지 않도록 콘택플러그의 양측벽을 식각하여 보잉(bowing)을 형성함으로써 금속 배선과 콘택플러그 간의 쇼트 불량을 방지할 수 있는 장점이 있다.The present invention forms a contact plug after etching an insulating film between metal wirings, and forms a bowing by etching both sidewalls of the contact plugs so as not to short with adjacent metal wirings, thereby forming a short fault between the metal wirings and the contact plugs. There is an advantage that can be prevented.

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 제조 방법을 도시한 단면도들.
도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들이다.2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 2a를 참조하면, 반도체 기판(100)상에 제 1 금속 배선(210)을 형성한다. 이때, 제 1 금속 배선(210)은 라인(Line) 타입으로 형성하는 것이 바람직하다. 다음에는, 제 1 금속 배선(210)을 포함한 전면에 식각 정지막(220, Etch Stopper layer)을 형성한다. 이때, 식각 정지막(220)은 질화막(Nitride)으로 형성하는 것이 바람직하다.Referring to FIG. 2A, a first metal wire 210 is formed on the semiconductor substrate 100. In this case, the first metal wire 210 may be formed in a line type. Next, an etch stopper layer 220 is formed on the entire surface including the first metal wire 210. In this case, the etch stop layer 220 may be formed of a nitride layer.

도 2b를 참조하면, 식각 정지막(220)을 포함한 전면에 제 1 희생 절연막(230)을 형성한다. 다음에는, 제 1 희생 절연막(230) 상부에 감광막(미도시)을 형성한 후, 콘택홀(Contact hole) 형성용 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(미도시)을 형성한다. 이후, 감광막 패턴을 식각 마스크로 이용하여 제 1 희생 절연막(230) 및 반도체 기판(200)을 식각하여 콘택홀(240)을 형성한다.Referring to FIG. 2B, the first sacrificial insulating layer 230 is formed on the entire surface including the etch stop layer 220. Next, after forming a photoresist film (not shown) on the first sacrificial insulating film 230, a photoresist pattern (not shown) is formed by an exposure and development process using a mask for forming a contact hole. Thereafter, the first sacrificial insulating layer 230 and the semiconductor substrate 200 are etched using the photoresist pattern as an etching mask to form the contact hole 240.

다음에는, 콘택홀(240)을 포함한 전면에 도전물질 또는 폴리머(Polymer)를 증착한 후, 제 1 희생 절연막(230)이 노출될 때까지 도전물질 또는 폴리머를 평탄화 식각하여 콘택플러그(250)를 형성한다.Next, after the conductive material or polymer is deposited on the entire surface including the contact hole 240, the contact plug 250 is planarized by etching the conductive material or polymer until the first sacrificial insulating film 230 is exposed. Form.

도 2c를 참조하면, 제 1 희생 절연막(230)을 제거한다. 이때, 제 1 희생 절연막(230)은 습식(wet) 식각 방법을 이용하여 제거하는 것이 바람직하다. 이때, 제 1 금속 배선(210) 또는 하부의 다른 층들은 식각 정지막(220)에 의해 보호된다.Referring to FIG. 2C, the first sacrificial insulating layer 230 is removed. In this case, the first sacrificial insulating layer 230 may be removed by using a wet etching method. In this case, the first metal wire 210 or the other layers below are protected by the etch stop layer 220.

도 2d를 참조하면, 콘택플러그(250)의 양측벽 일부를 식각하여 인접한 제 1 금속 배선(210)과 접촉되지 않도록 만든다. 즉, 습식 식각 방법을 이용하여 콘택플러그(250)의 측벽을 식각함으로써 'A'와 같이 보잉(bowing)이 형성된다. 이러한 보잉(bowing)으로 인하여 콘택플러그(250)와 제 1 금속 배선(210) 간의 쇼트를 방지할 수 있으며, 콘택플러그(250)의 상부는 다른 금속 배선과 연결될 수 있도록 식각되지 않고 원래의 크기를 유지하여 콘택 저항을 유지할 수 있다.Referring to FIG. 2D, portions of both side walls of the contact plug 250 are etched so as not to contact the adjacent first metal wires 210. That is, by etching the sidewall of the contact plug 250 using a wet etching method, bowing is formed as 'A'. This bowing prevents a short between the contact plug 250 and the first metal wire 210, and the upper portion of the contact plug 250 is not etched to be connected to other metal wires and has an original size. The contact resistance can be maintained.

구체적으로, 콘택플러그(250)의 양측벽을 식각하는 방법은 습식 식각 방법을 이용한다. 습식 식각 방법 중 습식 식각 용액은 질산계 혼합물을 사용하며, 질산계 혼합물은 질산(HNO3)을 주성분으로 하고 불산(HF) 등의 활성제를 혼합한 물질이다. 이때, 습식 용액은 상온에서 사용하는 것이 바람직하다. 가장 바람직하게는, 0℃ ~ 50℃의 온도에서 사용한다.Specifically, a method of etching both side walls of the contact plug 250 uses a wet etching method. In the wet etching method, the wet etching solution uses a nitric acid-based mixture, and the nitric acid-based mixture is made of nitric acid (HNO 3 ) as a main component and an active agent such as hydrofluoric acid (HF). At this time, the wet solution is preferably used at room temperature. Most preferably, it is used at the temperature of 0 degreeC-50 degreeC.

도 2e 및 도 2f를 참조하면, 콘택플러그(250)를 포함한 전면에 제 2 희생 절연막(260)을 형성한 후, 콘택플러그(250)가 노출될 때까지 화학적 기계적 연마(Chemical Mechanical Polishing)과 같은 평탄화 식각 공정을 실시한다. 이때, 도 2d의 'A' 와 같은 보잉(bowing) 영역에 제 2 희생 절연막(260)을 매립함으로써 콘택플러그(250)와 제 1 금속 배선(210)이 완전하게 절연된다.Referring to FIGS. 2E and 2F, after the second sacrificial insulating layer 260 is formed on the front surface including the contact plug 250, the chemical mechanical polishing may be performed until the contact plug 250 is exposed. A planar etching process is performed. In this case, the contact plug 250 and the first metal wire 210 are completely insulated by filling the second sacrificial insulating layer 260 in a bowing area such as 'A' of FIG. 2D.

도 2g를 참조하면, 콘택플러그(250)를 포함한 전면에 제 2 금속 배선(270)을 형성한다.Referring to FIG. 2G, a second metal wire 270 is formed on the entire surface including the contact plug 250.

전술한 바와 같이, 본 발명은 금속 배선 사이의 절연막을 식각한 다음에 콘택플러그를 형성하고, 인접한 금속 배선과 쇼트되지 않도록 콘택플러그의 양측벽을 식각하여 보잉(bowing)을 형성함으로써 금속 배선과 콘택플러그 간의 쇼트 불량을 방지할 수 있는 장점이 있다.As described above, the present invention forms a contact plug after etching the insulating film between the metal wirings, and forms a bowing by etching both sidewalls of the contact plugs so as not to short with the adjacent metal wirings, thereby forming a bow. There is an advantage that can prevent short short between plugs.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (9)

반도체 기판상에 제 1 금속 배선을 형성하는 단계;
상기 제 1 금속 배선 사이에 콘택 플러그를 형성하는 단계;
상기 콘택 플러그의 양측벽을 식각하되, 상기 콘택 플러그의 상부의 너비는 상기 콘택 플러그의 하부의 너비보다 더 넓게 형성되는 단계; 및
양측벽이 식각된 상기 콘택 플러그를 포함한 전면에 절연막을 형성하는 단계
를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.Forming a first metal wiring on the semiconductor substrate;
Forming a contact plug between the first metal wires;
Etching both side walls of the contact plug, wherein a width of an upper portion of the contact plug is wider than a width of a lower portion of the contact plug; And
Forming an insulating film on the entire surface including the contact plugs in which both side walls are etched.
And forming a second insulating film on the semiconductor substrate. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제 1 항에 있어서,
상기 제 1 금속 배선을 형성하는 단계와 상기 콘택 플러그를 형성하는 단계 사이에 식각 정지막(Etch Stop Layer)을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1,
And forming an etch stop layer between the step of forming the first metal wire and the step of forming the contact plug. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 has been abandoned due to the setting registration fee. 제 1 항에 있어서,
상기 콘택 플러그를 형성하는 단계는
상기 제 1 금속 배선을 포함한 전면에 희생 절연막을 형성하는 단계; 및
콘택 플러그 마스크를 식각 마스크로 상기 희생 절연막 및 상기 반도체 기판을 식각한 후, 플러그 물질을 매립하는 단계
를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1,
Forming the contact plug
Forming a sacrificial insulating film on the entire surface including the first metal wire; And
Etching the sacrificial insulating layer and the semiconductor substrate by using a contact plug mask as an etching mask, and then filling a plug material
And forming a second insulating film on the semiconductor substrate. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제 3 항에 있어서,
상기 플러그 물질은 도전물질 또는 폴리머(Polymer)를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법. The method of claim 3, wherein
The plug material includes a conductive material or a polymer (Polymer) characterized in that the manufacturing method of the semiconductor device. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제 3 항에 있어서,
상기 콘택 플러그를 형성하는 단계와 상기 콘택 플러그의 측벽을 식각하는 단계 사이에 상기 희생 절연막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 3, wherein
And removing the sacrificial insulating film between the forming of the contact plug and the etching of the sidewalls of the contact plug. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제 1 항에 있어서,
상기 콘택 플러그의 양측벽을 식각하는 단계는 습식(wet) 식각 방법을 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1,
The etching of both sidewalls of the contact plug is performed using a wet etching method. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제 6 항에 있어서,
상기 습식 식각 방법에서 식각 용액은 질산계 혼합물을 이용하되, 질산(HNO3) 및 불산(HF)을 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method according to claim 6,
In the wet etching method, the etching solution uses a nitric acid-based mixture, wherein the etching solution includes nitric acid (HNO 3 ) and hydrofluoric acid (HF). 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제 7 항에 있어서,
상기 식각 용액은 0℃ ~ 50℃의 온도에서 사용하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 7, wherein
The etching solution is a method of manufacturing a semiconductor device, characterized in that used at a temperature of 0 ℃ ~ 50 ℃. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 has been abandoned due to the setting registration fee. 제 1 항에 있어서,
상기 절연막을 형성하는 단계 후, 상기 절연막 상에 제 2 금속 배선을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조 방법.The method of claim 1,
And after forming the insulating film, forming a second metal wire on the insulating film.
KR1020100065185A 2010-07-07 2010-07-07 Method for Manufacturing Semiconductor Device KR101159693B1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040007112A (en) * 2002-07-16 2004-01-24 주식회사 하이닉스반도체 Method for forming plug of semiconductor device
KR20100076752A (en) * 2008-12-26 2010-07-06 주식회사 하이닉스반도체 Method for forming semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040007112A (en) * 2002-07-16 2004-01-24 주식회사 하이닉스반도체 Method for forming plug of semiconductor device
KR20100076752A (en) * 2008-12-26 2010-07-06 주식회사 하이닉스반도체 Method for forming semiconductor device

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