KR101152395B1 - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device suitable for improving the refresh of the device by reducing the electric field of the storage node contact junction region, the method for manufacturing a semiconductor device of the present invention is located in the channel scheduled region of the semiconductor substrate Injecting carborene; Diffusing the injected decarborene; Etching the semiconductor substrate to a predetermined depth to form a recess shallower than the depth at which the decarborene is diffused; Forming a gate insulating film along a surface of the recess; And forming a recess gate partially recessed in the recess on the gate insulating layer and protruding over the surface of the semiconductor substrate. Accordingly, the present invention provides a refresh effect of a device by applying a recess gate. as well as to improve, by using the dopant during the cell threshold voltage adjustment ion implantation of the mass is about 10 times heavier B ₁₀ H ₁₄ than a conventional 11B with a dopant prevent the spread of the tear-time storage node contact junction region for dopant diffusion There is an effect that can prevent the breakdown voltage drop of the device.

Cell Channel Ion Implantation, Decaborene (B10H14), Refresh, Storage Node Contact Junction Area

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view showing a semiconductor device manufacturing method according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Figure 3 is a graph showing the profile of the boron after rapid thermal processing (RTA).

4A and 4B are graphs showing boron diffusion profiles of 49BF ₂ and B ₁₀ H ₁₄ .

DESCRIPTION OF THE REFERENCE NUMERALS

21 semiconductor substrate 22 etch stop film

23 polysilicon film for hard mask 24 antireflection film

25 photoresist pattern 26 channel doped region

27 recess 28 gate insulating film

29 polysilicon film 30 tungsten film

31: gate hard mask RG: recess gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device related to cell channel ion implantation.

As semiconductor devices are highly integrated, the design rule of the device becomes 100 nm or less, and the electric field in the storage node contact region of the cell region is increased due to the increase of the implant doping concentration of the substrate. Due to the increase of junction leakage due to the increase of), the conventional planar transistor structure has a limitation in improving the refresh characteristics.

In order to alleviate this characteristic and increase the gate channel length, a recess gate is introduced, and the introduction of the recess gate can significantly improve the refresh characteristics of the device.

1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1, a predetermined region of the semiconductor substrate 11 is selectively etched to form a recess 12. Then, ion implantation is performed to control the cell channel threshold voltage to form an impurity region under the recess. In this case, 11B or 49BF ₂ is used as the ion for adjusting the cell channel threshold voltage.

However, in devices employing recess gates, storage node contact junctions may occur due to excessive lateral diffusion of dopants due to heat in subsequent processes in the case of 11B or 49BF ₂ dopants during cell channel threshold voltage adjust implantation. The concentration of 11B in (SNC) is increased. As a result, the storage node contact region has a problem in that the refresh is reduced by reducing the breakdown voltage.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device suitable for improving the refresh of the device by reducing the electric field of the storage node contact junction region.

In order to achieve the above object, there is provided a method of manufacturing a semiconductor device of the present invention, the method comprising the steps of injecting decarborene into a channel scheduled region of a semiconductor substrate, diffusing the injected decarborene, the semiconductor substrate to a predetermined depth Etching to form a recess shallower than the depth at which the decaborene is diffused, forming a gate insulating film along the surface of the recess, and filling a portion of the recess on the gate insulating film and the rest Forming a recess gate that protrudes above the surface of the semiconductor substrate.

In addition, the present invention using a boron compound having a mass of at least 11B in a predetermined region of the semiconductor substrate as a dopant, implanting the dopant to form an ion implantation region, by etching a predetermined thickness of the ion implantation region Forming a recess shallower than the depth at which a dopant is diffused, forming a gate insulating film along the recess surface, and partially recessing the recess on the gate insulating film, and the rest over the surface of the semiconductor substrate Forming a protruding recess gate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, an oxide film 22 is formed on the semiconductor substrate 21 as a film for etch stop during etching of the polysilicon film. At this time, the oxide film 22 is formed by dry oxidation or wet oxidation, and has a thickness of 30 to 250 kPa.

Subsequently, a polysilicon film 23 is deposited on the oxide film 22. The polysilicon film 23 is a film to be used as a hard mask during the etching of the recess, and preferably has a thickness of 500 to 2000 GPa. Next, the photoresist pattern 25 is formed on the predetermined region of the polysilicon film 23. In this case, an anti reflection coating layer 24 may be formed under the photoresist pattern 25, and the photoresist pattern 25 serves as a mask for forming a recess.

As shown in FIG. 2B, the anti-reflection film 24 and the polysilicon film 23 are etched by using the photoresist pattern 25 as an etch barrier to expose the oxide film 22. Hereinafter, the etched polysilicon film 23a is abbreviated as a recess hard mask 23a. Meanwhile, when the polysilicon film 23 is etched, a predetermined thickness of the photoresist pattern 25 is lost, so that the height thereof decreases as compared with the height H1> H2 of the photoresist pattern 25 of FIG. 2A. .

As shown in FIG. 2C, after forming the recess hard mask 23a, an ion implantation process for cell channel threshold voltage is performed before stripping the photoresist pattern 25. The channel doping region 26 is formed under the semiconductor substrate 21. Thus, the photoresist pattern 25 is initially adjusted to have a thickness sufficient to serve as an ion implantation barrier.

Decaborene (B ₁₀ H ₁₄ ) is used as a dopant for cell channel threshold voltage regulation. Decaborene is about 10 times heavier than conventional 11B (e.g. 11B is 11, decaboren is about 110), and heavier decarborene is a dopant for cell channel threshold voltage regulation. As a result, the diffusion into the storage node contact junction region SNC can be suppressed when diffusion is performed during the thermal process after implantation of the dopant. Therefore, the electric field of the storage node contact junction region SNC can be reduced, thereby improving the refresh characteristics of the device.

On the other hand, at the time of dopant implantation, the ion implantation energy is 100 KeV to 1MeV, and the dopant dose is 1E11 to 1E15 atoms / cm ₂ .

As shown in FIG. 2D, decaborene is diffused by performing a thermal diffusion process to form a channel doping layer 26a. Hereinafter, the channel doped region 26a in which decarborene is diffused is referred to as a channel doped layer 26a. Since the channel doping layer 26a uses decaborene, which is heavier than 11B, side diffusion is suppressed to the storage node contact junction region (SNC) during thermal diffusion, and the channel doping layer 26a is uniformly formed in the region where the recess gate will be formed. Is formed. And, the diffusion depth is deeper than the subsequent recesses.

As shown in FIG. 2E, after ion implantation for adjusting the cell channel threshold voltage, a strip process is performed to remove the photoresist pattern 25. Subsequently, the anti-reflection film 24 is also removed.

Thereafter, a cleaning process or dry etching is performed to selectively remove the oxide film 22 in the region where the recess is to be formed.

As shown in FIG. 2F, when etching the entire surface using the recess hard mask 23a as an etching barrier, the semiconductor substrate 21 may be held together while the recess hard mask 23a is etched. It is etched to form a recess 27. At this time, the depth of the recess 27 is preferably 500 to 2500 kPa, and the entire surface etching proceeds to the target where the oxide film 22 on the semiconductor substrate 21 is exposed.

As shown in FIG. 2G, after the oxide film 22 is removed by wet etching or dry etching, the gate insulating layer 28 is formed along the surface of the semiconductor substrate 21. Subsequently, a polysilicon film 29 and a tungsten film 30 are sequentially formed on the gate insulating film 28 as a gate conductive film, and a nitride film 31 for a gate hard mask is formed on the tungsten film 30.

Then, a gate patterning process is performed to form a recess gate RG in which the gate insulating film 28, the polysilicon film 29, the tungsten film 30, and the nitride film 31 for a gate hard mask are stacked. Form.

Figure 3 is a graph showing the profile of the boron after the Rapid Thermal Anneal (RTA).

Referring to FIG. 3, the horizontal axis represents depth (unit nm) and the vertical axis represents concentration of dopant (cm ³ ). Here, boron (B ⁺ ) and decaborene (B ₁₀ H _x ⁺ , for example, using B ₁₀ H ₁₄ ) have the same dose (10 ¹⁵ atoms / cm ² ), and boron (B ⁺ ) is 0.5 keV. The ion implantation energy, decaborene (B ₁₀ H ₁₄ ) is injected at 5 keV ion implantation energy. On the other hand, decaborene (B ₁₀ H ₁₄ ) compared with boron (B ⁺ ) is about 3 to 10 times heavier mass and requires more ion implantation energy to inject dopants at the same depth.

After each dopant injection, a rapid thermal process (RTA) is performed at a temperature of 1000 ° C. Herein, when the depth is 10 nm, the degree of diffusion of boron (B ⁺ ) and decaborene (B ₁₀ H ₁₄ ) is similar, but when the depth is 20 nm, boron (B ₁₀ H ₁₄ ) is compared with that of boron (B ₁₀ H ₁₄ ). The spread of ⁺ ) is faster. The concentration of boron (B ^+), when the depth 20㎚ one having carbonyl alkylene higher than the concentration of (B ₁₀ H _14), a deeper depth to be more carbonyl alkylene concentration of (B ₁₀ H ₁₄₎ is rapidly decreased, but the boron The concentration of (B ⁺ ) decreases with decreasing depth. That is, a mass of heat for heavy to carbonyl alkylene (B ₁₀ H ₁₄₎ when thermal processing (RTA) spread and then, constant if the depth or more, the longer the relative mass light with boron (B ⁺⁾ does not diffuse through the It can be seen that the diffusion proceeds to a deeper depth after the diffusion through the process.

4A and 4B are graphs showing boron diffusion profiles of 49BF ₂ and decaborene (B ₁₀ H ₁₄ ).

4A and 4B, the horizontal axis of the graph represents depth (Depth, unit nm), and the vertical axis represents the concentration of boron (cm ³ ). FIG. 4A has a dose of 1E14 and an ion implantation energy of 5 keV. denotes a time when doped with BF _2, Figure 4b illustrates a when having a dose of 1E13 doped with B ₁₀ H ₁₄ with an ion implantation energy of 5keV.

First, in the graphs of FIGS. 4A and 4B, when A is an boron injection, B is annealing boron for 10 seconds at 900 ° C., and C is annealing boron for 10 seconds at a temperature of 1000 ° C. Indicates.

Referring to FIG. 4A, when the depth is shallow, the TD (Thermal Diffusion) value between A and C is small, and as the depth is increased, the TED (Thermal Enhanced Diffusion) value is relatively large.

Referring to the graph of FIG. 4B, when the depth is shallow, the TD value between A and C is large, and as the depth increases, the TED value decreases relatively.

4A and 4B, TD corresponds to a high temperature process and TED corresponds to a low temperature process. In the case of BF ₂ having a relatively small mass compared to B ₁₀ H ₁₄ , the shallow temperature during the low temperature and high temperature processes It can be seen that diffusion is well performed not only at depth (for example, 20 to 40 nm) but also at deep depth (for example, 60 to 80 nm). On the other hand, B ₁₀ H _{14, which} is heavier than BF ₂ , is almost completely diffused at a shallow depth (eg, 20 to 40 nm), and almost no diffusion occurs at a deep depth (eg, 60 to 80 nm). .

As described above, the present invention uses the same conventional method of forming a recess gate after ion implantation used for ion implantation for cell channel threshold voltage adjustment, while using a dopant for ion implantation for cell channel threshold voltage regulation. The heavier decaborene (B ₁₀ H ₁₄ ) can be used to suppress the dopant increase in the storage node contact junction region by subsequent thermal processes, thereby reducing the electric field in the storage node contact junction region. .

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The above-described present invention is re-applied to the access gate, as well as to improve the refreshing effect of the device, the cell threshold voltage adjustment ion implantation when the dopant using a mass of about ten times heavier B ₁₀ H ₁₄ than a conventional 11B with a dopant dopant In the thermal process for diffusion, it is possible to prevent diffusion to the storage node contact junction region and thus prevent a breakdown voltage of the device.

Claims (10)

Injecting decaborene into a channel scheduled region of the semiconductor substrate; Diffusing the injected decarborene; Etching the semiconductor substrate to a predetermined depth to form a recess shallower than the depth at which the decarborene is diffused; Forming a gate insulating film along a surface of the recess; And Forming a recess gate in which the recess is partially embedded on the gate insulating layer and the remaining portion protrudes over the surface of the semiconductor substrate; Wherein the semiconductor device is a semiconductor device. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Injecting the decaborene, Forming a buffer oxide film on the semiconductor substrate; Forming a mask pattern on the buffer oxide layer, the mask pattern having an open portion to open the channel scheduled region; And Ion implanting the decarborene using the mask pattern as an ion implantation barrier Wherein the semiconductor device is a semiconductor device. Claim 3 was abandoned when the setup registration fee was paid. 3. The method of claim 2, Forming the mask pattern, Sequentially forming a polysilicon film, an antireflection film, and a photoresist on the buffer oxide film; Patterning the photoresist with exposure and development to form a photoresist pattern; And Etching the anti-reflection film and the polysilicon film using the photoresist pattern as an etching barrier Wherein the semiconductor device is a semiconductor device. Claim 4 was abandoned when the registration fee was paid. The method of claim 3, The buffer oxide film, Method of manufacturing a semiconductor device by etching through the dry etching or wet etching after the diffusion of the decarborene. Claim 5 was abandoned upon payment of a set-up fee. The method according to any one of claims 1 to 4, The manufacturing method of the semiconductor element inject | poured by the energy of 100 KeV-1MeV and the dose amount of 1E11-1E15 atoms / cm <_2> . Claim 6 was abandoned when the registration fee was paid. The method of claim 5, The step of diffusing the decaborene, Performing a rapid heat process to diffuse the decaborene Method of manufacturing a semiconductor device further comprising. Using a decarborene (B ₁₀ H ₁₄ ) having a mass greater than at least 11B as a dopant in a predetermined region of the semiconductor substrate, and implanting the dopant to form an ion implantation region; Etching a predetermined thickness of the ion implantation region to form a recess shallower than the depth at which the dopant is diffused; Forming a gate insulating film along the recess surface; And Forming a recess gate in which the recess is partially embedded on the gate insulating layer and the remaining portion protrudes over the surface of the semiconductor substrate; Wherein the semiconductor device is a semiconductor device. delete Claim 9 was abandoned upon payment of a set-up fee. The method of claim 7, wherein The dopant is, The manufacturing method of the semiconductor element inject | poured by the energy of 100 KeV-1MeV and the dose amount of 1E11-1E15 atoms / cm <_2> . Claim 10 has been abandoned due to the setting registration fee. 10. The method of claim 9, The dopant, A method of manufacturing a semiconductor device, which is subjected to a rapid thermal process and diffused.

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