KR101148369B1

KR101148369B1 - Stackup type components and manufacturing method thereof

Info

Publication number: KR101148369B1
Application number: KR1020100102789A
Authority: KR
Inventors: 이한
Original assignee: 삼성전기주식회사
Priority date: 2010-10-21
Filing date: 2010-10-21
Publication date: 2012-05-21
Also published as: KR20120041370A

Abstract

The present invention relates to a laminated chip component and a method for manufacturing the same, comprising: a laminate in which a plurality of insulating sheets having a conductive pattern formed of a conductive material are stacked; Pad line patterns disposed on upper and lower portions of the stack; And an external electrode made of a conductive material and coupled to upper and lower portions of the stack. It is configured to include, provides a useful effect that can improve the connectivity of the internal electrode and the external electrode.

Description

Multilayer Chip Component and Manufacturing Method therefor {STACKUP TYPE COMPONENTS AND MANUFACTURING METHOD THEREOF}

The present invention relates to a stacked chip component and a method of manufacturing the same, and more particularly, to a stacked chip component having a padline pattern on the upper and lower portions of the stacked portion to improve connectivity of electrodes inside and outside the stacked chip component, and a method of manufacturing the same. do.

Recently, the utilization of mobile devices is rapidly increasing, and various demands are generated as the utilization is increased. For example, the screen is larger, the sharper picture quality, the need to process a large amount of data, as well as the need to implement faster operation and processing speed is increasing.

Therefore, because data must be processed and transmitted at high speed, the frequency band used for data transmission has shifted to higher and higher frequencies, and thus the use of high-frequency beads has been expanded to solve problems caused by noise at high frequencies. It is becoming.

Meanwhile, the conventional bead is implemented as a multilayer inductor. Since the conventional multilayer inductor has a vertical shape in the direction of the inner coil and the length of the chip, the self resonant frequency is caused by the floating capacitance between the internal and external electrodes. ; SRF) characteristics were limited.

FIG. 1 illustrates a conventional bead configuration. As illustrated in the drawing, since the stacking direction of the coil 3 and the coupling direction of the external electrode 1 are perpendicular to each other, the SRF value is low. Difficult to use as a high frequency bead.

On the other hand, in order to solve the above problems, a bead for high frequency as illustrated in Figure 2 has been proposed.

Referring to FIG. 2, the stacking direction of the coil 3 and the coupling direction of the external electrode 1 are perpendicular to each other. Thus, since the parasitic capacitance between the internal electrode 5 and the external electrode 1 is minimized, the SRF value is minimized. This increases and the noise reduction area is widened.

However, the conventional high-frequency beads have a problem that the internal electrode is exposed during the manufacturing process and damage occurs during the process, thereby deteriorating the connection between the internal electrode and the external electrode.

The present invention, which was devised to solve the above problems, is further provided with a pad line pattern, and an object of the present invention is to provide a multilayer chip component and a method of manufacturing the same, which improves the connectivity between the internal electrode and the external electrode of the multilayer chip component. do.

According to an aspect of the present invention, there is provided a stacked chip component including: a stacking unit including a plurality of insulating sheets having a conductive pattern formed of a conductive material; Pad line patterns disposed on upper and lower portions of the stack; And an external electrode made of a conductive material and coupled to upper and lower portions of the stack. .

At this time, the pad line pattern is preferably made entirely of only a conductive material.

In addition, the lamination part may include internal electrodes connected from the uppermost conductive pattern provided in the lamination part to the upper surface of the lamination part and from the lowermost conductive pattern to the lower surface of the lamination part. It is preferred to be electrically connected.

In addition, the pad line pattern and the external electrode may be electrically connected to upper and lower surfaces and / or side surfaces of the stack.

In addition, the stacked chip component may be a high frequency chip inductor.

According to one or more exemplary embodiments, a method of manufacturing a stacked chip component includes: providing a conductive pattern on an insulating sheet; Stacking an insulating sheet provided with the conductor pattern to form a laminate; Pressing the laminate; Cutting the compressed laminate; Calcining and firing the cut laminate; And coupling an external electrode to the calcined and fired lamination portion, wherein the forming of the lamination portion includes a process of providing pad line patterns on upper and lower portions of the lamination portion.

The method may further include filling vias with a conductive material by forming via holes in the upper and lower surfaces of the stack between the forming of the stack and cutting the stack.

In addition, the pad line pattern and the external electrode may be electrically connected to the upper, lower and / or side surfaces of the stack.

In this case, the multilayer chip component may be a high frequency chip inductor.

The present invention configured as described above provides a stacked chip component capable of minimizing damage to an internal electrode, thereby providing a useful effect of improving the connection between the internal electrode and the external electrode of the stacked chip component.

1 is a perspective view and a cross-sectional view showing a configuration of a conventional general bead,
2 is a perspective view and a cross-sectional view showing a configuration of a conventional high frequency bead;
3 is a perspective view and a cross-sectional view showing the configuration of a stacked chip component according to the present invention;
4 is a flowchart illustrating a method of manufacturing a stacked chip component according to the present invention.

The advantages and features of the present invention and the techniques for achieving them will be apparent from the following detailed description taken in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. The present embodiments are provided so that the disclosure of the present invention is not only limited thereto, but also may enable others skilled in the art to fully understand the scope of the invention. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, 'comprise' and / or 'comprising' refers to a component, step, operation and / or element that is mentioned in the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Hereinafter, with reference to the accompanying drawings will be described in more detail the configuration and operation of the present invention.

3 is a perspective view and a cross-sectional view showing the configuration of a stacked chip component 100 according to the present invention.

Referring to FIG. 3, the stacked chip component 100 may include a stack 120, a pad line pattern 150, and an external electrode 110.

The stacking unit 120 may be formed by stacking a plurality of insulating sheets provided with a conductive pattern 130 formed of a conductive material.

In this case, various metals may be used as the conductive material, and the insulating sheet serves as a kind of substrate, and may be implemented with materials such as ferrite and ceramics.

Meanwhile, as a method of forming the conductor pattern 130 on the insulating sheet, plating or printing may be applied.

The external electrode 110 may be formed of a metal plate such as copper, aluminum, and the like, which is coupled to an upper portion and a lower portion of the laminated portion 120 to form a conductor pattern 130 provided inside the laminated portion 120. It serves as an electrical connection.

The pad line pattern 150 is provided on the upper and lower portions of the stacking part 120.

The stacking unit 120 is formed by stacking an insulating sheet on which the conductive pattern 130 is formed. In this stacking process, layers having only conductive materials on all sides of the stacking layer 120 are formed on the upper and lower portions of the stacking unit 120, respectively. The pad line pattern 150 may be formed by providing the pad line pattern 150.

In this case, the pad line pattern 150 may be positioned on the top and bottom surfaces of the stacking unit 120 to be directly exposed to the outside, but additionally includes an insulating sheet on the top or bottom surface of the pad line pattern 150. The pad line pattern 150 may not be directly exposed.

The stack 120 may be provided with an internal electrode 140 electrically connected to the conductor pattern 130 and exposed to the top and bottom surfaces of the stack 120.

The internal electrode 140 may be implemented by drilling a via hole or the like after completion of lamination and filling a conductive material in the via hole.

In addition, similar to the other conductive patterns 130, the internal electrode 140 may also be embodied by printing or plating on an insulating sheet, and may be electrically connected to the upper and lower layers by using vias.

Hereinafter, a method of manufacturing the stacked chip component 100 according to the present invention will be described in detail.

4 is a flowchart illustrating a method of manufacturing a stacked chip component 100 according to the present invention.

Referring to FIG. 4, the method for manufacturing a stacked chip component 100 according to the present invention may include forming a stacked portion 120 including a conductor pattern 130 (S100) and a pad line pattern 150 (S110), and crimping ( S120, cutting 130, plasticizing and firing 140 and the external electrode 110 may be configured to include (S150) step.

The step of providing the conductor pattern 130 (S100) may be implemented by selectively printing or printing a conductive material on the insulating sheet.

In the forming of the stacking unit 120 including the pad line pattern 150 (S110), the insulating sheets on which the conductor pattern 130 is formed are stacked, and the pad line pattern 150 layer is disposed on the uppermost layer or a lower layer thereof. By laminating and laminating a padline pattern 150 layer on a lowermost layer or an upper layer thereof.

In this case, it is preferable to form the internal holes 140 by filling the conductive material by forming via holes in the upper and lower surfaces of the stack 120 before the cutting process after forming the stack 120.

In addition, as described above, the internal electrode 140 may be implemented by stacking an insulating sheet on which a conductive pattern is formed.

Meanwhile, a series of manufacturing methods including printing, laminating, pressing, cutting, sintering, firing, and bonding the external electrode 110 of the conductive pattern 130 may be performed by a method similar to a multilayer chip manufacturing process, which is already widely used. The description is omitted.

According to the present invention configured as described above, since the internal electrode 140 is exposed to the outside and is not damaged during the lamination and compression process, the connection between the internal electrode 140 and the external electrode 110 when the external electrode 110 is combined is not damaged. Is improved.

Meanwhile, the pad line pattern 150 may serve to protect the internal electrode 140, and at the same time, the pad line pattern 150 may be directly connected to the external electrode 110. Referring to FIG. 3, the external electrode is coupled to the upper surface of the stack, but has an extension 111 extending to the side of the stack in order to improve the bonding force and widen the connection position selection when connecting to another product. The pad line pattern 150 may be electrically connected to the extension part 111 to increase connectivity between internal and external electrodes.

The multilayer chip component may be applied to any component manufactured by a stacked method, and particularly, when the multilayer chip component is applied to a multilayer chip inductor or a bead for high frequency, the effect may be maximized.

The foregoing detailed description is illustrative of the present invention. In addition, the foregoing description merely shows and describes preferred embodiments of the present invention, and the present invention can be used in various other combinations, modifications, and environments. That is, it is possible to make changes or modifications within the scope of the concept of the invention disclosed in this specification, the disclosure and the equivalents of the disclosure and / or the scope of the art or knowledge of the present invention. The above-described embodiments are for explaining the best state in carrying out the present invention, the use of other inventions such as the present invention in other state known in the art, and the specific fields of application and uses of the present invention. Various changes are also possible. Accordingly, the detailed description of the invention is not intended to limit the invention to the disclosed embodiments. Also, the appended claims should be construed to include other embodiments.

10: conventional common bead
1: external electrode
2: laminated part
3: coil
4, 5: internal electrode
20: conventional high frequency beads
100: Stacked Chip Parts
110: external electrode
111: extension part
120: laminated part
130: conductor pattern
140: internal electrode
150: pad line pattern

Claims

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A stacking unit including a plurality of insulating sheets having a conductive pattern formed of a conductive material stacked thereon;
Internal electrodes connecting the uppermost conductive pattern provided in the stack to the top surface of the stack and the bottom conductor pattern to the bottom surface of the stack;
Pad line patterns provided on upper and lower portions of the stack and electrically connected to the internal electrodes; And
An external electrode made of a conductive material and coupled to upper and lower portions of the stack;
Containing
Stacked Chip Components.

A stacking unit including a plurality of insulating sheets having a conductive pattern formed of a conductive material stacked thereon;
Pad line patterns disposed on upper and lower portions of the stack; And
An external electrode made of a conductive material and coupled to upper and lower portions of the stack;
Including;
The pad line pattern and the external electrode are configured to be electrically connected to upper and lower surfaces and / or side surfaces of the stack.
Stacked Chip Components.

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Providing a conductive pattern on the insulating sheet;
Stacking an insulating sheet provided with the conductor pattern to form a laminate;
Pressing the laminate;
Cutting the compressed laminate;
Calcining and firing the cut laminate; And
Coupling an external electrode to the calcined and fired laminate;
Including;
The forming of the stacking unit may include providing pad line patterns on the upper and lower portions of the stacking unit.
And forming a via hole in the upper and lower surfaces of the laminate to fill the conductive material between the forming of the laminate and cutting the laminate.
Manufacturing method of stacked chip component.

Providing a conductive pattern on the insulating sheet;
Stacking an insulating sheet provided with the conductor pattern to form a laminate;
Pressing the laminate;
Cutting the compressed laminate;
Calcining and firing the cut laminate; And
Coupling an external electrode to the calcined and fired laminate;
Including;
The forming of the stacking unit may include providing pad line patterns on the upper and lower portions of the stacking unit.
The pad line pattern and the external electrode are configured to be electrically connected to upper and lower surfaces and / or side surfaces of the stack.
Manufacturing method of stacked chip component.

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