KR101146470B1 - An array substrate for Liquid Crystal Display device and the method for fabricating the same - Google Patents

Abstract

Disclosed are an array substrate for a liquid crystal display device and a method of manufacturing the same for preventing distortion of a transverse electric field generated between a common electrode and a pixel electrode.

An array substrate for an LCD device according to an embodiment of the present invention includes a gate line and a data line arranged vertically and horizontally to define a pixel region, a thin film transistor formed at an intersection of the gate line and the data line, and within the pixel region. At least one pair of common electrodes and pixel electrodes for generating a transverse electric field, and storage electrodes overlapping upper and lower ends of the gate line and electrically connected to the pixel electrodes.

Transverse field, storage electrode, gate line

Description

An array substrate for liquid crystal display device and the method for fabricating the same}

1 is a plan view showing a part of a conventional array substrate for a liquid crystal display device.

2 is a plan view showing a part of another conventional array substrate for a liquid crystal display device.

3 is a view showing an array substrate for a liquid crystal display device according to the present invention;

4A is a view taken along the line II ′ of the array substrate of FIG. 3.

4B is a view taken along the line II-II 'of the array substrate of FIG.

FIG. 4C is a view of the array substrate of FIG. 3 taken along III-III '. FIG.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

100: array substrate 101: glass substrate

112: gate line 113: gate insulating film

114: gate electrode 116: storage electrode

116a: first storage electrode 116b: second storage electrode

116c: third storage electrode 117a: first common electrode

117b: second common electrode 120: active layer

124: data line 126: source electrode

128: drain electrode 130: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device and a method of manufacturing the same, which minimize distortion of a transverse electric field generated between a common electrode and a pixel electrode.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal.

Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

1 is a plan view showing a part of a conventional array substrate for a liquid crystal display device.

As illustrated in FIG. 1, the array substrate 10 for a liquid crystal display device includes a plurality of gate lines 12 arranged in one direction in parallel with a predetermined interval, and the gate lines 12 and the pixel region P. As shown in FIG. The data line 24 is defined.

The thin film transistor T including the gate electrode 14, the active layer 20, the source electrode 26, and the drain electrode 28 is formed at the intersection of the gate line 12 and the data line 24. The source electrode 26 is connected to the data line 24 and the gate electrode 14 is connected to the gate line 12. The data line 24 is zigzag.

The pixel electrode 30 connected to the drain electrode 28 and the first and second common electrodes 17a and 17b formed in parallel with the pixel electrode 30 are formed on the pixel region P. do.

The first common electrode 17a is formed on the pixel region P in parallel with the data line 24, and the second common electrode 17b is formed in parallel with the gate line 12. . In addition, the first common electrode 17a is zigzag together with the data line 24, and a plurality of first common electrodes 17a are formed on one pixel area P.

In this case, the first common electrode 17a is arranged up and down symmetrically with respect to the second common electrode 17b and is connected to each other.

The pixel electrodes 30 are arranged in a zigzag shape in a vertical symmetry with respect to the second common electrode 17b. The pixel electrode 30 extends above the front gate line to form the storage electrode 16.

The storage structure may be configured as a hybrid storage structure (not shown) applying both a storage on gate and a storage on common.

The storage electrode 16 spans the lower end of the gate line 12, as shown at A. A gate insulating layer (not shown) is formed over the gate line 12 to insulate the gate line 12 from the storage electrode 16.

The storage electrode 16 cuts off the electric fields of the gate voltage supplied to the gate line 12, that is, the gate high voltage VGH and the gate low voltage VGL, thereby blocking the pixel electrode 30 and the first and second electrodes. The transverse electric field generated between the common electrodes 17a and 17b is prevented from being distorted.

The storage electrode 16 is positioned at the lower end of the gate line 12, so that the electric field of the gate voltage supplied to the upper end of the gate line 12 can not be blocked. As a result, a gate electric field is generated at a portion of the gate line 12 where the storage electrode 16 is not present, and thus the transverse electric field generated between the pixel electrode 30 and the first and second common electrodes 17a and 17b. It will cause distortion.

2 is a plan view showing a part of another conventional array substrate for a liquid crystal display device.

As shown in FIG. 2, the array substrate 20 has a plurality of gate lines 22 arranged in one direction at regular intervals to define the pixel region P, and is perpendicular to the gate line 22. The plurality of data lines 34 are arranged at regular intervals in the direction.

At the intersection of the gate line 22 and the data line 34, a thin film transistor T including a gate electrode 24, an active layer 30, a source electrode 36, and a drain electrode 38 is formed. The source electrode 36 is connected to the data line 24, and the gate electrode 24 is connected to the gate line 22.

The pixel electrode 40 connected to the drain electrode 38 and the first and second common electrodes 27a and 27b formed in parallel with the pixel electrode 40 are formed on the pixel region P. do.

Parts identical to those described above will be omitted.

The first common electrode 27a is vertically symmetrical with respect to the second common electrode 27b and is connected to each other.

The pixel electrode 40 is arranged in a zigzag shape in a vertical symmetry with respect to the second common electrode 27b. The pixel electrode 40 extends above the front gate line to form the storage electrode 26.

As illustrated in B, the storage electrode 26 overlaps the gate line 22. As a result, the storage electrode 26 can block an electric field of the gate voltage supplied to the gate line 22, that is, the gate high voltage VGH and the gate low voltage VGL. As a result, distortion of the transverse electric field generated between the first and second common electrodes 27a and 27b and the pixel electrode 40 can be minimized.

On the other hand, when the storage electrode 26 overlaps the gate line 22 to block the gate voltage, the storage electrode 26 affects the gate voltage supplied to the gate line 22 due to a gate load or the like. .

That is, when the storage electrode 26 overlaps the gate line 22 and is formed on the gate line 22, the gate load is increased due to an increase in the area of the storage electrode 26.

As a result, when the storage electrode 26 overlaps the gate line 22, the transverse electric field generated between the first and second common electrodes 27a and 27b and the pixel electrode 40 is affected. However, increasing the gate load affects the gate voltage supplied to the gate line 22.

An object of the present invention is to provide an array substrate for a liquid crystal display device and a method of manufacturing the same, which minimizes the area of the storage electrode without distorting the transverse electric field generated between the common electrode and the pixel electrode.

According to an exemplary embodiment of the present invention, an array substrate for a liquid crystal display device includes a gate line and a data line arranged vertically and horizontally to define a pixel region, and a thin film transistor formed at an intersection point of the gate line and the data line. And at least one pair of common electrodes and pixel electrodes for generating a transverse electric field in the pixel area, and storage electrodes overlapping upper and lower ends of the gate line and electrically connected to the pixel electrodes.

According to another aspect of the present invention, an array substrate for a liquid crystal display device includes a first metal layer having a gate line and a gate electrode, a second metal layer and a pixel electrode having a data line and a common electrode, and the pixel electrode. And a third metal layer formed to extend and overlap the upper and lower plates of the gate line to overlap the storage electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: forming a gate line and a gate electrode on a lower substrate; Forming a data line and a common electrode defining a pixel region, forming a pixel electrode on the pixel region, and forming a storage electrode that overlaps the upper and lower ends of the gate line and overlaps the pixel electrode; It includes a step.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including forming a gate line and a gate electrode on a lower substrate, and crossing the gate line perpendicularly to the plurality of pixels. Forming a data line defining a region, forming a common electrode and a pixel electrode on the pixel region, and forming a storage electrode extending from the pixel electrode and overlapping the upper and lower ends of the gate line; Steps.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

3 is a view showing an array substrate for a liquid crystal display device according to the present invention.

As shown in FIG. 3, the array substrate 100 has a plurality of gate lines 112 arranged in one direction at regular intervals to define the pixel region P, and is perpendicular to the gate line 112. Direction, a plurality of data lines 124 are arranged at regular intervals.

In this case, the data line 124 has a zigzag shape that is bent at least once in the longitudinal direction of one pixel area P. FIG. The gate line 112 and the data line 124 intersect to define the pixel region P, and a thin film transistor T is formed in each cross region.

The thin film transistor T may include a gate electrode 114 protruding from the gate line 112, a gate insulating film (not shown) formed on an entire surface thereof, and a gate insulating film (not shown) above the gate electrode 114. The active layer 120 formed over the source layer, the source electrode 126 protruding from the data line 124, and the source electrode 126 at regular intervals and are integrally formed with the pixel electrode 130. The drain electrode 128 is formed.

In addition, first and second common electrodes 117a and 117b are formed on the same layer as the data line 124, and the first common electrode 117a is zigzag in parallel with the data line 124. A plurality of pixels are formed in one pixel area, and the second common electrode 117b is formed to cross the pixel area P in parallel with the gate line 112.

In this case, the first common electrode 117a is arranged up and down symmetrically with respect to the second common electrode 117b and is connected to each other. The pixel region P defined by the intersection of the gate line 112 and the data line 124 has a zigzag shape in parallel with the first common electrode 117a, and the second common electrode 117b at regular intervals. The pixel electrode 130 is arranged between them.

In this case, the pixel electrode 130 is also arranged in a zigzag shape up and down symmetrically with respect to the second common electrode 117b.

The pixel electrode 130 and the first and second common electrodes 117a and 117b may be formed on the same layer.

In addition, the pixel electrode 130 contacts the active region 120 of the thin film transistor T to form the drain electrode 128 through a drain contact hole (not shown). The pixel electrode 130 extends to the upper end of the front gate line to form the storage electrode 116.

The storage structure may be configured as a hybrid storage structure (not shown) applying both a storage on gate and a storage on common.

Although not illustrated, the second common electrode 117b is not formed to cross the pixel region P, but may be disposed outside the pixel region adjacent to the gate line 112. In this case, the first common electrode 117a and the pixel electrode 130 are not formed symmetrically about the second common electrode 117b, but are bent at least once in a zigzag shape in the pixel region P parallel to each other. .

Liquid crystals (not shown) positioned between the first common electrode 117a and the pixel electrode 130 are arranged in the same direction by a transverse electric field distributed between the first common electrode 117a and the pixel electrode 130. It forms one domain. In the transverse electric field system having the above configuration, since a plurality of multi-domains can be configured in a single pixel region P, a liquid crystal display having a wider viewing angle can be manufactured.

A transverse electric field is generated between the first common electrode 117a and the pixel electrode 130. The first common electrode 117a and the pixel electrode 130 are formed on a lower substrate (not shown).

The common voltage Vcom, which is a constant DC voltage, is supplied to the first common electrode 117a, and a data voltage converted to analog is supplied to the pixel electrode 130. The transverse electric field is generated by the potential difference between the data voltage supplied to the pixel electrode 130 and the common voltage Vcom supplied to the first common electrode 117a.

The gate line 112 is supplied with a gate voltage, that is, a gate high voltage VGH and a gate low voltage VGL. The gate voltage means a high or low voltage value. Therefore, the gate voltage affects the transverse electric field generated between the first common electrode 117a and the pixel electrode 130 on the pixel region P.

That is, the transverse electric field generated between the first common electrode 117a and the pixel electrode 130 is distorted due to the potential of the gate high voltage VGH and the gate low voltage VGL supplied to the gate line 112. do. As the transverse electric field is distorted, the quality of the image quality of the liquid crystal display is degraded.

In order to prevent distortion of a transverse electric field generated between the first common electrode 117a and the pixel electrode 130, the storage electrode 116 formed by extending the pixel electrode 130 is connected to the gate line 112. Form so as to overlap.

The storage electrode 116 overlaps the gate line 112 and the gate voltage supplied to the gate line 112, that is, the gate high voltage VGH and the gate low voltage VGL, is applied to the first common electrode 117a. ) And the transverse electric field generated between the pixel electrode 130 and the pixel electrode 130.

In the case of a conventional array substrate for a liquid crystal display device, a storage capacitor is formed to overlap the gate line in order to prevent distortion of the transverse electric field generated between the common electrode and the pixel electrode.

As the storage electrode overlaps the gate line, the storage electrode affects the gate voltage supplied to the gate line, that is, the gate high voltage VGH and the gate low voltage VGL.

That is, as the storage electrode overlaps the gate line, an area in which the storage electrode overlaps with the gate line increases, thereby increasing the load of the gate line. This influences the gate voltages supplied to the gate line.

In order to solve this problem, in the array substrate 100 for a liquid crystal display device of the present invention, the storage electrode 116 is manufactured in an “I” shape.

The storage electrode 116 has a "I" shape, such as C. Thus, the storage electrode 116 overlaps the gate line 112 and minimizes an area overlapping the gate line 112.

The storage electrode 116 may be formed on the upper and lower ends of the gate line 112 to block electric fields of the gate high voltage VGH and the gate low voltage VGL supplied to the gate line 112.

In addition, as illustrated in FIG. 3, the storage electrode 116 has an “I” shape while minimizing an overlapping area on the gate line 112 to supply the gate voltage to the gate line 112. Minimized their impact.

As a result, the “I” shaped storage electrode 116 prevents distortion of the transverse electric field generated between the first common electrode 117a and the pixel electrode 130 and reduces the gate load of the gate line 112. Minimize the role.

4A is a view taken along the line II ′ of the array substrate of FIG. 3.

As shown in FIG. 4A, a gate line 112 is formed over the transparent glass substrate 101, and a gate insulating layer 113 is formed on the gate line 112. The first storage electrode 116a is formed on a portion of the gate insulating layer 113.

The first storage electrode 116a refers to a portion that is displayed by cutting the center portion of the “I” shaped storage electrode 116.

4B is a view taken along the line II-II 'of the array substrate of FIG.

As shown in FIG. 4B, the gate line 112 is formed on the entire surface of the transparent glass substrate 101, and the gate insulating layer 113 is formed on the entire surface of the gate line 112. The second storage electrode 116b is formed on the entire surface of the gate insulating layer 113.

The second storage electrode 116b refers to a portion cut out based on the upper end of the “I” shaped storage electrode 116. In addition, the second storage electrode 116b is the same as a portion obtained by cutting the lower end of the “I” shaped storage electrode 116.

FIG. 4C is a diagram illustrating the array substrate of FIG. 3 taken along III-III '.

As shown in FIG. 4C, the gate line 112 is formed on the entire surface of the transparent glass substrate 101, and the gate insulating layer 113 is formed on the entire surface of the gate line 112. Third storage electrodes 116c are formed at both ends of the gate insulating layer 113 except for the center portion.

The third storage electrode 116c refers to a portion formed by vertically cutting the storage electrode 116 having an “I” shape.

The first common electrode 117a and the pixel electrode 130 are formed by the “I” shaped storage electrode 116 including the first, second, and third storage electrodes 116a, 116b, and 116c. It is possible to prevent distortion of the transverse electric field generated in between, and to minimize the gate load of the gate line 112.

Upper and lower ends of the “I” shaped storage electrode 116 overlap the gate line 112, and a central portion thereof is narrowly connected to overlap the gate line 112.

The array substrate 100 for a liquid crystal display according to the present invention includes a storage electrode 116 having an “I” shape in order to prevent distortion of a transverse electric field generated between the first common electrode 117a and the pixel electrode 130. Is formed to overlap the gate line 112. In this case, the storage electrode 116 minimizes an area overlapping with the gate line 112 to minimize the gate load of the gate line 112.

Upper and lower ends of the storage electrode 116 span the gate line 112, and a central portion of the storage electrode 116 extends narrowly and overlaps the gate line 112.

Accordingly, the storage electrode 116 blocks the gate voltage supplied to the gate line 112 to prevent distortion of the transverse electric field generated between the first common electrode 117a and the pixel electrode 130 and the gate The area overlapping with the line 112 may be minimized to minimize the gate load of the gate line 112.

As mentioned above, the array substrate for a liquid crystal display according to the present invention can minimize the distortion of the transverse electric field generated between the common electrode and the pixel electrode and minimize the gate load of the gate line.

The array substrate for a liquid crystal display according to the present invention forms a storage electrode having an “I” shape to block an electric field of the gate voltage supplied to the gate line, thereby preventing distortion of the transverse electric field generated between the common electrode and the pixel electrode. The gate rod may be minimized by minimizing the overlapping portion of the storage electrode on the gate line.

Claims (9)

Gate lines and data lines arranged vertically and horizontally to define pixel areas; A thin film transistor formed at the intersection of the gate line and the data line; At least one pair of common electrodes and pixel electrodes generating a transverse electric field in the pixel region; And A storage electrode extending from the pixel electrode and overlapping the gate line; And the storage electrode has an " I " shape in which an area overlapping with each of an upper end and a lower end of the gate line is larger than an area overlapping with a center part of the gate line. delete The method of claim 1, The thin film transistor, A gate electrode; A gate insulating film formed on the gate electrode; A semiconductor layer formed on the gate insulating film; And And a source electrode and a drain electrode formed on the semiconductor layer. A first metal layer having a gate line and a gate electrode formed thereon; A second metal layer on which data lines and a common electrode are formed; And And a third metal layer extending from the pixel electrode and the pixel electrode to form a storage electrode overlapping the gate line. And the storage electrode has an " I " shape in which an area overlapping with each of an upper end and a lower end of the gate line is larger than an area overlapping with a center part of the gate line. delete Forming a gate line and a gate electrode on the lower substrate; Forming a data line and a common electrode defining a plurality of pixel regions crossing the gate line perpendicularly to the gate line; Forming a pixel electrode on the pixel region; And Forming a storage electrode extending from the pixel electrode and overlapping the gate line; And the storage electrode has an " I " shape in which an area overlapping each of an upper end and a lower end of the gate line is larger than an area overlapping with a center part of the gate line. delete Forming a gate line and a gate electrode on the lower substrate; Forming a data line crossing the gate line to define a plurality of pixel regions; Forming a common electrode and a pixel electrode on the pixel region; And Forming a storage electrode extending from the pixel electrode and overlapping the gate line; And the storage electrode has an " I " shape in which an area overlapping each of an upper end and a lower end of the gate line is larger than an area overlapping with a center part of the gate line. delete

Images