KR101146319B1 - Semiconductor chip supplying Method of bonder - Google Patents

Semiconductor chip supplying Method of bonder Download PDF

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Publication number
KR101146319B1
KR101146319B1 KR1020060032641A KR20060032641A KR101146319B1 KR 101146319 B1 KR101146319 B1 KR 101146319B1 KR 1020060032641 A KR1020060032641 A KR 1020060032641A KR 20060032641 A KR20060032641 A KR 20060032641A KR 101146319 B1 KR101146319 B1 KR 101146319B1
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South Korea
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wafer
alignment
semiconductor chip
frame
wafer frame
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KR1020060032641A
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Korean (ko)
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KR20070101519A (en
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이기빈
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삼성테크윈 주식회사
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention provides a semiconductor chip supply method of a bonder for supplying a semiconductor chip on a wafer fixed to a wafer frame to a semiconductor chip bonding section. The provided semiconductor chip supply method of the bonder includes a mounting step of placing the magazine on which the wafer frame is loaded in the wafer loader and a step of aligning the alignment points of the respective semiconductor chips on the wafer fixed to the wafer frame A loading step of loading the wafer frame of the wafer loader into the wafer stage, a step of calculating the alignment value of the wafer frame through the pre-taught alignment points and rotating the wafer stage in accordance with the calculated alignment value, A compensating step of compensating the alignment positions of each of the semiconductor chips previously taught by reflecting the rotation value of the wafer stage, a semiconductor chip aligning step of aligning the semiconductor chips with the compensated alignment positions, And a pickup step of picking up the aligned semiconductor chips.

Description

Technical Field [0001] The present invention relates to a method of supplying a semiconductor chip to a bonder,

1 is a schematic view showing a flip chip bonder according to the present invention.

Fig. 2 is a plan view of the wafer frame shown in Fig. 1 and the wafer fixed thereon.

3 is an enlarged view of the semiconductor chip shown in Fig.

4 is a flowchart showing an embodiment of a method of supplying a semiconductor chip according to the present invention.

5 is a flowchart showing the wafer frame aligning method of FIG.

6 is a flowchart showing the semiconductor chip alignment method of FIG.

DESCRIPTION OF REFERENCE NUMERALS

100: Flip chip bonder

110: Wafer loader

130: Wafer stage

140: vision camera

160: Flip head

180: bonding head

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonder for bonding a semiconductor chip, and more particularly, to a method of supplying a semiconductor chip to a bonder for supplying the semiconductor chip so that the semiconductor chip is bonded.

Generally, a bonder for bonding a semiconductor chip includes a die bonder, a wire bonder, and a flip chip bonder. Normally, the die bonder and the wire bonder are used continuously, and the flip chip bonder is used separately.

Specifically, the die bonder refers to a device for bonding a semiconductor chip (also referred to as a " die ") manufactured by a semiconductor chip manufacturing process to a printed circuit board or the like, and the wire bonder includes an electrode of a semiconductor chip bonded by a die bonder, Refers to a device for bonding leads formed on a substrate to each other with wires such as gold wires. The flip chip bonder may be formed by forming a solder bump on a pad which is an input / output terminal of a semiconductor chip and then turning the semiconductor chip upside down to form a circuit pattern such as a carrier substrate or a circuit tape (Pattern).

In order to smoothly perform the bonding operation of the semiconductor chips by the bonders, the semiconductor chips must be accurately supplied. Particularly, in the case of a flip chip bonder in which these semiconductor chips are directly bonded to a circuit pattern such as a carrier substrate or a circuit tape together with the supply of semiconductor chips, more accurate supply work must be performed.

Therefore, the conventional flip chip bonder does not directly pick up and supply the semiconductor chips positioned in the pre-taught position, but rather, deflects the semiconductor chips positioned in the pre-taught position before proceeding with the pick-up operation, And before aligning each of the semiconductor chips provided on the wafer, the wafer frame fixing the wafer is entirely aligned to correct the position of the wafer frame by this alignment value.

However, since the conventional flip chip bonder aligns the wafer including the respective semiconductor chips together with the wafer frame before aligning the respective semiconductor chips, and corrects the position of the wafer and the wafer frame according to the alignment value When correcting the position of the wafer and the wafer frame and then aligning the semiconductor chips mounted on the wafer with a vision camera or the like in accordance with a value previously taught, the semiconductor chips provided on the wafer are largely deviated from the pre- A vision camera or the like can not align the semiconductor chips provided on the wafer, that is, a vision alignment error occurs.

Particularly, in recent years, the sizes of semiconductor chips have been gradually decreasing, and vision cameras for aligning the semiconductor chips have been increasing in size with the trend of the size of semiconductor chips, and also in the field of view (FOV) area is reduced, and thus the vision-aligned error described above occurs more frequently.

Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of supplying a semiconductor chip of a bonder that minimizes occurrence of a vision error.

According to another aspect of the present invention, there is provided a semiconductor chip supply method for supplying a semiconductor chip on a wafer fixed to a wafer frame to a semiconductor chip bonding section.

The semiconductor chip supply method of the bonder includes a mounting step of placing the magazine on which the wafer frame is loaded on the wafer loader, a step of teaching the alignment points of the respective semiconductor chips on the wafer fixed to the wafer frame and the alignment points of the wafer frame A loading step of loading the wafer frame of the wafer loader into the wafer stage, a step of calculating the alignment value of the wafer frame through the pre-taught alignment points and rotating the wafer stage in accordance with the calculated alignment value, A compensating step of compensating the alignment positions of each of the semiconductor chips previously taught by reflecting the rotation value of the wafer stage, a semiconductor chip aligning step of aligning the semiconductor chips with the compensated alignment positions, And a pickup step of picking up the aligned semiconductor chips.

In another embodiment, the wafer-frame aligning step includes moving the wafer frame to a position where the wafer stage is pre-taught so that the vision camera will locate a first alignment point of the wafer frame, A step of moving the wafer frame to a position where the wafer stage is pre-taught to find a second alignment point of the wafer frame, and a step of moving the wafer frame to a second alignment Moving the wafer frame to a position where the wafer stage is pre-taught to locate the third alignment point of the wafer frame; and finding the third alignment point of the wafer frame by the vision camera The first alignment point of the found wafer frame, and the second alignment The X-axis rotation value of the wafer frame is calculated by using the second and third alignment points of the detected wafer frame, and the Y-axis rotation value of the wafer frame is calculated. Calculating the rotation value of the wafer stage using the calculated Y-axis rotation value, and rotating the wafer stage by the rotation value calculated using the wafer stage rotation motor.

In yet another embodiment, the teaching step may further comprise teaching alignment patterns of the respective semiconductor chips on the wafer and an alignment order of each of the semiconductor chips on the wafer.

In another embodiment, the semiconductor chip aligning step may include aligning the alignment position of the wafer stage to the alignment position of the semiconductor chip to which the wafer stage is pre-aligned so as to locate the first alignment pattern of the semiconductor chip to be picked up, Shifting the wafer frame to reflect the / Y transition value; and finding a first alignment pattern within the viewing angle of the vision camera, and determining a second alignment pattern of the semiconductor chip to which the vision camera is to be picked Moving the wafer frame to reflect an X / Y variation value due to rotation of the wafer stage to an alignment position of a semiconductor chip to which the wafer stage has been previously taught, and moving the wafer frame to a second alignment pattern Calculating a center point of the semiconductor chip using the two alignment patterns found; The emitter point so the chip pick-up position of the wafer stage may include the step of moving the wafer frame.

In another embodiment, the aligning of the semiconductor chips may further include a step of further extending the viewing angle to a predetermined size if the alignment patterns are not found within the viewing angle of the vision camera, and then searching for the alignment patterns again.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals designate like elements throughout the specification.

FIG. 1 is a schematic view showing a flip chip bonder according to the present invention, FIG. 2 is a plan view of the wafer frame shown in FIG. 1 and a wafer fixed thereon, and FIG. 3 is an enlarged view of the semiconductor chip shown in FIG.

1 to 3, a flip chip bonder 100 according to the present invention includes a wafer loader 110, a wafer stage 130, a vision camera 140, a flip head 160, and a bonding head 180).

Specifically, a magazine 90 having a plurality of wafer frames 80 mounted thereon is mounted on the wafer loader 110. The magazine 90 is formed in a box type so that a plurality of wafer frames 80 are stacked in a vertical direction. The wafer frame 80 serves to fix the wafer 70 to its upper surface through an adhesive tape (not shown) or the like. At this time, the wafer frame 80 is formed so as to support only the edge of the wafer 70. For example, the wafer frame 80 is formed in the shape of a disk having a hole with a size slightly smaller than the wafer size at the center. The wafer 70 fixed to the wafer frame 80 has a plurality of semiconductor chips 75. At this time, the plurality of semiconductor chips 75 are individually sliced. Therefore, the flip head 160, which serves as a chip suction head, can individually pick up the semiconductor chips 75 provided on the wafer 80.

The wafer stage 130 fixes the wafer frame 80 fixing the wafer 70 and moves and rotates the wafer frame 80 in the X, Y, and R directions in accordance with the progress of the process. Therefore, the wafer stage 130 is provided with a drive unit 134 for moving and rotating the wafer frame 130 in the X, Y, and R directions. In one embodiment, the driving unit 134 may include an X-axis moving motor 131, a Y-axis moving motor 132, and a wafer stage rotating motor 133. In this case, the X-axis rotary motor 131 serves to move the wafer stage 130 which fixes the wafer frame 80 in the X direction so as to move the wafer frame 80 in the X direction, The wafer stage rotating motor 133 serves to move the wafer stage 130 for fixing the wafer frame 80 in the Y direction so as to move the wafer frame 80 in the Y direction, 80 to rotate the wafer stage 130 that fixes the wafer frame 80 to the wafer stage 80.

Between the wafer loader 110 and the wafer stage 130 is mounted a gripper 125 for transferring the wafer frame 80 mounted on the magazine 90 of the wafer loader 110 to the wafer stage 130 side, A guide 120 for guiding the wafer frame 80 to be transferred by the wafer transfer unit 125 may be installed. The wafer frame 80 loaded on the magazine 90 of the wafer loader 110 is smoothly transferred to the wafer stage 130 side through the gripper 125 and the guide 120. In this case,

The vision camera 140 is fixed on the upper side of the wafer stage 130 and recognizes the patterns previously taught. In one embodiment, the vision camera 140 is fixed to the upper portion of the center of the wafer stage 130 and is installed to be movable up and down. On the other hand, a backup pin 150 indicating a chip pickup position is installed at the center of the wafer stage 130 facing the vision camera 140. At this time, the backup pin 150 is installed so as to be movable up and down a predetermined distance, and serves to raise the semiconductor chip 75 located above the semiconductor chip 75 by a predetermined distance so that the semiconductor chip 75 located thereon is picked up.

The flip head 160 picks up the semiconductor chip 75 located on the wafer stage 130 and supplies the semiconductor chip 75 to the bonding head 180, which is a semiconductor chip bonding part. The flip head 160 picks up the semiconductor chip 75 located on the upper side of the backup pin 150 of the semiconductor chip 75 located on the wafer stage 130 and rotates the semiconductor chip 75 about 180 °, And serves to supply the semiconductor chip 75 to the bonding head 180, which is a semiconductor chip bonding portion. In this case, the backup pin 150 raises the semiconductor chip 75 located above the semiconductor chip 75 by a predetermined distance so that the flip head 160 picks up the semiconductor chip 75 as described above.

The bonding head 180 serves to bond the semiconductor chip 75 supplied from the flip head 160 to a circuit pattern 50 such as a carrier substrate (not shown) or a circuit tape 60. At this time, the bonding head 180 is installed so as to be movable up and down. Reference numeral 170 refers to a supply rail 170 that guides the supply of the circuit tape 60.

Hereinafter, with reference to FIG. 1 to FIG. 4, the semiconductor chip supply method of the flip chip bonder 100 will be described in detail as follows.

4 is a flowchart showing an embodiment of a method of supplying a semiconductor chip according to the present invention.

First, when a magazine 90 having a plurality of wafer frames 80 is provided, the user places the magazine 90 on the wafer loader 110 of the flip chip bonder 100 (S200) The aligning points of the wafer frame 80 and the alignment positions of the respective semiconductor chips 75 on the wafer 70 fixed to the wafer frame 80 in a central control device (not shown) The aligning patterns of the respective semiconductor chips 75 on the wafer 70 and the aligning order of the respective semiconductor chips 75 on the wafer 70 (S300).

Thereafter, the wafer frame 80 of the wafer loader 110 is loaded onto the wafer stage 130 using the gripper 125 (S400).

Subsequently, when the wafer frame 80 is loaded, the vision camera 140 calculates the alignment value of the wafer frame 80 through the alignment points of the pre-taught wafer frame 80, The wafer stage 130 is rotated in accordance with the value (S500).

Thereafter, the wafer frame 80 fixed to the wafer stage 130 and the wafer 70 fixed to the wafer frame 80 are rotated according to the above-described rotation of the wafer stage 130, The alignment positions of the respective semiconductor chips 75 are compensated by reflecting the rotation value of the wafer stage 130 to the aligned positions of the respective semiconductor chips 75 that have been taught (S600).

Subsequently, the aligned positions of the respective semiconductor chips 75 are compensated for as long as the wafer stage 130 is rotated in the pre-taught position, so that the vision camera 140 can compensate the aligned positions The semiconductor chips 75 are aligned with each other (S700).

Thereafter, the flip head 160, which is a head for picking up the chips, picks up the aligned semiconductor chips 75 to supply the semiconductor chips 75 to the bonding head 180, which is a semiconductor chip bonding part (S800).

Therefore, according to the semiconductor chip supply method of the present invention, when the semiconductor chips 75 provided on the wafer 70 are largely deviated from the previously taught position, The alignment positions of the semiconductor chips 75 are compensated for by the rotation of the wafer stage 130 at the pre-taught positions as described above, and then the semiconductor chips 75 are aligned Therefore, it is possible to prevent a vision error caused by a vision camera or the like not being able to align the semiconductor chips mounted on the wafer as in the prior art, and the semiconductor chip can be quickly and smoothly supplied do.

Hereinafter, with reference to FIG. 5, a wafer frame aligning method of the present invention bonder will be described in detail.

5 is a flowchart showing the wafer frame aligning method of FIG.

First, when the wafer frame 80 is loaded into the wafer stage 130, the wafer stage 130 is moved to a pre-taught position (not shown) so that the vision camera 140 can locate the first alignment point 72 of the wafer frame 80 The wafer frame 80 is moved (S510). Accordingly, the vision camera 140 detects a first alignment point 72 of the wafer frame 80 by sensing a pattern previously taught in the wafer frame 80 to be moved (S520).

Thereafter, the wafer stage 130 moves the wafer frame 80 to a pre-taught position so that the vision camera 140 can locate the second alignment point 74 of the wafer frame 80 (S530). Accordingly, the vision camera 140 detects the secondly aligned point 74 of the wafer frame 80 by detecting the previously-taught pattern in the moved wafer frame 80 (S540).

Subsequently, the wafer stage 130 moves the wafer frame 80 to the pre-taught position so that the vision camera 140 finds the third alignment point 76 of the wafer frame 80 (S550). Accordingly, the vision camera 140 detects the thirdly aligned point 76 of the wafer frame 80 by detecting the pattern previously taught in the moved wafer frame 80 (S560).

Next, when the first alignment point 72, the second alignment point 74 and the third alignment point 76 of the wafer frame 80 are all found, the central control device of the flip chip bonder 100 The alignment value of the wafer frame 80 is used to calculate a value to be aligned on the wafer frame 80, that is, a rotation value of the wafer stage 130 (S570). More specifically, the X-axis rotation value of the wafer stage 130 is calculated using the first alignment point 72 and the second alignment point 74 of the wafer frame 80, The Y-axis rotation value is calculated using the second alignment point 74 and the third alignment point 76 of the wafer frame 80. Then, the rotation value of the wafer stage 80 is calculated using the calculated X-axis rotation value and the Y-axis rotation value (S570). In one embodiment, the rotation value of the wafer stage 130 can be calculated by the following equation.

Wafer stage rotation value = (X axis rotation value + Y axis rotation value) / 2

Thereafter, when the rotation value of the wafer stage 130 is calculated, the central control device rotates the wafer stage 130 by the calculated rotation value using the wafer stage rotation motor 133 or the like, (S580).

Hereinafter, a semiconductor chip aligning method of a bonder according to the present invention will be described in detail with reference to FIG.

6 is a flowchart showing the semiconductor chip alignment method of FIG.

First, when the alignment positions of the respective semiconductor chips 75 previously taught by the compensation step are compensated, the wafer stage 130 sequentially aligns the semiconductor chips 75 (75) in accordance with the aligning order of the pre- ) To align the semiconductor chips 75 sequentially.

That is, when the alignment positions of the respective semiconductor chips 75 previously taught by the compensation step described above are compensated, the wafer stage 130 is moved to the first alignment position of the semiconductor chip 75 to be picked up, The wafer frame 80 is moved (S710) by reflecting the X / Y transition value due to the rotation of the wafer stage 130 to the alignment position of the semiconductor chip 75 previously trained to find the pattern 751, The vision camera 140 finds the first alignment pattern 751 of the semiconductor chip 75 within the viewing angle of the preset vision camera 140 at step S720. At this time, the positions (Tx1, Ty1) of the first alignment pattern 751 of the semiconductor chip 75 to be picked up can be calculated by the following equation in one embodiment.

Tx1 = Da-X1 +? X +? X

Ty1 = Da-Y1 +? Y +? Y

(Where Da-X1 and Da-Y1 are the first alignment pattern position values of the semiconductor chip 75 determined in the teaching step, and X and Y are the wafer X / Y X and? Y are rotation variation amounts of the semiconductor chip alignment positions after the wafer frame 80 is rotated, respectively,

Then, DELTA X and DELTA Y and DELTA X and DELTA Y can be calculated by the following equations, respectively.

ΔX = first alignment position of the taught wafer frame X - first alignment position of the found wafer frame X

DELTA Y = first alignment position of the taught wafer frame Y - first alignment position Y of the found wafer frame Y

(Da-Y1-Rc-Y) + Rc-X (Da-X1-Rc-X)

(Da-Y1-Rc-Y) + Rc-Y (X)

(Where? Is the rotation value of the wafer frame, and Rc-X and Rc-Y are the center coordinates of the wafer stage rotation axis)

Next, after the first alignment pattern 751 is found, the first alignment pattern 751 of the semiconductor chip 75 is found within the viewing angle of the preset vision camera 140 (S730). Accordingly, if it is determined that the first alignment pattern 751 is found by the first determination value, the above-described processes are continued. However, if it is determined that the first alignment pattern 751 is not found, The first alignment pattern 751 of the semiconductor chip 75 is again searched in step S732 after the viewing angle of the vision camera 140 is further expanded to a predetermined size in step S731. A second determination is made whether the first alignment pattern 751 is found within the extended viewing angle (S733). If it is determined that the first alignment pattern 751 is found based on the second determination value, the above-described processes are continued. In this case, however, if it is determined that the first alignment pattern 751 is not found, (S734), the first alignment pattern 751 is searched in a manual manner to find the first alignment pattern 751 directly (S735), and the above-described processes are continued.

On the other hand, if it is determined that the first alignment pattern 751 is found by the first determination value, the wafer stage 130 determines that the second alignment pattern 753 of the semiconductor chip 75 to be picked up by the vision camera 140 The wafer frame 80 is moved (S740) by reflecting the X / Y transition value due to the rotation of the wafer stage 130 to the alignment position of the semiconductor chip 75 that is pre-touched to be detected, The second alignment pattern 753 of the semiconductor chip 75 is found within the viewing angle of the preset vision camera 140 (S750). At this time, the positions (Tx2, Ty2) of the second alignment pattern 753 of the semiconductor chip 75 to be picked up can be calculated by the following equation in one embodiment.

Tx2 = Da-X2 +? X +? X

Ty2 = Da-Y2 +? Y +? Y

(Where Da-X2 and Da-Y2 are the second alignment pattern position values of the semiconductor chip 75 determined in the teaching step, and DELTA X and DELTA Y are the wafer alignment values of the wafer X / Y X and? Y are rotation variation amounts of the semiconductor chip alignment positions after the wafer frame 80 is rotated, respectively,

Then, DELTA X and DELTA Y and DELTA X and DELTA Y can be calculated by the following equations, respectively.

ΔX = second alignment position of the taught wafer frame X - second alignment position of the found wafer frame X

ΔY = second alignment position of the taught wafer frame Y - second alignment position Y of the found wafer frame Y

(Da-Y2-Rc-Y) + Rc-X (Da-X2-Rc-X)

(Da-Y2-Rc-Y) + Rc-X (Da-X2-Rc-X) + Cos

(Where? Is the rotation value of the wafer frame, and Rc-X and Rc-Y are the center coordinates of the wafer stage rotation axis)

Subsequently, after the step of finding the second alignment pattern 753, a first determination is made as to whether or not the second alignment pattern 753 of the semiconductor chip 75 is found within the viewing angle of the preset vision camera 140 (S760). Accordingly, if it is determined that the second alignment pattern 753 is found by the first determination value, the above-described processes are continued. If it is determined that the second alignment pattern 753 is not found, The second alignment pattern 753 of the semiconductor chip 75 is again searched in step S762 after the viewing angle of the vision camera 140 is further expanded to a predetermined size in step S761. A second determination is made whether the second alignment pattern 753 is found within the extended viewing angle (S763). If it is determined that the second alignment pattern 753 is found by the second determination value, the above-described processes are continued. In this case, however, if it is determined that the second alignment pattern 753 is not found, (S764), the user finds the second alignment pattern 753 in a manual manner in which the user directly finds the second alignment pattern 753 (S765), and continues the above-described processes.

When the first alignment pattern 751 and the second alignment pattern 753 are found by the above steps, the central control device of the flip chip bonder 100 picks up the two alignment patterns, The center point 757 of the semiconductor chip 75 is calculated (S770).

When the center point 757 of the semiconductor chip 75 to be picked up is calculated, the wafer stage 130 is moved to the center position 757 of the semiconductor chip 75 to be picked up, The alignment of the semiconductor chip 75 to be picked up is completed by moving the wafer frame 80 so as to come to the upper side (S780).

Therefore, when the center point 757 of the semiconductor chip 75 to be picked up comes to the chip pickup position, the flip head 160, which is the chip suction head, picks up the center point 757 of the semiconductor chip 75 to be picked up, The semiconductor chip 75 is supplied to the bonding head 180, which is the chip bonding portion.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various modifications and equivalents may be resorted to by those skilled in the art. Therefore, the scope of the present invention should be determined by the appended claims and their equivalents.

As described above, according to the semiconductor chip supply method of the present invention, the semiconductor chips provided on the wafer are largely deviated from the previously taught position, and the semiconductor chips are aligned based on the previously taught position, Since the alignment positions of the respective semiconductor chips are compensated for the rotation of the wafer stage at the pre-taught positions and then the semiconductor chips are aligned and picked up as described above, a vision camera or the like is mounted on the wafer It is possible to prevent the alignment error caused by not aligning the semiconductor chips. Therefore, according to the semiconductor chip supply method of the bonder of the present invention, it is possible to rapidly and smoothly supply the semiconductor chip.

Claims (5)

A semiconductor chip supply method of a bonder for supplying a semiconductor chip on a wafer fixed to a wafer frame to a semiconductor chip bonding section, A mounting step of placing a magazine on which the wafer frame is loaded on a wafer loader; Teaching the alignment points of the wafer frame and the aligned positions of the respective semiconductor chips on the wafer fixed to the wafer frame; Loading a wafer frame of the wafer loader into a wafer stage; A wafer frame aligning step of calculating an alignment value of the wafer frame through the aligned alignment points and rotating the wafer stage according to the calculated alignment value; A compensating step of reflecting the rotation value of the wafer stage to compensate for the aligned positions of the respective semiconductor chips being taught; A semiconductor chip aligning step of aligning the semiconductor chips with the compensated alignment positions; And And a pickup step of picking up the aligned semiconductor chips, The wafer-frame aligning step includes: Moving the wafer frame to the taught position so that a vision camera finds a first alignment point of the wafer frame; The vision camera finding a first alignment point of the wafer frame; Moving the wafer frame to the taught position so that the vision stage finds a second alignment point of the wafer frame; The vision camera finding a second alignment point of the wafer frame; Moving the wafer frame to the taught position so that the vision camera finds a third alignment point of the wafer frame; The vision camera searching for a third alignment point of the wafer frame; Calculating an X-axis rotation value of the wafer frame using a first alignment point and a second alignment point of the found wafer frame, and calculating a second alignment point of the wafer frame and a third alignment Calculating a rotation value of the wafer stage using the calculated X-axis rotation value and the calculated Y-axis rotation value; And And rotating the wafer stage by the calculated rotation value using a wafer stage rotation motor. delete 2. The method according to claim 1, Further comprising aligning the alignment patterns of the semiconductor chips on the wafer and the aligning order of the semiconductor chips on the wafer. The method of claim 1, wherein the step of aligning the semiconductor chips The wafer stage moves the wafer frame to reflect the X / Y shift due to the rotation of the wafer stage to the aligned position of the taught semiconductor chip so as to find the first alignment pattern of the semiconductor chip to be picked up by the vision camera ; The vision camera searching for the first alignment pattern within a viewing angle of the vision camera; Wherein the wafer stage reflects an X / Y transition value due to rotation of the wafer stage to an aligned position of the taught semiconductor chip so that the vision camera finds a second alignment pattern of the semiconductor chip to be picked up, ; ≪ / RTI > The vision camera searching for the second alignment pattern within a viewing angle of the vision camera; Calculating a center point of the semiconductor chip with the two alignment patterns found; And And moving the wafer frame by the wafer stage so that the center point of the semiconductor chip is at a chip pick-up position. 5. The method of claim 4, wherein the semiconductor chip aligning step If the alignment patterns are not found within the viewing angle of the vision camera, further expanding the viewing angle to a predetermined size and then searching for the alignment patterns again.
KR1020060032641A 2006-04-11 2006-04-11 Semiconductor chip supplying Method of bonder KR101146319B1 (en)

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CN103077904B (en) * 2013-01-14 2015-09-09 武汉新芯集成电路制造有限公司 A kind of method that bonding machine platform device is aimed at bonding

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980076498A (en) * 1997-04-10 1998-11-16 윤종용 Semiconductor Wafer Alignment Method Using Vision Recognition
KR0155774B1 (en) * 1994-10-29 1998-12-01 이대원 Method and device for die bonding
KR0167457B1 (en) * 1995-12-30 1999-02-01 김광호 Wire bonding apparatus
KR100199293B1 (en) * 1996-11-08 1999-06-15 윤종용 Semiconductor package manufacturing apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0155774B1 (en) * 1994-10-29 1998-12-01 이대원 Method and device for die bonding
KR0167457B1 (en) * 1995-12-30 1999-02-01 김광호 Wire bonding apparatus
KR100199293B1 (en) * 1996-11-08 1999-06-15 윤종용 Semiconductor package manufacturing apparatus
KR19980076498A (en) * 1997-04-10 1998-11-16 윤종용 Semiconductor Wafer Alignment Method Using Vision Recognition

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