KR101146319B1 - Semiconductor chip supplying Method of bonder - Google Patents
Semiconductor chip supplying Method of bonder Download PDFInfo
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- KR101146319B1 KR101146319B1 KR1020060032641A KR20060032641A KR101146319B1 KR 101146319 B1 KR101146319 B1 KR 101146319B1 KR 1020060032641 A KR1020060032641 A KR 1020060032641A KR 20060032641 A KR20060032641 A KR 20060032641A KR 101146319 B1 KR101146319 B1 KR 101146319B1
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- wafer
- alignment
- semiconductor chip
- frame
- wafer frame
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Abstract
The present invention provides a semiconductor chip supply method of a bonder for supplying a semiconductor chip on a wafer fixed to a wafer frame to a semiconductor chip bonding section. The provided semiconductor chip supply method of the bonder includes a mounting step of placing the magazine on which the wafer frame is loaded in the wafer loader and a step of aligning the alignment points of the respective semiconductor chips on the wafer fixed to the wafer frame A loading step of loading the wafer frame of the wafer loader into the wafer stage, a step of calculating the alignment value of the wafer frame through the pre-taught alignment points and rotating the wafer stage in accordance with the calculated alignment value, A compensating step of compensating the alignment positions of each of the semiconductor chips previously taught by reflecting the rotation value of the wafer stage, a semiconductor chip aligning step of aligning the semiconductor chips with the compensated alignment positions, And a pickup step of picking up the aligned semiconductor chips.
Description
1 is a schematic view showing a flip chip bonder according to the present invention.
Fig. 2 is a plan view of the wafer frame shown in Fig. 1 and the wafer fixed thereon.
3 is an enlarged view of the semiconductor chip shown in Fig.
4 is a flowchart showing an embodiment of a method of supplying a semiconductor chip according to the present invention.
5 is a flowchart showing the wafer frame aligning method of FIG.
6 is a flowchart showing the semiconductor chip alignment method of FIG.
DESCRIPTION OF REFERENCE NUMERALS
100: Flip chip bonder
110: Wafer loader
130: Wafer stage
140: vision camera
160: Flip head
180: bonding head
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonder for bonding a semiconductor chip, and more particularly, to a method of supplying a semiconductor chip to a bonder for supplying the semiconductor chip so that the semiconductor chip is bonded.
Generally, a bonder for bonding a semiconductor chip includes a die bonder, a wire bonder, and a flip chip bonder. Normally, the die bonder and the wire bonder are used continuously, and the flip chip bonder is used separately.
Specifically, the die bonder refers to a device for bonding a semiconductor chip (also referred to as a " die ") manufactured by a semiconductor chip manufacturing process to a printed circuit board or the like, and the wire bonder includes an electrode of a semiconductor chip bonded by a die bonder, Refers to a device for bonding leads formed on a substrate to each other with wires such as gold wires. The flip chip bonder may be formed by forming a solder bump on a pad which is an input / output terminal of a semiconductor chip and then turning the semiconductor chip upside down to form a circuit pattern such as a carrier substrate or a circuit tape (Pattern).
In order to smoothly perform the bonding operation of the semiconductor chips by the bonders, the semiconductor chips must be accurately supplied. Particularly, in the case of a flip chip bonder in which these semiconductor chips are directly bonded to a circuit pattern such as a carrier substrate or a circuit tape together with the supply of semiconductor chips, more accurate supply work must be performed.
Therefore, the conventional flip chip bonder does not directly pick up and supply the semiconductor chips positioned in the pre-taught position, but rather, deflects the semiconductor chips positioned in the pre-taught position before proceeding with the pick-up operation, And before aligning each of the semiconductor chips provided on the wafer, the wafer frame fixing the wafer is entirely aligned to correct the position of the wafer frame by this alignment value.
However, since the conventional flip chip bonder aligns the wafer including the respective semiconductor chips together with the wafer frame before aligning the respective semiconductor chips, and corrects the position of the wafer and the wafer frame according to the alignment value When correcting the position of the wafer and the wafer frame and then aligning the semiconductor chips mounted on the wafer with a vision camera or the like in accordance with a value previously taught, the semiconductor chips provided on the wafer are largely deviated from the pre- A vision camera or the like can not align the semiconductor chips provided on the wafer, that is, a vision alignment error occurs.
Particularly, in recent years, the sizes of semiconductor chips have been gradually decreasing, and vision cameras for aligning the semiconductor chips have been increasing in size with the trend of the size of semiconductor chips, and also in the field of view (FOV) area is reduced, and thus the vision-aligned error described above occurs more frequently.
Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of supplying a semiconductor chip of a bonder that minimizes occurrence of a vision error.
According to another aspect of the present invention, there is provided a semiconductor chip supply method for supplying a semiconductor chip on a wafer fixed to a wafer frame to a semiconductor chip bonding section.
The semiconductor chip supply method of the bonder includes a mounting step of placing the magazine on which the wafer frame is loaded on the wafer loader, a step of teaching the alignment points of the respective semiconductor chips on the wafer fixed to the wafer frame and the alignment points of the wafer frame A loading step of loading the wafer frame of the wafer loader into the wafer stage, a step of calculating the alignment value of the wafer frame through the pre-taught alignment points and rotating the wafer stage in accordance with the calculated alignment value, A compensating step of compensating the alignment positions of each of the semiconductor chips previously taught by reflecting the rotation value of the wafer stage, a semiconductor chip aligning step of aligning the semiconductor chips with the compensated alignment positions, And a pickup step of picking up the aligned semiconductor chips.
In another embodiment, the wafer-frame aligning step includes moving the wafer frame to a position where the wafer stage is pre-taught so that the vision camera will locate a first alignment point of the wafer frame, A step of moving the wafer frame to a position where the wafer stage is pre-taught to find a second alignment point of the wafer frame, and a step of moving the wafer frame to a second alignment Moving the wafer frame to a position where the wafer stage is pre-taught to locate the third alignment point of the wafer frame; and finding the third alignment point of the wafer frame by the vision camera The first alignment point of the found wafer frame, and the second alignment The X-axis rotation value of the wafer frame is calculated by using the second and third alignment points of the detected wafer frame, and the Y-axis rotation value of the wafer frame is calculated. Calculating the rotation value of the wafer stage using the calculated Y-axis rotation value, and rotating the wafer stage by the rotation value calculated using the wafer stage rotation motor.
In yet another embodiment, the teaching step may further comprise teaching alignment patterns of the respective semiconductor chips on the wafer and an alignment order of each of the semiconductor chips on the wafer.
In another embodiment, the semiconductor chip aligning step may include aligning the alignment position of the wafer stage to the alignment position of the semiconductor chip to which the wafer stage is pre-aligned so as to locate the first alignment pattern of the semiconductor chip to be picked up, Shifting the wafer frame to reflect the / Y transition value; and finding a first alignment pattern within the viewing angle of the vision camera, and determining a second alignment pattern of the semiconductor chip to which the vision camera is to be picked Moving the wafer frame to reflect an X / Y variation value due to rotation of the wafer stage to an alignment position of a semiconductor chip to which the wafer stage has been previously taught, and moving the wafer frame to a second alignment pattern Calculating a center point of the semiconductor chip using the two alignment patterns found; The emitter point so the chip pick-up position of the wafer stage may include the step of moving the wafer frame.
In another embodiment, the aligning of the semiconductor chips may further include a step of further extending the viewing angle to a predetermined size if the alignment patterns are not found within the viewing angle of the vision camera, and then searching for the alignment patterns again.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Like reference numerals designate like elements throughout the specification.
FIG. 1 is a schematic view showing a flip chip bonder according to the present invention, FIG. 2 is a plan view of the wafer frame shown in FIG. 1 and a wafer fixed thereon, and FIG. 3 is an enlarged view of the semiconductor chip shown in FIG.
1 to 3, a
Specifically, a
The
Between the wafer loader 110 and the
The
The
The bonding
Hereinafter, with reference to FIG. 1 to FIG. 4, the semiconductor chip supply method of the
4 is a flowchart showing an embodiment of a method of supplying a semiconductor chip according to the present invention.
First, when a
Thereafter, the
Subsequently, when the
Thereafter, the
Subsequently, the aligned positions of the
Thereafter, the
Therefore, according to the semiconductor chip supply method of the present invention, when the semiconductor chips 75 provided on the
Hereinafter, with reference to FIG. 5, a wafer frame aligning method of the present invention bonder will be described in detail.
5 is a flowchart showing the wafer frame aligning method of FIG.
First, when the
Thereafter, the
Subsequently, the
Next, when the
Wafer stage rotation value = (X axis rotation value + Y axis rotation value) / 2
Thereafter, when the rotation value of the
Hereinafter, a semiconductor chip aligning method of a bonder according to the present invention will be described in detail with reference to FIG.
6 is a flowchart showing the semiconductor chip alignment method of FIG.
First, when the alignment positions of the
That is, when the alignment positions of the
Tx1 = Da-X1 +? X +? X
Ty1 = Da-Y1 +? Y +? Y
(Where Da-X1 and Da-Y1 are the first alignment pattern position values of the
Then, DELTA X and DELTA Y and DELTA X and DELTA Y can be calculated by the following equations, respectively.
ΔX = first alignment position of the taught wafer frame X - first alignment position of the found wafer frame X
DELTA Y = first alignment position of the taught wafer frame Y - first alignment position Y of the found wafer frame Y
(Da-Y1-Rc-Y) + Rc-X (Da-X1-Rc-X)
(Da-Y1-Rc-Y) + Rc-Y (X)
(Where? Is the rotation value of the wafer frame, and Rc-X and Rc-Y are the center coordinates of the wafer stage rotation axis)
Next, after the
On the other hand, if it is determined that the
Tx2 = Da-X2 +? X +? X
Ty2 = Da-Y2 +? Y +? Y
(Where Da-X2 and Da-Y2 are the second alignment pattern position values of the
Then, DELTA X and DELTA Y and DELTA X and DELTA Y can be calculated by the following equations, respectively.
ΔX = second alignment position of the taught wafer frame X - second alignment position of the found wafer frame X
ΔY = second alignment position of the taught wafer frame Y - second alignment position Y of the found wafer frame Y
(Da-Y2-Rc-Y) + Rc-X (Da-X2-Rc-X)
(Da-Y2-Rc-Y) + Rc-X (Da-X2-Rc-X) + Cos
(Where? Is the rotation value of the wafer frame, and Rc-X and Rc-Y are the center coordinates of the wafer stage rotation axis)
Subsequently, after the step of finding the
When the
When the
Therefore, when the
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various modifications and equivalents may be resorted to by those skilled in the art. Therefore, the scope of the present invention should be determined by the appended claims and their equivalents.
As described above, according to the semiconductor chip supply method of the present invention, the semiconductor chips provided on the wafer are largely deviated from the previously taught position, and the semiconductor chips are aligned based on the previously taught position, Since the alignment positions of the respective semiconductor chips are compensated for the rotation of the wafer stage at the pre-taught positions and then the semiconductor chips are aligned and picked up as described above, a vision camera or the like is mounted on the wafer It is possible to prevent the alignment error caused by not aligning the semiconductor chips. Therefore, according to the semiconductor chip supply method of the bonder of the present invention, it is possible to rapidly and smoothly supply the semiconductor chip.
Claims (5)
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KR1020060032641A KR101146319B1 (en) | 2006-04-11 | 2006-04-11 | Semiconductor chip supplying Method of bonder |
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KR1020060032641A KR101146319B1 (en) | 2006-04-11 | 2006-04-11 | Semiconductor chip supplying Method of bonder |
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KR101146319B1 true KR101146319B1 (en) | 2012-05-21 |
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CN103077904B (en) * | 2013-01-14 | 2015-09-09 | 武汉新芯集成电路制造有限公司 | A kind of method that bonding machine platform device is aimed at bonding |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980076498A (en) * | 1997-04-10 | 1998-11-16 | 윤종용 | Semiconductor Wafer Alignment Method Using Vision Recognition |
KR0155774B1 (en) * | 1994-10-29 | 1998-12-01 | 이대원 | Method and device for die bonding |
KR0167457B1 (en) * | 1995-12-30 | 1999-02-01 | 김광호 | Wire bonding apparatus |
KR100199293B1 (en) * | 1996-11-08 | 1999-06-15 | 윤종용 | Semiconductor package manufacturing apparatus |
-
2006
- 2006-04-11 KR KR1020060032641A patent/KR101146319B1/en active IP Right Grant
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0155774B1 (en) * | 1994-10-29 | 1998-12-01 | 이대원 | Method and device for die bonding |
KR0167457B1 (en) * | 1995-12-30 | 1999-02-01 | 김광호 | Wire bonding apparatus |
KR100199293B1 (en) * | 1996-11-08 | 1999-06-15 | 윤종용 | Semiconductor package manufacturing apparatus |
KR19980076498A (en) * | 1997-04-10 | 1998-11-16 | 윤종용 | Semiconductor Wafer Alignment Method Using Vision Recognition |
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