KR101128261B1 - Fully wafer level processed light emitting diode package and methods for manufacturing a light emitting diode package - Google Patents

Abstract

PURPOSE: An LED package made with a wafer level and a manufacturing method thereof are provided to improve the performance and reliability of the LED package by suppressing local stress concentration. CONSTITUTION: A carrier substrate(100) includes a first via hole(101) and a second via hole(102). An epitaxial layer(200) is formed on the upper side of the carrier substrate. A first type electrode layer(210) is formed between the carrier substrate and the epitaxial layer. An epitaxial layer via(220) vertically passes through the epitaxial layer and the first type electrode layer. A second type electrode layer(230) is formed around the epitaxial layer via and on the upper side of the epitaxial layer.

Description

LED wafer fabricated at the wafer level in the previous process and a method of manufacturing the same {Fully wafer level processed light emitting diode package and methods for manufacturing a light emitting diode package}

The present invention relates to an LED package, and more particularly, to a wafer-level three-dimensional structure LED package and a method of manufacturing the same, which can increase the integration and production yield through a simplified process as the entire process proceeds to the wafer level. .

What is a physical group 3-5 nitride semiconductor? Due to its chemical properties, it has been spotlighted as a core material of light emitting devices such as a light emitting diode (LED) or a laser diode (LD).

In particular, LED has longer lifespan and lower power consumption than light sources such as incandescent and fluorescent lamps, and because it converts electric energy directly into light energy, it has high luminous efficiency, safety, eco-friendliness, and various colors. It is applied to various fields such as display, vehicle headlight, street light, traffic light, optical communication light source, and decorative lighting. In addition, with the development of the electronics industry, demands for high output, high brightness, low cost, and slimness of LED application products are increasing.

On the other hand, despite the many advantages of the LED lighting in the lighting field, the price is expensive, the situation is not expanded. In addition, the development of the LED package technology is progressing to improve performance, the price is lower than the performance, but the conventional technology has a limit of low price because the unit production cost is still high. Accordingly, there is a demand for an innovative manufacturing method that can replace conventional incandescent lamps or fluorescent lamps with LED lighting due to the low price.

Current general LED packages are SMD (Surface Mount Device) type, and are manufactured by applying independent three-stage technology so that the LED chip is mounted inside and can be attached to the board.

That is, the LED package includes an epitaxial process of growing an epitaxial layer that converts electricity into light on a growth substrate, a chip process of processing an epitaxial layer formed on an upper surface of the growth substrate in a chip form, and a growth substrate on which a chip is formed. The chips are cut and bonded to a carrier substrate one by one through packaging processes such as bonding and wire bonding and molding. The packaging process of the LED package production process is an important factor in determining the price of the LED package because it takes 50 to 60% of the LED package production cost.

Recently, wafer-level packaging has been proposed, which is packaged in a wafer state instead of a chip-level packaging process in which individual chips are cut into individual chips on a carrier substrate to package individual chips.

These wafer-level packaging techniques show excellent results, but most wafer-level packaging techniques do not package the entire process at the wafer level, but only some of the processes are performed at the wafer level, while the remaining processes package individual chips. By applying the technology of R & D, it can act as a factor of price increase.

In other words, conventional wafer-level packaging technology works on a submount substrate at the wafer level and then cuts the submounts to which individual chips are bonded to bond the finished chip onto the carrier substrate, and the chip and external leads. ) Is electrically connected through wire bonding or flip chip bonding, and it is a very complicated packaging method that seals it back with encapsulant. Therefore, the final finished product is required because it must include the wafer level process and the existing packaging process of the submount. There is a problem that the production cost of the rise.

A chip scale package of a light emitting device is disclosed in Korean Patent Laid-Open Publication No. 10-2007-0041729 as an example of an LED package in which the entire process is performed at the wafer level. This is a vertical LED package in which chips are stacked vertically and the stacked chips are electrically connected and packaged through vias formed in a carrier substrate. The via holes are formed perpendicularly to the carrier substrate, and then Cu is formed inside the via holes. By forming a conductive material such as Au, and the like, an electrical signal can be transferred to the inside of the chip, thereby increasing the degree of integration and reducing power consumption as compared with the conventional planar chip array packaging.

However, as shown in FIG. 1, the vertical LED package has a thin thickness because the via hole 11 is formed in the carrier substrate 10 positioned below the epitaxial layer 20 having a thickness of several microns. Since the epi layer 20 floats on the space, it may be easily damaged by physical impact or pressure in the subsequent process, and the packaging may inevitably have a reliability problem.

In addition, as shown in FIG. 2, when the via hole 11 is filled with a resin or a conductive material in order to prevent damage to the thin epitaxial layer 20, the filling material, the epitaxial layer 20, and the carrier substrate ( Due to the difference in thermal expansion coefficient of 10), stress is concentrated locally on the epi layer and its interface, and when the internal temperature of the package rises during use, the periphery of the via hole 11 filled with resin or conductive material is localized. As it expands, cracks may occur in the epitaxial layer 20 having a thickness of several microns, which causes a problem that the reliability of the package is lowered.

Furthermore, since the epitaxial layer 20 is blocking the upper portion of the via hole 11, the inside of the via hole 11 is connected or filled with a conductive material 27 before bonding the growth substrate onto the carrier substrate 10. The process must be preceded, and then the wafer bonding and the growth substrate are removed, and then the electrode on the epi layer 20 and the electrode on the lower side of the carrier substrate 10 are made of a conductive material through another via located outside the chip. Will be connected.

Due to such structural characteristics, both vias cannot be connected at the same time in one process, there are process limitations requiring two via connection processes, and as a result, there is a problem in that the production yield falls.

In order to solve this problem, both vias should be placed on the outside of the chip, but in this case, a space for forming a via hole is needed separately on the outside of the chip, which leads to a drastic reduction in chip density. Because of this, it is difficult and inadequate to apply the entire process at the wafer level.

Accordingly, the present inventors have developed a wafer level light emitting device package having a new three-dimensional structure that electrically connects the electrode of the chip and the electrode under the carrier substrate through the micro via hole, with an emphasis on solving the above-mentioned problems and problems. The invention was completed by devising the present invention during the intensive study for many years.

Accordingly, an object of the present invention is to provide an LED package and a method of manufacturing the same, which can improve the chip density, production yield, and lower the cost by manufacturing the entire process at the wafer level without expensive packaging processes as in the prior art. .

Another object of the present invention is to provide an LED package and a method of manufacturing the same, which can improve the reliability by preventing damage or crack generation of the epi layer.

In order to achieve the above object, an embodiment of the present invention provides a carrier substrate having vertically penetrating first and second via holes, an epi layer formed on an upper surface of the carrier substrate, and between the carrier substrate and the epi layer. A type 1 electrode layer formed in the second layer, an epi layer via formed vertically through the epi layer and the first type electrode layer positioned on the second via hole, and a type 2 electrode formed on an upper surface of the epi layer around and around the epi layer via Types 1 and 2 formed on an electrode layer, an insulating layer formed on the epi layer and an epi layer via, and insulating the epi layer and the type 1 electrode layer, and formed on the bottom surface of the carrier substrate in correspondence with the type 1 and type 2 electrode layers. An electrode pad, a first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad through the first via hole, and the type 2 electrode layer 2 through the epi layer via and the second via hole; It provides an LED package comprises a second coupling circuit for electrically connecting the electrode pad.

As a result, the present invention can increase the density and production yield through a more simplified process at the wafer level, and can improve reliability by preventing damage or cracking of the epi layer during the manufacturing process.

Another embodiment of the present invention is a carrier substrate having a vertically formed via hole, an epi layer formed on an upper surface of the carrier substrate, a type 1 electrode layer formed between the carrier substrate and the epi layer, and an upper portion of the via hole. An epi layer via formed vertically through the epi layer and the type 1 electrode layer to be positioned, a type 2 electrode layer formed on an upper surface of the epi layer around and around the epi layer via, and formed on the epi layer and the epi layer via, A first insulating layer which insulates the epi layer and the type 1 electrode layer and the type 2 electrode layer, the type 1 and type 2 electrode pads formed on the bottom surface of the carrier substrate corresponding to the type 1 and type 2 electrode layers, and the via hole. A first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad through the surface of the type 1 electrode layer, the type 1 connection circuit, and the type 1 electrode pad; And a second connection circuit for electrically connecting the second type electrode layer and the second type electrode pad electrode through the via hole and the epi layer via to prevent an electrical short circuit of the electrode layer. Provide LED package.

In an embodiment of the present invention, the epi layer is formed between the type 1 and type 2 group 3-5 semiconductor layers stacked on the type 1 electrode layer and the type 1 and type 2 group 3-5 semiconductor layers and is formed of electrons and holes. It can provide an LED package comprising an active layer for generating light by recombination of.

Another embodiment of the present invention, (a) a step of depositing and patterning a type 1 electrode layer on the epi layer surface of the growth substrate (b) the step of etching the epi layer to form at least one epi layer via and mesa pattern (c) bonding the growth substrate on which the epi layer via and the mesa pattern are formed on a carrier substrate on which a bonding layer is deposited on a top surface; (d) removing the growth substrate except for the epi layer and the type 1 electrode layer; (F) depositing and patterning an insulating layer on the inner surface of the epi layer via, the sidewalls of the epi layer, and the type 1 and type 2 electrode layers around and around the epi layer via. (g) forming first and second via holes vertically penetrating the portion of the bonding layer and the carrier substrate where the epi layer vias are located; (h) forming a lower surface of the first and second via holes and the carrier substrate. By plating with conductive material 1 Forming a first electrode pad and a second electrode pad, and forming first and second connection circuits electrically connecting the first electrode layer, the first electrode pad, the second electrode layer, and the second electrode pad. Provided is a method for manufacturing a package.

Another embodiment of the present invention, (a) a step of depositing a type 1 electrode layer on the epi layer surface of the growth substrate (b) a carrier having a bonding layer deposited on the upper surface of the growth substrate formed with the epi layer and the type 1 electrode layer Bonding on a substrate (c) removing the growth substrate except for the epi layer and the type 1 electrode layer (d) depositing and patterning a type 2 electrode layer on the upper surface of the epi layer (e) etching the epi layer Forming at least one epi layer via and a mesa pattern (f) patterning the bonding layer of the type 1 electrode layer and the carrier substrate (g) an inner wall of the epi layer via, sidewalls of the epi layer, forms 1 and 2 Depositing and patterning an insulating layer on the type electrode layer (h) forming first and second via holes vertically penetrating the carrier substrate on which a portion of the bonding layer and the epi layer vias are located (i) the first And the second via hole and the carrier substrate. First and second connection circuits for electrically connecting the first type electrode layer, the first type electrode pad, the second type electrode layer, and the second type electrode pad to form a type 1 electrode pad and a type 2 electrode pad by plating a surface with a conductive material. It provides a LED package manufacturing method comprising a forming step.

Another embodiment of the present invention, (a) a step of depositing a type 1 electrode layer on the epi layer surface of the growth substrate (b) a carrier having a bonding layer deposited on the upper surface of the growth substrate formed with the epi layer and the type 1 electrode layer Bonding on a substrate (c) removing the growth substrate except for the epi layer and the type 1 electrode layer (d) depositing and patterning a type 2 electrode layer on the upper surface of the epi layer (e) etching the epi layer Forming a mesa pattern (f) patterning a bonding layer of the type 1 electrode layer and the carrier substrate (g) vertically penetrating a portion of the bonding layer and a carrier substrate while forming an epi layer via in the epi layer Forming first and second via holes (h) depositing and patterning an insulating layer on inner walls of the epi layer vias, sidewalls of the epi layer, and type 1 and type 2 electrode layers (i) the first and second vias Conductive water on the bottom of the via hole and the carrier substrate Forming first and second connection circuits electrically connecting the first type electrode layer, the first type electrode pad, the second type electrode layer, and the second type electrode pad while forming the first type electrode pad and the second type electrode pad by plating with It provides an LED package manufacturing method comprising a.

Another embodiment of the present invention, (a) a step of depositing and patterning a type 1 electrode layer on the epi layer surface of the growth substrate (b) the step of etching the epi layer to form an epi layer via and mesa pattern (c) Bonding the growth substrate having the epi layer via and the mesa pattern on the carrier substrate on which the bonding layer is deposited (d) removing the growth substrate except for the epi layer and the type 1 electrode layer (e) the epi layer (F) depositing and patterning a second type electrode layer on top of the epi layer around and around the via (f) depositing and patterning a first insulating layer on the inner wall of the epi layer via, sidewall of the epi layer, and type 1 electrode layer (g) Forming a via hole vertically penetrating the carrier substrate on which the layer vias are located; (h) forming a type 1 electrode pad by plating a portion of a lower surface of the carrier substrate with a conductive material to form the type 1 electrode layer and the type 1 electrode pad; Electricity (I) depositing and patterning a second insulating layer on the first type electrode layer, the first connecting circuit, and the first type electrode pad; and (j) an epitaxial formation of the second insulating layer. Forming a second type electrode pad by plating a portion of the lower surface of the carrier substrate with a conductive material while forming a second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad through the layer via and the via hole; It provides a LED package manufacturing method made.

Another embodiment of the present invention, (a) a step of depositing a type 1 electrode layer on the epi layer surface of the growth substrate (b) a carrier having a bonding layer deposited on the upper surface of the growth substrate formed with the epi layer and the type 1 electrode layer Bonding on the substrate (c) removing the growth substrate except for the epi layer and the type 1 electrode layer (d) depositing and patterning a type 2 electrode layer on the top surface of the epi layer (e) etching the epi layer (F) patterning the bonding layer between the type 1 electrode layer and the carrier substrate (g) inner wall of the epi layer via, sidewall of the epi layer, type 1 electrode layer and type 2 electrode layer Depositing and patterning an insulating layer on the substrate (h) forming a via hole vertically penetrating the carrier substrate on which the epi layer vias are located (i) forming a type 1 electrode by plating a portion of the lower surface of the carrier substrate with a conductive material If you form a pad Forming a first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad (j) depositing and patterning a second insulating layer on the type 1 electrode layer, the first connection circuit, and the type 1 electrode pad; (k) forming a second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad through the epi layer via and the via hole on which the second insulating layer is formed, and plating a portion of the lower surface of the carrier substrate with a conductive material; It provides a LED package manufacturing method comprising the step of forming a type 2 electrode pad.

The present invention, which consists of the above-described solutions, configurations, and manufacturing methods, integrates the chip process and the carrier substrate process in a substrate (wafer) state, and the entire process proceeds in wafer level units, and the chip and carrier substrate are formed together in a batch process. As a result, the LED package can be implemented without the conventional package processes, thereby greatly reducing the production cost.

In addition, since the carrier substrate simultaneously performs the role of a submount without a separate submount, it is easy to reduce the size and thinness, and the production yield can be increased by simplifying the process and improving the degree of integration.

In addition, since the epi layer is not formed on the via hole formed in the carrier substrate, the via for forming the electrical connection circuit between the electrodes can be simply formed in one step.

In addition, since the thin epi layer has a structure in which the entire surface is bonded to the carrier substrate without floating portions due to the via hole space, it is possible to prevent damage or crack generation of the epi layer during the manufacturing process, and each layer has a coefficient of thermal expansion. Instead of being composed of many different materials, each layer is made of the same material with the same coefficient of thermal expansion, preventing local stress concentrations inside the package, improving the performance and reliability of the LED package.

1 and 2 is a cross-sectional configuration diagram showing a local example of the LED package according to the prior art,
3 is a local cross-sectional view of a type 1 electrode layer deposited on the epi layer surface of an epitaxial growth substrate with an LED package according to the first embodiment of the present invention;
FIG. 4 is a local cross-sectional view of a mesa pattern and a type 1 electrode layer pattern formed on an epitaxial layer formed on the growth substrate as an LED package according to the first embodiment of the present invention; FIG.
FIG. 5 is a cross-sectional view of a growth substrate of a LED package according to a first embodiment of the present invention in a state of wafer bonding on a carrier substrate on which a wafer bonding layer is formed;
FIG. 6 is a partial cross-sectional view and a plan view of an LED package according to a first embodiment of the present invention, in which only an growth layer is removed while leaving an epitaxial layer and a type 1 electrode layer on a carrier substrate;
FIG. 7 is a cross-sectional view and a plan view of a patterned state in which a type 2 electrode layer and an insulating layer are deposited by the LED package according to the first embodiment of the present invention; FIG.
8 is a local cross-sectional view and a plan view of a state in which two via holes per chip are formed in a carrier substrate with an LED package according to the first embodiment of the present invention;
FIG. 9 is a cross-sectional view and a plan view of a LED package according to a first embodiment of the present invention in which a type 1 and type 2 electrode pad and first and second connection circuits are formed on a carrier substrate;
FIG. 10 is a bottom view of a LED package according to a first embodiment of the present invention in which a type 1 and type 2 electrode pad and first and second connection circuits are formed on a carrier substrate;
11 is a local cross-sectional view showing an LED package according to a first embodiment of the present invention;
12 is a local cross-sectional view and a plan view of the LED package according to the second embodiment of the present invention in the same process as the first embodiment until the growth substrate is removed;
FIG. 13 is a cross-sectional view and a plan view of a state in which a type 2 electrode layer and a first insulating layer are deposited and patterned with an LED according to a second embodiment of the present invention; FIG.
FIG. 14 is a local cross-sectional view and a plan view of an LED package according to a second embodiment of the present invention in which one via hole is formed on a carrier substrate in a carrier substrate;
15 is a local cross-sectional view and a plan view of a LED package according to a second embodiment of the present invention in a state in which a type 1 electrode pad and a first connection circuit are formed on a carrier substrate;
16 is a local cross-sectional view and a plan view of a state in which a second insulating layer is deposited and patterned with an LED package according to a second embodiment of the present invention;
17 is a local bottom view of a state in which a second insulating layer is deposited and patterned with an LED package according to a second embodiment of the present invention;
FIG. 18 is a local cross-sectional view and a plan view of a state in which a type 2 electrode pad and a second connection circuit are formed on a carrier substrate with an LED package according to a second embodiment of the present invention; FIG.
19 is a local bottom view of a LED package according to a second embodiment of the present invention with a type 2 electrode pad and a second connection circuit formed on a carrier substrate;
20 is a local cross-sectional view showing an LED package according to a second embodiment of the present invention;

Hereinafter, embodiments according to the present invention will be described more specifically with reference to the accompanying drawings.

Prior to this, the following terms are defined in consideration of the functions in the present invention, which specifies that the concept should be construed as a concept consistent with the technical spirit of the present invention and commonly used or commonly recognized in the art.

In addition, when it is determined that the detailed description of known functions or configurations related to the present invention may obscure the gist of the present invention, the detailed description thereof will be omitted.

The accompanying drawings are shown by exaggerating or simplifying a part for convenience and clarity of description and understanding, and each component does not exactly match the actual size.

≪ Embodiment 1 >

FIG. 11 is a local cross-sectional view illustrating an LED package according to a first embodiment of the present invention. As shown in FIG. 11, a carrier substrate 100, a first via hole 101, a second via hole 102, and a bonding layer ( 110, epitaxial layer 200, type 1 electrode layer 210, epi layer via 220, type 2 electrode layer 230, insulating layer 240, type 1 electrode pad 250, type 2 electrode pad 260. ), A first connection circuit 270, and a second connection circuit 280.

The carrier substrate 100 serves as a submount at the same time, and the first and second via holes 101/102 penetrating vertically through the upper surface and the lower surface are formed.

In addition, the diameters of the first and second via holes 101 and 102 may be formed in a range of 10 to 100 μm, and may be spaced apart from each other according to the size of the final finished product, the size of the chip, and the pattern of the epi layer 200. Can be arranged spaced apart.

That is, the first via hole 101 is a passage for electrically connecting the type 1 electrode layer 210 and the type 1 electrode pad 250 through a conductive material that is the first connection circuit 270, and the second via hole 102. ) Is a passage for electrically connecting the type 2 electrode layer 230 and the type 2 electrode pad 260 through the conductive material that is the second connection circuit 280. In the process of forming the first connection circuit 270 and the second connection circuit 280, the first type electrode layer 210, the first via hole 101, the second type electrode layer 230, and the second via hole 102 are formed. A conductive material is deposited on the substrate, and at the same time, the first type electrode pad 250 and the second type electrode pad 260 are formed and electrically connected to each other.

The first and second via holes 101/102 may prevent leakage currents between the type 1 and type 2 group 3-5 semiconductor layers 201/202 and the active layer 203 of the epi layer 200 and the type 1. It may be formed before or after depositing the insulating layer 240 formed to insulate the electrode layer 210.

The first and second via holes 101 and 102 may be formed of fine vias of several tens of micrometers or less using laser drilling.

The carrier substrate 100 may be implemented in various forms and materials. For example, it may be in the form of a polygon, such as a square, hexagon, octagon, elliptical, circular or the like, alumina, BN, BeO, ceramics, etc. may be applied.

More preferably, the thermal conductivity is excellent compared to the price, the epilayer 200 and the thermal expansion coefficient difference of the growth substrate is small and can be used in a large area, and made of aluminum nitride (AIN) having high heat dissipation characteristics, high output and high efficiency performance The thickness can be applied to 0.2 mm or less.

The epitaxial layer 200 is grown on the upper surface of the growth substrate 400 by organometallic chemical vapor deposition (MOCVD), liquid phase epitaxial growth, molecular beam epitaxial growth (MBE), and the like to grow with the carrier substrate 100. It can be formed on the carrier substrate 100 through the bonding process of the substrate 400, the type 1 and type 2 group 3-5 semiconductor layer (201/202), these type 1 and type 2 group 3-5 semiconductor An active layer 203 formed between layers 201/202.

That is, the first type electrode layer 210 is formed on the carrier substrate 100, and the first type 3-5 group semiconductor layer 201, the active layer 203, and the second type 3-5 group are formed on the first type electrode layer 210. The epi layer 200 having a structure in which the semiconductor layers 202 are sequentially stacked is formed. Another semiconductor layer may be further disposed above or below the respective layers, but is not limited thereto.

Specifically, the type 1 group 3-5 semiconductor layer 201 is formed on the type 1 electrode layer 210 formed on the upper surface of the carrier substrate 100 and has a p type conductivity. The active layer 203 is formed on the Type 1 Group 3-5 semiconductor layer 201 and generates light by recombination of electrons and holes. The 2 type group 3-5 semiconductor layer 202 is formed on the active layer 203, and has n type conductivity.

The type 1 group 3-5 semiconductor layer 201 is a compound semiconductor of a group 3 group 5 element doped with a type 1 dopant, for example, may be formed of p-GaN, and the type 1 dopant may include Mg, Zn, or the like. The same p-type dopant can be used.

Further, the Type 1 Group 3-5 semiconductor layer 201 may be formed to have n-type conductivity, and the Type 2 Group 3-5 semiconductor layer 201 may have p-type conductivity.

The active layer 203 may be a semiconductor layer containing a light emitting material made of In (x) Ga (1-x) N (0 <x≤1) or the like, and in addition, InAlGaN, InGaAIP, GaP, GaAsP, AlGaAs, AlGaInP, etc. The material may be used, and may have a single quantum well layer or a multi quantum well layer structure composed of a plurality of quantum well layers.

The type 2 group 3-5 semiconductor layer 202 is a compound semiconductor of a group 3 group 5 element doped with a type 2 dopant, and may be formed of, for example, n-GaN, and the type 2 dopant may be Si, Ge, Sn. N-type dopants such as Te and the like can be used.

As described above, the epi layer 200 and the type 1 electrode layer 210 formed on the growth substrate have a predetermined region and a pattern through an etching process, and may be wafer bonded using only the type 1 electrode layer 210 formed on the growth substrate. A separate bonding layer may be formed on the first type electrode layer 210, and the first type electrode layer 210 may mean that the bonding layer 110 is included. A portion of the bonding layer 110 formed on the carrier substrate 100 and an upper edge of the carrier substrate 100 are exposed to the outside in plan view. The epitaxial layer 200 may be etched using plasma dry etching.

The first type electrode layer 210 is formed between the carrier substrate 100 and the epi layer 200 and has a p-type conductivity. Since the type 1 electrode layer 210 is formed on the entire lower surface of the type 1 group 3-5 semiconductor layer 201, the operating current can be increased, and at the same time, the light extraction performance can be improved by acting as a reflective layer.

Here, the type 1 electrode layer 210 exhibits ohmic contacts with the type 1 group 3-5 semiconductor layer 201 and has high light reflectivity and does not cause side effects or adverse effects in the wafer bonding process. , Cu,, Al, Rh, Ir, Ru, Pt, Pd, Cr, Mo, W, Sn, indium tin oxide (ITO) and the like may be formed in multiple layers by selecting one or more.

In addition, the first type electrode layer 210 is formed in a predetermined pattern before etching the epi layer 200 to form the epi layer via 220 and the mesa pattern, and then the epi layer via 220 and the mesa pattern are plasma dry etching. It can be formed at the same time by the method.

Meanwhile, when the via hole is formed in the carrier substrate 100, the epi layer via 220 may be formed together. In this case, only the mesa pattern may be formed without the epi layer via 220.

The epi layer via 220 is formed by vertically penetrating the epi layer 200 and the type 1 electrode layer 210 positioned above the edge of the second via hole 102, and is larger than the diameter of the second via hole 102. It can be formed with a large diameter or the same diameter.

The epi layer via 220 and the second via hole 102 serve as a passage for electrically connecting the type 2 electrode layer 230 and the type 2 electrode pad 260.

The type 2 electrode layer 230 is formed on the upper surface of the epi layer 200 around and around the epi layer via 220 to be in electrical contact with the type 2 type 3-5 semiconductor layer 202 and have n type conductivity.

Here, the type 2 electrode layer 230 may be an electrically conductive material having good ohmic contact properties and adhesion to dissimilar compounds and metals. For example, select one, two or more from Ni, Ag, Ti, Au, Cu,, Al, Rh, Ir, Ru, Pt, Pd, Cr, Mo, W, Sn, Indium Tin Oxide (ITO), Indium Oxide, etc. To form a multilayer.

In addition, the type 2 electrode layer 230 may be connected to the type 2 electrode pad 260 through the epi layer via 220 and may be located anywhere on the upper surface of the epi layer 200.

The type 2 electrode layer 230 is deposited on the surface of the type 2 type 3-5 semiconductor layer 202 by vacuum deposition or plating, and is electrically connected to each other type 2 type 3-5 group semiconductor layer 202. Ensure the supply of current is smooth.

The type 1 electrode layer 210 may be formed to have n-type conductivity, and the type 2 electrode layer 230 may have a p-type conductivity in correspondence with the type 1 and type 2 to group 3-5 semiconductor layers 201 and 202.

The insulating layer 240 is formed on the upper edge of the carrier substrate 100, a part of the type 1 electrode layer 210, the sidewall of the epi layer 200, and the inner wall of the epi layer via 220 to form the type 1 and type 2 3-5. A leakage current between the group semiconductor layers 201/202 and the active layer 203 is prevented, and electrical shorts between the type 1 electrode layer 210 and the type 2 electrode layer 230 are prevented.

The insulating layer 240 may be formed of a material such as silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), or the like, and may be formed by chemical vapor deposition.

The first and second connection circuits 270/280 form through electrodes together with the first and second via holes 101/102, which are electrical passages between the electrodes, and form the carrier substrate 100 and the epi layer 200. ) May be formed by filling the first and second via holes 101/102 penetrating vertically with a conductive material or by coating an inner wall thereof with the conductive material.

In the process of forming the first and second connection circuits 270/280, the type 1 and type 2 electrode pads 250/260 are formed together.

Here, the conductive material for the first and second connection circuits 270/280 is any one or a plurality of materials selected from Au, Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, etc. It may be formed in a multi-layer, but is not limited thereto.

The first and second connection circuits 270/280 may be formed through plating, and may be applied by using electroplating, electroless plating, screen printing, vacuum deposition, or the like.

The type 1 and type 2 electrode pads 250/260 are in contact with a main board of an external device composed of a controller or passive elements, and correspond to the type 1 and type 2 electrode layers 210/230. Is formed on the lower surface of the bottom surface) and is electrically connected to each electrode through the first and second connection circuits 270/280. The first type electrode pad 250 is p-type conductive and the second type electrode pad 260 is It has n-type conductivity.

The type 1 electrode pad 250 may be formed to have n type conductivity, and the type 2 electrode pad 260 may have p type conductivity.

Thereafter, the type 1 electrode pad 250 and the type 2 electrode pad 260 are surface treated for stable soldering with a circuit of an external device. Surface treatment may be applied to Hot Air Solder Leveling (HASL), Organic Solderability Preservative (OSP), electroless Ni / Au plating and Sn plating, but is not limited thereto.

Here, the surface treatment of the type 1 and type 2 electrode pads 250/260 may be plated with Ni, Au, and Ag. It can also be processed. In addition, the type 1 and type 2 electrode pads 250/260 may be surface treated after the silicone resin layer 310 is coated.

The phosphor layer 300 and the silicone resin layer 310 are for protecting the light emitting device and improving the light collecting efficiency. The phosphor layer 300 and the silicone resin layer 310 may include an epitaxial layer 200, a type 2 electrode layer 230, an insulating layer 240, and first and second connections. After coating the phosphor layer 300 on the circuit (270/280), it is formed by coating the silicone resin layer 310 sequentially thereon.

In the LED package P according to the first embodiment of the present invention, the entire process can be performed on a wafer level basis, and chips are formed in a batch process integrating a chip process and a carrier substrate process, and at the same time, Since it can be formed, productivity per unit can be increased significantly.

In addition, the integrated circuit is minimized by minimizing the space required for electrical connection between the chip and the carrier substrate 100, and the first and second types of chips are formed through two via holes 101/102 and the EBI layer via 202. The carrier substrate 100 serves as a submount due to the wafer-level three-dimensional structure in which the electrode layers 210/230 and the type 1 and type 2 electrode pads 250/260 below the carrier substrate are electrically connected to each other. Doing so simultaneously eliminates the need for a separate submount.

In addition, the entire thickness of the package (P) is less than 0.3 mm can be reduced in size and weight, and the production cost can be greatly reduced. In addition, since the epi layer 200 is not formed on the first and second via holes 101/102, the epi layer 200 may be prevented from being damaged or cracked during the manufacturing process, and the reliability may be improved.

In addition, since each layer of the package P is made of one material having the same thermal expansion coefficient, the stress due to the difference in thermal expansion coefficient of each layer is uniformly distributed on the front surface of each layer, thereby increasing the reliability of the product and improving heat dissipation performance. Can be.

A method of manufacturing the LED package according to the first embodiment of the present invention configured as described above will be described with reference to FIGS. 3 to 11.

Referring to FIG. 3, the type 1 electrode layer 210 is deposited and patterned on the epitaxial layer 200 surface of the growth substrate 400. In this case, the type 1 electrode layer 210 may simultaneously perform the role of ohmic contacts and the wafer bonding layer, or may include a layer for separate wafer bonding.

The epitaxial layer 200 may be formed on the top surface of the sapphire growth substrate 400 by organometallic chemical vapor deposition (MOCVD), liquid phase epitaxial growth, molecular beam epitaxial growth (MBE), type 1 And an active layer formed between the type 2 group 3-5 semiconductor layers 201/202 and the type 1 and type 2 group 3-5 semiconductor layers 201/202 to generate light by recombination of electrons and electrons. 203).

In addition, the epi layer 200 and the type 1 electrode layer 210 form a predetermined region and a pattern through an etching process, and the etching of the epi layer 200 may be performed using a plasma dry etching method.

In addition, the type 1 electrode layer 210 is deposited on the epi layer 200, is formed in a predetermined pattern to form the epi layer via 220 and the mesa pattern, and has a p type conductivity.

Here, the type 1 electrode layer 210 exhibits ohmic contacts with the type 1 group 3-5 semiconductor layer 201 and has a high light reflectivity and adverse effects and adverse effects in the bonding process between the growth substrate 400 and the carrier substrate 100. Cr, Ni, Ti, Au, Al, Cu, Mo, W, Ag, Sn, Pd and the like that do not cause any one or may be made of two or more multilayers.

As the growth substrate 400, a sapphire substrate (Al203), GaN, SiC, ZnO, AIN, Si, GaAs, etc., in which the compound semiconductor may be grown, may be applied.

4, the epi layer 200 is etched to form at least one epi layer via 220 and a mesa pattern. In this case, the epi layer via 220 and the mesa pattern may be formed by etching the epi layer 200 after removing the growth substrate 400 through wafer bonding and laser lift off (LLO) processes.

The epi layer via 220 and the mesa pattern may be simultaneously formed by plasma dry etching.

In addition, when the via is formed in the carrier substrate 100, the second via hole 102 may be formed together with the via formed in the epi layer 200. In this case, only the mesa pattern may be formed without the epi layer via 220. That is, the epi layer via 220 may be formed together through a method of forming a via hole in the carrier substrate 100.

In addition, the type 1 electrode layer 210 and the epi layer 200 on the upper surface of the epi layer 200 may proceed to the next process without a pattern.

The type 1 electrode layer 210 may simultaneously serve as ohmic contacts and a wafer bonding layer, or may include a layer for separate wafer bonding.

5, the epitaxial via 220 and the growth substrate 400 having the mesa pattern are bonded to each other on the carrier substrate 100 having the bonding layer 110 formed thereon.

The carrier substrate 100 is preferably made of aluminum nitride (AIN) having a high heat dissipation characteristics, high output and high efficiency, the thickness can be applied to 0.2 mm or less.

In addition, the bonding layer 110 may have a pattern corresponding to the epi layer via 220 and the mesa pattern as shown in FIG. 5A before bonding the growth substrate 400 and the carrier substrate 100 to each other. It may be formed after bonding the growth substrate 400 and the carrier substrate 100 as shown in (b). At this time, the upper edge of the carrier substrate 100 is exposed to the outside in plan view.

The bonding layer 110 may be deposited by vacuum deposition of Au and Sn in a multilayer or by mixing Au and Sn by plating or vacuum deposition. At this time, in order to increase the bonding force with the carrier substrate 100, vacuum deposition of Ti, Ni, and then vacuum deposition of Au, Sn, vacuum deposition of Ti, Cu, plating Ni, Au and plating Au, Sn It may be formed by. In addition, not only the AuSn layer but also a solderable metal layer, for example, SnPb, AuSi, AuGe, or the like may be applied, but is not limited thereto.

In addition, in the case of coating BCB (benzocyclobutene) having excellent flowability and crosslinking reaction density, spin coating is performed on the carrier substrate 100 to apply a total thickness of 4 to 5 μm or vacuum deposition of Ti and Cu on the carrier substrate 100. BCB can then be applied. In addition to BCB, polyimide (PI), SU8, and the like can also be applied, but are not limited thereto.

6, after the growth substrate 400 and the carrier substrate 100 are bonded, the growth substrate 400 is removed on the carrier substrate 100 except for the epi layer 200 and the type 1 electrode layer 210. Remove At this time, when the epitaxial layer 200 proceeds without patterning the mesa maton and the type 1 electrode layer 210, the pattern is removed after the growth substrate 400 is removed.

The growth substrate 400 may be removed using a laser lift off (LLO) method. It can also be removed by chemical lift off (CLO) by chemical method. If the growth substrate 400 is not removed, the surface of the type II 3-5 semiconductor layer 202 may not be exposed, and thus, the electrodes may not be electrically connected to each other.

Subsequently, referring to FIG. 7, the type 2 electrode layer 230 is deposited and patterned on the upper surface of the epi layer 200 around and around the epi layer via 220.

At this time, the type 2 group 3-5 semiconductor layer 202 may be removed by leaving only the necessary thickness through plasma dry etching, and then form the type 2 electrode layer 230 by vacuum deposition thereon.

The two-type electrode layer 230 is made of, for example, Ni, Ag, Ti, Au, Cu,, Al, Rh, Ir, Ru, Pt, Pd, Cr, Mo, W, Sn indium tin oxide (ITO), or the like. Two or more may be selected to form a multilayer.

On the other hand, after the LLO process several photolithography (photo lithography) process is performed, each layer due to the thickness of the epi layer 200, type 1 electrode layer 210, bonding layer 110 and type 2 electrode layer 230 When the difference in height is large, it is difficult to form a pattern by a photolithography process, and spin coating and patterning with photoresist (PR) before plating to prevent plating to unnecessary parts when forming a connection circuit between the electrodes. In this case, if the height difference between the layers is large, the photoresist may not be applied well to the interface of each layer.

Therefore, the maximum height difference between the epitaxial layer 200, the first type electrode layer 210, the bonding layer 110, and the second type electrode layer 230 may be reduced to facilitate the packaging process.

After depositing and patterning the type 2 electrode layer 230 on the upper surface of the epi layer 200, the inner wall of the epi layer via 220, the sidewalls of the epi layer 200, the type 1 and type 2 electrode layers 210/230, and the carriers. The insulating layer 240 is deposited and patterned on the exposed upper surface of the substrate 100.

The insulating layer 240 insulates current leaking from the type 1 and type 2 group 3-5 semiconductor layers 201/202 of the epi layer 200, and the type 1 and type 2 electrode layers 210/230 are electrically insulated from each other. To prevent them from being connected to each other.

The insulating layer 240 may be formed of a material such as silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), or the like, and may be formed by chemical vapor deposition.

8, first and second via holes 101/102 penetrating perpendicularly to a carrier substrate 100 in which a portion of the bonding layer 110 and the epi layer via 220 are located are formed. . In this case, when the epi layer via 220 is not formed in the previous process, the first and second via holes 101 and 102 may be formed together in the carrier substrate 100.

Here, the first and second via holes 101 and 102 may be formed as fine vias of several tens of micrometers or less using laser drilling as a passage for electrically connecting the electrodes.

9 and 10, the first and second via holes 101 and 102 and the lower surface of the carrier substrate 100 are plated with a conductive material to form the first type electrode pad 250 and the second type electrode pad ( The first and second connection circuits electrically connecting the type 1 electrode layer 210, the type 1 electrode pad 250, and the type 2 electrode layer 230 and the type 2 electrode pad 260 to each other by forming a 260 ( 270/280). In this case, the first and second connection circuits 270/280 and the type 1 and type 2 electrode pads 250/260 may be simultaneously formed.

Here, the conductive material for the first and second connection circuits 270/280 is any one or a plurality of materials selected from Au, Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, etc. It may be formed in a multi-layer, but is not limited thereto.

The first and second connection circuits 270/280 may be formed through plating, and may be applied by using electroplating, electroless plating, screen printing, vacuum deposition, or the like.

Thereafter, the type 1 electrode pad 250 and the type 2 electrode pad 260 are surface treated for stable soldering with a circuit of an external device. As the surface treatment method, hot air solder leveling (HASL), organic solderability preservative (OSP), electroless Ni / Au plating, and Sn plating may be applied, but are not limited thereto.

Here, the surface treatment of the lower surfaces of the type 1 and type 2 electrode pads 250/260 may be plated with Ni, Au, Ag, and the like, and the process of forming the first and second connection circuits 270/280 and one continuous It can also be processed by a process. In addition, the first and second electrode pads 250 and 260 may be surface treated after the silicone resin layer 310 is coated.

11, the phosphor layer 300 is formed by coating a phosphor on the epi layer 200, the type 2 electrode layer 230, the insulating layer 240, and the first and second connection circuits 270/280. Next, the silicon resin layer 310 is formed by coating a silicone resin on the surface of the phosphor layer 300, and finally, a scribe area that is a boundary between one light emitting device package chip and another adjacent light emitting device package chip. The process is completed by dividing into individual light emitting device package chips through dicing or breaking.

Here, the phosphor and the silicone resin may be applied to a thickness of about 50 μm by controlling the rotation speed of the spin coating. The coating of the phosphor and the silicone resin may be formed by a dispensing method, a molding method, or the like, or may be applied by mixing these methods.

The method of manufacturing an LED package according to the first embodiment of the present invention integrates a chip process and a carrier substrate 100 process to manufacture a package at a wafer level in the entire process, thereby significantly reducing production costs. However, since the epi layer 200 is not formed on the first and second via holes 101/102 formed in the carrier substrate 100, vias for forming an electrical connection circuit between the electrodes may be formed in one process. In addition, the epi layer 200 may be prevented from being damaged and deteriorated in reliability.

In addition, a series of processes for forming a carrier substrate, chip formation, and package are integrated into one, thereby significantly reducing production costs since the functional role of the carrier substrate 100 and the connection between the electrodes of the chip and the circuit are made in units of wafers. can do.

&Lt; Embodiment 2 >

FIG. 19 is a local cross-sectional view illustrating an LED package according to a second embodiment of the present invention. As shown in FIG. 19, a carrier substrate 100, a via hole 103, a bonding layer 110, an epitaxial layer 200, and FIG. Type electrode layer 210, epi layer via 220, type 2 electrode layer 230, first and second insulating layers 241/242, type 1 electrode pad 250, type 2 electrode pad 260, The first connection circuit 270 and the second connection circuit 280 are configured to be included.

Here, the parts having the same or similar effects as those of the first embodiment among the components of the second embodiment of the present invention use the same reference numerals as the first embodiment, and a repetitive description thereof will be omitted.

The carrier substrate 100 is a portion that simultaneously serves as a submount, and has a via hole 103 vertically penetrating the upper and lower surfaces thereof.

Here, the diameter of the via hole 103 may be formed in a range of 10 to 100 μm, and may be spaced apart from each other according to the size of the final finished product, the size of the chip, and the pattern of the epi layer 200.

That is, the via hole 103 is a passage for electrically connecting the type 1 electrode layer 210 and the type 1 electrode pad 250 through the conductive material, which is the first connection circuit 270, and at the same time, the type 1 electrode layer 210, After insulating the first type electrode pad 250 and the first connection circuit 270 with the second insulating layer 242, the second type electrode layer 230 and the second type electrode pad 260 may be the second connection circuit 280. It serves as a passage for electrically connecting through the conductive material.

The first type electrode layer 210 is formed in a predetermined pattern before the epi layer 200 is etched to form the epi layer via 220 and the mesa pattern, and then the epi layer via 220 and the mesa pattern are formed by plasma dry etching. It can be formed at the same time.

The epi layer via 220 is formed by vertically penetrating the epi layer 200 and the type 1 electrode layer 210 positioned on the via hole 103.

The epi layer via 220 is formed larger than the via hole 103.

The epi layer via 220 and the via hole 103 are passages for electrically connecting the type 1 electrode layer 210, the type 1 electrode pad 250, and the type 2 electrode layer 230 and the type 2 electrode pad 260. Play a role.

The first insulating layer 241 is formed by deposition and a pattern on the top edge of the carrier substrate 100, the sidewall of the epi layer 200, and the inner wall of the epi layer via 220. ) And the active layer 203 and the type 1 electrode layer 210 are electrically insulated.

The first insulating layer 241 may be formed of a material such as silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), or the like, and may be formed by chemical vapor deposition.

The first connection circuit 270 forms a through electrode together with the via hole 103, which is an electrical passage between the electrodes, and the via hole 103 vertically penetrates the carrier substrate 100 and the epi layer 200. It can be formed by coating the inner wall of the conductive material.

In the process of forming the first connection circuit 270, the type 1 electrode pad 250 is formed together.

The first connection circuit 270 and the first electrode pad 250 may be formed by plating, and may be applied by using electroless plating, electroplating, screen printing, vacuum deposition, or a combination of these methods. have.

The second insulating layer 242 is formed on the surfaces of the first type electrode layer 210, the first connection circuit 270, and the first type electrode pad 250 to form the first type electrode layer 210, the first connection circuit 270, and the like. The type 1 electrode pad 250 is electrically insulated.

Like the first insulating layer 241, the second insulating layer 242 may be formed of a material such as silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), or the like, and may be formed by chemical vapor deposition.

After forming the second insulating layer 242, the second connection circuit 280 forms a through electrode together with the via hole 103, which is an electrical passage between the electrodes, similarly to the first connection circuit 270. The via hole 103 vertically penetrating the carrier substrate 100 and the epi layer 200 may be filled with a conductive material or may be formed by coating an inner wall thereof with a conductive material.

In the process of forming the second connection circuit 280, the type 2 electrode pad 260 is formed together.

The second connection circuit 280 and the type 2 electrode pad 260 may be formed by plating, and may be applied using electroless plating, electroplating, screen printing, vacuum deposition, or the like, or a combination thereof. have.

Thereafter, the type 1 electrode pad 250 and the type 2 electrode pad 260 are surface treated for stable soldering with a circuit of an external device. Surface treatment may be applied to Hot Air Solder Leveling (HASL), Organic Solderability Preservative (OSP), electroless Ni / Au plating and Sn plating, but is not limited thereto.

Here, the surface treatment of the type 1 and type 2 electrode pads 250/260 may be plated with Ni, Au, and Ag, and may be treated with a process of forming the second connection circuit 280 and one continuous process.

In addition, the first and second electrode pads 250 and 260 may be surface treated after the silicone resin layer 310 is coated.

The phosphor layer 300 and the silicone resin layer 310 are for protecting the light emitting device and improving the light condensing efficiency, and include an epi layer 200, a second insulating layer 242, and first and second connection circuits 270/280. After coating the phosphor layer 300 on the), it is formed by sequentially coating the silicone resin layer 310 thereon.

The LED package P ′ according to the second embodiment of the present invention can further increase the integration degree by minimizing the space required for the electrical connection between the chip and the carrier substrate 100 as well as the effects of the first embodiment described above. And via one via located at the bottom of the space occupied by the chip, the type 1 and type 2 electrode layers 210/230 of the chip and the type 1 and type 2 electrode pads 250/260 below the carrier substrate are electrically connected to each other. The three-dimensional structure is formed.

In particular, a single via disposed under the chip by being insulated by the first and second insulating layers 241/242 may be used to form the second type electrode layer 230 without an electrical short between the type 1 electrode layer 210 and the first connection circuit 270. ) Is connected to maximize the degree of integration, and also because there is no epi layer 200 on the via hole 101, it is possible to prevent damage or crack generation of the epi layer during the manufacturing process as well as to improve reliability.

A method of manufacturing the LED package according to the second embodiment of the present invention configured as described above will be described with reference to FIGS. 12 to 20.

Referring to FIG. 12, the type 1 electrode layer 210 is deposited and patterned on the epitaxial layer 200 surface of the growth substrate 400, and the epitaxial layer 200 is etched to form at least one epitaxial via 220. Form a mesa pattern.

In this case, the epi layer via 220 and the mesa pattern may be formed by etching the epi layer 200 after removing the growth substrate 400 through wafer bonding and an LLO process. Here, the type 1 electrode layer 210 may simultaneously perform the role of ohmic bonding and the wafer bonding layer, or may include a layer for separate wafer bonding.

The epitaxial via 220 and the growth substrate 400 having the mesa pattern are bonded to each other on the carrier substrate 100 having the bonding layer 110 deposited thereon, and then bonded to the epitaxial layer on the carrier substrate 100. The process of removing the growth substrate 400 except for the type 200 and the type 1 electrode layer 210 may be performed in the same manner as in the above-described first embodiment.

However, when the epi layer vias 220 are processed and processed in the same way as the via holes 103 to form the same size, the electrical connection of the type 1 electrode layer 210 becomes difficult, and thus the epi layer vias 220 are formed. It is to be formed larger than the via hole 103 through the etching process before or after the process of removing the growth substrate 400, the via hole 103 is preferably processed in a separate process.

13, the second type electrode layer 230 is deposited and patterned on the upper surface of the epi layer 200 around and around the epi layer via 220. In this case, the type 2 electrode layer 230 connected to the type 2 electrode pad 260 through the epi layer via 220 may be located anywhere on the upper surface of the epi layer 200.

Here, the type 2 group 3-5 semiconductor layer 202 constituting the epi layer 200 may be removed while leaving only the necessary thickness through plasma dry etching, and then the type 2 electrode layer 230 may be formed thereon by vacuum deposition.

The two-type electrode layer 230 is made of, for example, Ni, Ag, Ti, Au, Cu,, Al, Rh, Ir, Ru, Pt, Pd, Cr, Mo, W, Sn, indium tin oxide (ITO), or the like. Alternatively, two or more may be selected to form a multilayer.

Thereafter, a first insulating layer 241 is formed on the top edge of the carrier substrate 100, the inner wall of the epi layer via 220, the side wall of the epi layer 200, and a portion of the type 1 electrode layer 210.

The first insulating layer 241 insulates current leaking from the type 1 and type 2 to group 3-5 semiconductor layers 201 and 202 of the epi layer 200, and forms the type 1 and type 2 electrode layers 210 and 230. This prevents them from being electrically connected to each other.

The first insulating layer 241 may be formed of a material such as silicon dioxide (SiO 2), silicon nitride (Si 3 N 4), or the like, and may be formed by chemical vapor deposition.

14, a via hole 103 perpendicularly penetrating the carrier substrate 100 in which the epi layer via 220 is located is formed.

The via holes 103 may be formed as fine vias of several tens of micrometers or less using laser drilling as a passage for electrically connecting the electrodes.

15, an epitaxial via 220 and an inner wall of the via hole 103 and a portion of the lower surface of the carrier substrate 100 are plated with a conductive material to form a type 1 electrode pad 250 while forming a type 1 electrode layer. A first connection circuit 270 for electrically connecting the 210 and the type 1 electrode pad 250 is formed. In this case, the first connection circuit 270 and the first type electrode pad 250 may be formed at the same time.

16 and 17, in addition to forming the second insulating layer 242 on the upper surface of the carrier substrate 100 to insulate the first connection circuit 270 and the first type electrode layer 210, the carrier substrate may be formed. A second insulating layer 242 is also formed on the bottom surface of the carrier substrate 100 to insulate the type 1 electrode pad 250 formed on the bottom surface of the substrate 100.

The pattern of the second insulating layer 242 may be formed by wet etching after laminating a pattern on both sides of a photosensitive dry film. If the second insulating layer 242 is patterned using a liquid photoresist, the photoresist may be difficult to protect the inner wall of the via hole 103, and thus wet etching may not be possible.

That is, the liquid photoresist is applied by spin coating, which is not easy to apply to the edge and the inner wall of the via hole 101, so that the first insulating layer 241 formed in the via hole 103 may be protected from wet etching. Unexpected problems may arise.

The second insulating layer 242 prevents the first connection circuit 270 and the first type electrode layer 210, the second connection circuit 280, and the type 2 electrode layer 230 from being electrically connected to each other.

18 and 19, the upper surface of the type 2 electrode layer 230 and the carrier substrate 100 are formed through the epi layer via 220 and the via hole 103 on which the second insulating layer 242 is deposited. By forming a second type electrode pad 260 by plating a portion of the lower surface with a conductive material, a second connection circuit 280 electrically connecting the type 2 electrode layer 230 and type 2 electrode pad 260 is formed. In this case, the second connection circuit 280 and the type 2 electrode pad 260 may be formed at the same time.

Here, the conductive material for the first and second connection circuits 270/280 is any one or a plurality of materials selected from Au, Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag, etc. It may be formed in a multi-layer, but is not limited thereto.

In addition, the first and second connection circuits 270/280 may be formed by plating, and may be applied by using electroplating, electroless plating, screen printing, vacuum deposition, or the like.

Subsequently, the bottom surfaces of the type 1 electrode pad 250 and the type 2 electrode pad 260 are surface-treated for stable soldering with a circuit of an external device. Surface treatment may be applied to Hot Air Solder Leveling (HASL), Organic Solderability Preservative (OSP), electroless Ni / Au plating and Sn plating, but is not limited thereto.

The surface treatment of the lower surfaces of the type 1 and type 2 electrode pads 250/260 may be plated with Ni, Au, Ag, etc. It may be.

20, the phosphor layer 300 is formed on the epi layer 200, the second insulating layer 242, and the second connection circuit 280 to form a phosphor layer 300, and then the phosphor layer 300. To form a silicone resin layer 310 by coating a silicone resin on the surface of the semiconductor layer), and finally, dicing or breaking along a scribe area, which is a boundary between one light emitting device package chip and another adjacent light emitting device package chip. The process is completed by separating the individual light emitting device package chips.

Here, the phosphor and the silicone resin may be coated with a thickness of about 50 μm by controlling the number of rotations of the spin coating. The coating of the phosphor and the silicone resin may be formed by a dispensing method, a molding method, or the like, and these methods may be used in combination.

The manufacturing method of the LED package according to the second embodiment of the present invention can maximize the integration of the chip by forming only one via.

On the other hand, the present invention is included in at least one embodiment described above, and is not limited by one embodiment and the accompanying drawings, various modifications and applications that are not illustrated within the scope without departing from the spirit of the invention It is apparent to those skilled in the art that the present invention can be changed as well as substitution of components and equivalent other embodiments. Therefore, contents related to the modification and application of the features of the present invention should be construed as being included within the scope of the present invention.

100: carrier substrate 101: first via hole
102: second via hole 103: via hole
110: bonding layer
200: epi layer 201: type 1 group 3-5 semiconductor layer
202: Group 2 type 3-5 semiconductor layer 203: Active layer
210: type 1 electrode layer 220: epi layer via
230: type 2 electrode layer 240: insulating layer
241: first insulating layer 242: second insulating layer
250: type 1 electrode pad 260: type 2 electrode pad
270: first connection circuit 280: second connection circuit
300: phosphor layer 310: silicone resin layer
400: growth substrate

Claims (11)

A carrier substrate on which first and second via holes penetrate vertically;
An epitaxial layer formed on an upper surface of the carrier substrate;
A type 1 electrode layer formed between the carrier substrate and the epi layer;
An epi layer via formed vertically through the epi layer and the type 1 electrode layer positioned on the second via hole;
A type 2 electrode layer formed on an upper surface of the epi layer around and around the epi layer via;
An insulating layer formed on the epi layer and the epi layer via, and insulating the epi layer and the type 1 electrode layer;
Type 1 and type 2 electrode pads formed on the bottom surface of the carrier substrate in correspondence with the type 1 and type 2 electrode layers;
A first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad through the first via hole;
A second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad through the epi layer via and the second via hole;
LED package comprising a.
A carrier substrate having via holes vertically therethrough;
An epitaxial layer formed on an upper surface of the carrier substrate;
A type 1 electrode layer formed between the carrier substrate and the epi layer;
An epi layer via formed vertically through the epi layer and the type 1 electrode layer positioned on the via hole;
A type 2 electrode layer formed on an upper surface of the epi layer around and around the epi layer via;
A first insulating layer formed on the epi layer and the epi layer via and insulating the epi layer and the type 1 electrode layer and the type 2 electrode layer;
Type 1 and type 2 electrode pads formed on the bottom surface of the carrier substrate in correspondence with the type 1 and type 2 electrode layers;
A first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad through the via hole;
A second insulating layer formed on surfaces of the first electrode layer, the first connection circuit, and the first electrode pad to prevent electrical shorts between the first electrode layer and the second electrode layer;
A second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad electrode through the via hole and the epi layer via;
LED package comprising a.
The method according to claim 1 or 2,
The epi layer is formed between the type 1 and type 2 group 3-5 semiconductor layers stacked on the type 1 electrode layer and the type 1 and type 2 group 3-5 semiconductor layers to generate light by recombination of electrons and holes. LED package comprising an active layer.
The method according to claim 1 or 2,
The carrier substrate is an LED package made of aluminum nitride (AIN).
LED package manufacturing method comprising each of the following steps.
(a) Process of depositing and patterning a type 1 electrode layer on the epi layer surface of the growth substrate
(b) etching the epi layer to form at least one epi layer via and a mesa pattern
(c) bonding the growth substrate on which the epi layer via and the mesa pattern are formed, onto a carrier substrate on which a bonding layer is deposited;
(d) removing the growth substrate except for the epi layer and the type 1 electrode layer;
(e) depositing a type 2 electrode layer on top of the epi layer around and around the epi layer via
(f) depositing and patterning an insulating layer on the inner wall of the epi layer via, the sidewall of the epi layer, and the type 1 and type 2 electrode layers
(g) forming first and second via holes vertically penetrating the carrier substrate on which a portion of the bonding layer and the epi layer vias are located;
(h) plating the lower surfaces of the first and second via holes and the carrier substrate with a conductive material to form a type 1 electrode pad and a type 2 electrode pad, while forming the type 1 electrode layer and type 1 electrode pad and type 2 electrode layer and type 2 electrode; Forming first and second connection circuits electrically connecting the electrode pads
LED package manufacturing method comprising each of the following steps.
(a) depositing a type 1 electrode layer on the epi layer surface of the growth substrate;
(b) bonding the growth substrate on which the epitaxial layer and the type 1 electrode layer are formed, onto a carrier substrate on which a bonding layer is deposited;
(c) removing the growth substrate except for the epitaxial layer and the type 1 electrode layer;
(d) depositing and patterning a type 2 electrode layer on the epitaxial upper surface
(e) etching the epi layer to form at least one epi layer via and a mesa pattern
(f) patterning the bonding layer between the type 1 electrode layer and the carrier substrate;
(g) depositing and patterning an insulating layer on the inner wall of the epi layer via, the sidewall of the epi layer, and the type 1 and type 2 electrode layers
(h) forming first and second via holes vertically penetrating the carrier substrate on which a portion of the bonding layer and the epi layer vias are located;
(i) forming the first type electrode pad and the second type electrode pad by plating the lower surface of the first and second via holes and the carrier substrate with a conductive material to form the type 1 electrode pad and type 1 electrode pad and type 2 electrode layer and type 2 Forming first and second connection circuits electrically connecting the electrode pads
LED package manufacturing method comprising each of the following steps.
(a) depositing a type 1 electrode layer on the epi layer surface of the growth substrate;
(b) bonding the growth substrate on which the epitaxial layer and the type 1 electrode layer are formed, onto a carrier substrate on which a bonding layer is deposited;
(c) removing the growth substrate except for the epitaxial layer and the type 1 electrode layer;
(d) depositing and patterning a type 2 electrode layer on the epitaxial upper surface
(e) forming a mesa pattern by etching the epi layer
(f) patterning the bonding layer between the type 1 electrode layer and the carrier substrate;
(g) forming first and second via holes vertically penetrating the portion of the bonding layer and the carrier substrate while forming epi layer vias in the epi layer;
(h) depositing and patterning an insulating layer on the inner walls of the epi layer vias, sidewalls of the epi layer, type 1 and type 2 electrode layers
(i) forming the first type electrode pad and the second type electrode pad by plating the lower surface of the first and second via holes and the carrier substrate with a conductive material to form the type 1 electrode pad and type 1 electrode pad and type 2 electrode layer and type 2 Forming first and second connection circuits electrically connecting the electrode pads
LED package manufacturing method comprising each of the following steps.
(a) Process of depositing and patterning a type 1 electrode layer on the epi layer surface of the growth substrate
(b) etching the epi layer to form an epi layer via and a mesa pattern
(c) bonding the growth substrate on which the epi layer via and the mesa pattern are formed on a carrier substrate on which a bonding layer is deposited;
(d) removing the growth substrate except for the epi layer and the type 1 electrode layer;
(e) depositing a type 2 electrode layer on top of the epi layer around and around the epi layer via
(f) depositing and patterning a first insulating layer on an inner wall of the epi layer via, a side wall of the epi layer, and a type 1 electrode layer
(g) forming via holes vertically penetrating the carrier substrate on which the epilayer vias are located;
(h) forming a first connection circuit electrically connecting the type 1 electrode layer and the type 1 electrode pad by forming a type 1 electrode pad by plating a portion of a lower surface of the carrier substrate with a conductive material;
(i) depositing and patterning a second insulating layer on the first electrode layer, the first connection circuit, and the first electrode pad;
(j) forming a second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad through the epi layer via and the via hole in which the second insulating layer is formed, and plating a portion of the lower surface of the carrier substrate with a conductive material; Process of forming 2 type electrode pad
LED package manufacturing method comprising each of the following steps.
(a) depositing a type 1 electrode layer on the epi layer surface of the growth substrate;
(b) bonding the growth substrate on which the epitaxial layer and the type 1 electrode layer are formed, onto a carrier substrate on which a bonding layer is deposited;
(c) removing the growth substrate except for the epitaxial layer and the type 1 electrode layer;
(d) depositing and patterning a type 2 electrode layer on the upper surface of the epitaxial layer
(e) forming an epitaxial via and a mesa pattern by etching the epitaxial layer
(f) patterning the bonding layer between the type 1 electrode layer and the carrier substrate;
(g) depositing and patterning an insulating layer on the inner wall of the epi layer via, the side wall of the epi layer, the type 1 electrode layer and the type 2 electrode layer
(h) forming a via hole vertically penetrating the carrier substrate on which the epilayer vias are located;
(i) forming a first connection circuit for electrically connecting the type 1 electrode layer and the type 1 electrode pad while forming a type 1 electrode pad by plating a portion of a lower surface of the carrier substrate with a conductive material;
(j) depositing and patterning a second insulating layer on the first electrode layer, the first connection circuit, and the first electrode pad;
(k) forming a second connection circuit electrically connecting the type 2 electrode layer and the type 2 electrode pad through the epi layer via and the via hole on which the second insulating layer is formed, and plating a portion of the lower surface of the carrier substrate with a conductive material; Process of forming 2 type electrode pad
The method according to any one of claims 5 to 9,
After forming the type 1 electrode pad and the type 2 electrode pad, each of the lower surface of the LED package manufacturing method characterized in that the surface treatment for soldering and external circuit.
The method according to any one of claims 5 to 9,
The epi layer of step (a) is formed between the type 1 and type 2 group 3-5 semiconductor layers formed on the type 1 electrode layer and the type 1 and type 2 group 3-5 semiconductor layers and recombines electrons and holes. LED package manufacturing method comprising an active layer for generating light by.

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