WO2013081328A1

WO2013081328A1 - Light emitting diode package and method of manufacturing light emitting diode package

Info

Publication number: WO2013081328A1
Application number: PCT/KR2012/009904
Authority: WO
Inventors: Jin Sung Park; Ho Sang Yoo; Sang Bum Kwon; Kum Jung Lee
Original assignee: Jin Sung Park
Priority date: 2011-11-29
Filing date: 2012-11-22
Publication date: 2013-06-06
Also published as: KR101128261B1

Abstract

A light emitting diode (LED) package having two vias (101, 102) and one epitaxial (epi) via (102) for electrical connections includes a carrier substrate (100), an LED chip, an epi layer (200), a bonding layer (110), two electrodes (210, 230), two conductors through the vias, two pads (250, 260) on the bottom of the carrier substrate and a passivation layer (240). The two vias are formed through the carrier substrate. The epi layer via is formed through the epi layer and the first electrode. Another LED package having a via and an epi layer via for electrical connections includes sub strate, an LED chip, an epi layer, a bonding layer, two electrodes, two conductors the via, two passivation layers (241, 242) for electrical insulation and two pads on the bottom of the carrier substrate. All electrical connections are formed through the single via and the epi layer via. The two conductors are isolated by the second passivation layer. A

Description

LIGHT EMITTING DIODE PACKAGE AND METHOD OF MANUFACTURING LIGHT

EMITTING DIODE PACKAGE

[Technical Field]

The present disclosure generally relates to a light emitting diode (LED) package, and more particularly to a wafer-level LED package and methods of fabricating the same.

[Background Art]

A Group III-V nitride semiconductor has been highlighted as an essential material to lighting devices such as an LED and a laser diode. The LED has a longer lifespan and consumes less power than conventional light sources such as an incandescent light and a fluorescent light. Despite various merits of LED illumination, as LED illumination is costly, the market for LED illumination is not increasing much. Even if the price of LED lamps is decreased rapidly as increasing the luminous efficacy (decreasing the cost per lumen), the production cost of LED package is still too high compared to conventional lamps.

The fabrication of typical LED package includes the epitaxial (epi) process of growing epi layers on a growth substrate, FAB of machining the epi layers grown on the growth substrate to form LED chips by metallization, patterning, etching and dielectric layer deposition, and the packaging process of mounting a LED chip diced off from the growth substrate to a submount or a carrier substrate, electrically connecting electrodes on the LED chip to pads on the carrier substrate by wire bonding and encapsulating LED chips on the carrier substrate by molding.

The packaging process may be costly, time consuming and low productivity. In conventional LED package fabricaton, an LED chip, a submount and/or a carrier substrate are fabricated in other manufacturers or sites, and then LED package manufacturers use LED chips and submounts and/or carrier substrates supplied from other manufacturers as raw materials. That is, an LED package is fabricated by processes to assemble these kinds of raw materials.

In recent years, in order to achieve high productivity, a Wafer Level Package (WLP) technique of fabricating an LED package on a wafer level has been applied instead of the conventional packaging processes which are carried out using individual LED chips diced off from the growth substrate. WLP has shown good results in terms of performance. However, in WLP not all of the processes are carried out on a wafer level. That is, some processes of WLP are still carried out using individual LED chips separately fabricated in FAB. Moreover, WLP is not wafer batch process that generally produces several tens of wafers from one single process. As a result, this may lead to a rise in production cost.

An existing WLP technique is a complicated packaging method including the fabrication of submount substrate, dicing the submount substrate on which individual LED chips are bonded, attaching the diced submount substrate to a carrier substrate, electrically connecting electrodes on the individual LED chips to pads on the carrier substrate using a wire bonding or Flipchip bonding process, and encapsulating the individual LED chips on the carrier substrate using silicone or epoxy resin. Thus, WLP may still be costly, time- consuming and low productivity.

An example of an LED package processed on a wafer level in all processes is a Chip Scale LED package disclosed in Korean Laid-open Patent No. 10-2007-0041729. The disclosed Chip Scale LED package is a Vertical LED, and the LED chips are electrically connected through two vias formed in a carrier substrate on a wafer level. After the two vias are formed in the carrier substrate, conductive material is deposited on the vias for electrical connection between electrodes on LED chips and pads on the bottom of the carrier substrate.

As shown in FIG. 1 , the Chip Scale LED package is configured such that an epi layer 20 that is a few of micrometers thick is placed on a carrier substrate 10 having two vias, and the epi layer 20 on the via 11 in the central part of the carrier substrate 10 is suspended in the air. As a result, the epi layer 20 may be easily damaged or broken during subsequent processes, and the LED package may have reliability problems.

As shown in FIG. 2, when the via 11 is filled with a resin or conductive material to prevent the damage of the epi layer 20, stress may be locally concentrated on the epi layer 20 and the interface between the filled material 27 and the epi layer 20 due to large differences in the coefficient of thermal expansion of the filled material 27, the epi layer 20 and the carrier substrate 10. When the internal temperature of the LED package is raised during the use thereof, the filled material 27 are locally expanded so that epi layer crack may be encountered in the few-micrometers thick epi layer 20 on the via 11.

Furthermore, as the epi layer 20 blocks the upper portion of the via 1 1, a process of connecting or filling the inside of the via 1 1 with a resin or conductive material 27 may be performed before the epi layer 20 is bonded to the carrier substrate 10 and transferred from a growth substrate (not shown in FIG. 1 and 2.). That is, due to the structural characteristics, metallization on the two vias may not be simultaneously formed using a single process. Thus, more processes are needed for the electrical connection between electrodes on a LED chip and pads on the bottom of the carrier substrate 10. As a result, the processes for the electrical connections are more complicated, which may affect productivity and quality.

In order to solve these problems, both of the vias should be in the outer portion of LED chip. However, more space for forming vias in the outer portion of LED chip is needed, thereby decreasing the number of chips that is produced per wafer. That is, integrity density is decreased.

[Disclosure of Invention]

The present invention provides an LED package that is produced using wafer batch process. Unlike the conventional WLP, the LED packages shown in FIGS. 1 1 and 20 are processed on a wafer level in all processes, and an LED chip and a carrier substrate are simultaneously formed in wafer batch processes without using an individual LED chip, a submount and/or a carrier substrate that are separately fabricated in other sites as finished products. Thus, productivity is increased because the LED package is fabricated by wafer batch processes and LED chips and carrier substrates are fabricated simultaneously. Wafer batch process generally produces several tens of wafers and thousands or tens of thousands of the LED packages per wafer are produced. However, conventional LED package is fabricated one by one by processes to assemble individual LED chips and raw materials as described above.

In addition, integration density is increased as minimizing a space required to form electrical connections between electrodes on an LED chip and pads on a carrier substrate. In conventional LED package, gold wire bonding is typically needed to form electrical connections between electrodes on an LED chip and pads on a carrier substrate. The gold wire bonding requires a space on a carrier substrate around an LED chip. In this invention, a carrier substrate also functions as a submount so that no additional submount is needed.

Furthermore, since the LED packages are a kind of Chip Scale Package (CSP), the

LED packages are reduced in size, weight and the use of raw materials is reduced. Thus, the production cost is reduced. In addition, since the thin epi layer 200 does not exist over a via, crack or damage in the epi layer 200 is prevented from any stress during a fabrication process, and reliability performance is enhanced.

The present disclosure provides an LED package and a method of fabricating the same, in which the entire process is carried out on a wafer level without conventional high-priced packaging processes, thus improving LED chip integration density and productivity, and reducing production costs.

According to first exemplary embodiments described below, an LED package is provided. The LED package includes a carrier substrate through which first and second vias are formed, a bonding layer formed on the carrier substrate, an epi layer transferred to the carrier substrate from a growth substrate (the epi layer has typically first- and second-type Group III-V semiconductor layers and multi-quantumn well layers as an active layer), first and second electrodes formed in order to be electrically connected to the first- and second- type Group III-V semiconductor layers correspondingly, the first electrode formed between the bonding layer on the carrier substrate and the epi layer, the second electrode formed on the top surface, an epi layer via formed through the epi layer and the first electrode, a passivation layer formed for electrical insulation between the first and the second electrodes and preventing electrical leakage of the first- and second-type Group III-V semiconductor layers and the active layer, first and second pads on the bottom surface of the carrier substrate correspondingly formed to be electrically connected to the first and the second electrodes, first and second conductors correspondingly formed to electrically connect the first and the second electrodes to the first and the second pads through the two vias and the epi layer via.

According to second exemplary embodiments, an LED package is provided. The LED package includes a carrier substrate through which one single via is formed, a bonding layer formed on the carrier substrate, an epi layer transferred to the carrier substrate from a growth substrate, first and second electrodes formed in order to be electrically connected to the first- and second-type Group III-V semiconductor layers correspondingly, a first electrode formed between the bonding layer on the carrier substrate and the epi layer, a second electrode formed on the top surface, an epi layer via formed through the epi layer and the first electrode, a first passivation layer formed to prevent electrical leakage of the first- and second-type Group III-V semiconductor layers and the active layer, a first conductor through the via and and a first pad on the bottom surface of the carrier substrate simultaneously formed, a second passivation layer formed to prevent an electrical short between the first and the second electrodes, a second conductor through the via and the epi layer via on the second passivation, and a second pad on the bottom surface of the carrier substrate simultaneously formed.

In addition to the effects according to the first embodiments described above, the LED package having one single via according to the second embodiments may have the following effects. Integration density is further increased by minimizing a space required for electrical connection.

In this disclosure, methods of fabricating LED package are provided, The methods include depositions of electrode, bonding layer, conductor, pad and passivation, wafer to wafer bonding, epi layer lift off technique, wet and dry etching, masking, patterning, plating, drilling of via and metal finish.

[BRIEF DESCRIPTION OF DRAWINGS]

FIGS. 1 and 2 are cross-sectional drawings showing examples of the LED package disclosed in Korean Laid-open patent No. 10-2007-0041729.

FIG. 3 is a cross-sectional drawing showing first exemplary embodiments after a first electrode is deposited on an epi layer on a growth substrate.

FIG. 4 is a cross-sectional drawing showing the first exemplary embodiments after LED chips, epi layer vias and first electrodes are patterned.

FIG. 5 is cross-sectional drawings showing the first exemplary embodiments after the growth substrate is wafer-bonded to a carrier substrate on which a bonding layer is formed.

FIG. 6 is cross-sectional and plan drawings showing the first exemplary embodiments after the growth substrate is only removed.

FIGS. 7 (a) and (b) are cross-sectional and plan drawings showing the first exemplary embodiments aftr a second electrode and a passivation layer are deposited and patterned.

FIG. 7 (c) is cross-sectional and plan drawings showing the first exemplary embodiments after a passivation layer are deposited and patterned.

FIGS. 8 (a), (b) and (c) are cross-sectional and plan drawings showing the first exemplary embodiments after two vias are formed in the carrier substrate;

FIGS. 9 (a), (b) and (c) are cross-sectional and plan drawings showing the first exemplary embodiments after first and second pads and first and second conductors are formed. FIG. 10 is a bottom view showing the first exemplary embodiments after first and second pads and first and second conductors are formed.

FIG. 1 1 is a cross-sectional drawing showing the LED package of the first exemplary embodiments.

FIG. 12 is cross-sectional and plan drawings showing the LED package of second exemplary embodiments after the same processes as in the first exemplary embodiments up to the removal of the growth substrate are applied.

FIG. 13 (a) is cross-sectional and plan drawings showing the LED package of the second exemplary embodiments after a second electrode and a first passivation layer are deposited and patterned.

FIG. 13 (b) is cross-sectional and plan drawings showing the LED package of the second exemplary embodiments after a first passivation layer are deposited and patterned.

FIG. 14 (a) and (b) are cross-sectional and plan drawings showing the LED package of the second exemplary embodiments after one via is formed in a carrier substrate.

FIG. 15 (a) and (b) are cross-sectional and plan drawings showing the LED package of the second exemplary embodiments after a first pad and a first conductor are formed.

FIG. 16 (a) and (b) are cross-sectional and plan drawings showing the LED package of the second exemplary embodiments after a second passivation layer is deposited and patterned.

FIG. 17 is a bottom view showing the LED package of the second exemplary embodiments after the second passivation layer is deposited and patterned.

FIG. 18 (a) is a cross-sectional drawing showing the LED package of the second exemplary embodiments after a second pad and a second conductor are formed.

FIG. 18 (b) is a cross-sectional drawing showing the LED package of the second exemplary embodiments after a second electrode, a second pad and a second conductor are formed.

FIG. 19 is a bottom view showing the LED package of the second exemplary embodiments after the second pad and the second conductor are formed.

FIG. 20 is the cross-sectional drawing of the LED package of the second exemplary embodiments. [Best Mode for Carrying Out the Invention]

Exemplary embodiments of the present invention will become more apparent by describing in detailed embodiments of the present invention with reference to the accompanying drawings. The terms used herein is for descrbing embodiments of the invention and is not intented to be limiting of the invention. Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this invention belongs.

Descriptions of well-known functions, elements, components or layers are omitted so as not to unnecessarily obscure the embodiments of the present disclosure.

When an element or layer is referred to as being "on", "connected to", "bonded to/on",

"attached to/on" and "deposited to/on" another element or layer, there may be (an) intervening layer(s), component(s) or element(s) present between them, unless otherwise specified clearly.

The terms first and second may be only used herein to distinguish layers, elements and/or components. Thus, the terms should not be limited to these layers, elements and/or components.

In the drawings, each of elements are not exactly proportionate to actual sizes, thicknesses and lengths but may be exaggerated or simplified for ease of description and understanding. Furthermore, the various layers and regions illustrated in the figures are shown schematically. Accordingly, the present disclosure is not limited to the relative size and spacing illustrated in the accompanying drawings.

In some embodiments, an electrode underneath the epi layer may be used as the meaning of an electrode including a bonding layer for ease of explanation.

FIG. 11 is the cross-sectional view of an LED package according to first exemplary embodiments. As shown in FIG. 11, the LED package includes a carrier substrate 100, two vias 101 and 102, a bonding layer 1 10, an epi layer 200, a first electrode 210, an epi layer via 220, a second electrode 230, a passivation layer 240, first and second pads 250 and 260, first and second conductors 270 and 280.

The LED package shown in FIG. 11 will be described in more details with reference to the embodiments of FIG. 3 through FIG. 11.

Referrring to FIG. 3, an epi layer 200 is grown on a growth substrate 400. The growth substrate 400 may include sapphire (A1₂0₃), Si, SiC, GaAs, GaN, A1N and/or other substrates. The epi layer 200 includes first- and second- type Group III-V semiconductor layers 201 and 202, and an active layer 203 between the first- and the second-type Group III-V semiconductor layers 201 and 202. However, other epitaxial layers such as an electron- blocking layer and a buffer layer may be further disposed above or below any of the semiconductor layers. Thus, the epi layer 200 may includes multiple layers, all the epi layers are referred to as the epi layer 200 with no particular limitation. The epi layer 200 is transferred to a carrier substrate 100 using a Laser Lift Off (LLO) or any other conventional growth substrate lift off techniques after bonding the carrier substrate 100 and the growth substrate 400, as will be described below.

The first-type Group III-V semiconductor layer 201 formed on the growth substrate

400 is typically p-type. The active layer 203 on the first-type Group III-V semiconductor layer 201 emits light. The second-type Group III-V semiconductor layer 202 on the active layer 203 is typically n-type.

As shown in FIG. 3, a first electrode 210 is formed on the first-type semiconductor layer 201 for ohmic contact. The first electrode 210 may include multiple layers which are suitable for ohmic contact to the first-type Group III-V semiconductor layer 201. The first electrode 210 also serves as an optical-reflective layer to improve light extraction performance. In addition, the first electrode 210 is used for bonding the growth substrate 400 and the carrier substrate 100. An additional bonding layer may be formed on the first electrode 210.

Referring to FIG. 4, the first electrode 210 deposited on the epi layer 200 is masked, patterned and etched, and then the epi layer 200 is etched to form an epi layer via 220 and/or LED chips using conventional wet and/or dry etching techniques. The LED chip is herein referred to as a patterned epi layer in arbitrary size.

While three LED chips are shown in FIG. 4, the part having one LED chip is only depicted from FIG. 5 through 20.

As shown in FIG. 3 and 4, the first electrode 210 are deposited by vacuum deposition or the combination of vacuum deposition and plating technique, and patterned by conventional wet etching technique before forming the epi layer via 220 and/or patterning the epi layer 200 to form the LED chip as shown in FIG. 4. However, the first electrode 210 may be deposited and patterned after the epi layer 200 is etched to form the epi layer via 220 and/or the LED chip. The epi layer via 220 is formed through the epi layer 200 and the first electrode 210. The epi layer via 220 is equal to or greater than the diameter of a second via 102 (shown in FIG. 8) described in more details below. Thus, the epi layer via 220 and the second via 102 serve as a path of electrical connection between a second electrode 230 and a second pad 260, as will be described in more details below. Epi layer crack and/or damage may happen when epi layer is disposed over the second via 102. The epi layer via 220 and the LED chip may be simultaneously formed.

Referring to FIG. 5, the growth substrate 400 and the carrier substrate 100 having a bonding layer 110 are wafer-bonded facing each other using eutectic bonding technique or using adhesive materials such as cyclotene and polyimide of conventional Wafer to Wafer Bonding.

The carrier substrate 100 is aluminum nitride (A1N) which has a high thermal conductivity for the thermal management of LED package and minimal difference in the coefficient of thermal expansion between the carrier substrate 100 and the epi layer 200 for reliability performance. As a result, a LED package with A1N has shown high luminous efficacy and reliability performance, compared to other materials. Other suitable materials such as alumina (A1₂0₃), silicon, and BeO may be used as a carrier substrate.

Before the two substrates 100 and 400 are wafer-bonded, the bonding layer 100 is deposited on the carrier substrate 100 using a vacuum deposition, plating technique or the combination of vacuum deposition and plating technique. The bonding layer 100 may include multiple layers such as an adhesion layer, a diffusion barrier layer and a solder layer. Gold bearing materials such as AuSn, AuGe and AuSi are generally used for eutectic wafer bonding.

To enhance adhesive strength between the bonding layer 110 and the carrier substrate 100, the bonding layer 1 10 may include Ti and/or Ni as an adhesion layer and/ or a diffusion barrier layer. Any other suitable substances such as Cr, TiW, Pt, Nb and Pd may be included to the bonding layer 1 10.

The bonding layer 1 10 is patterned using wet etching technique, and then the growth substrate 400 is wafer-bonded to the carrier substrate 100 as shown in FIG. 5 (a). Referring to FIG. 5 (b), the two substrates 100 and 400 are wafer-bonded without patterning the bonding layer 110, and then the bonding layer 110 is masked, pattered and etched after removing the growth substrate 400 as shown in FIG. 6. Referring to FIG. 6, after wafer-bonding the two substrates 100 and 400, the growth substrate 400 is removed from the carrier substrate 100 using Lift Off techniques such as laser lift-off (LLO) and chemical lift-off (CLO), leaving the epi layer 200 and the first electrode 210 on the carrier substrate 100.

In some embodiments, patterning the first electrode 210 and etching the epi layer 200 may be performed after removing the growth substrate 400 bonded to the carrier substrate 100. The growth substrate 400 is wafer-bonded to the carrier substrate 100 without patterning the first electrode 210 and/or the epi layer 200, and then the growth substrate 400 is removed. The epi layer 200 is transferred upside-down to the carrier substrate 100, then. The second-type Group III-IV semiconductor layer 202 is revealed on the carrier substrate 100 after removing the growth substrate 400, and then the epi layer 200 is masked, patterned and etched. The first electrode 210 is exposed after etching the epi layer 200, and then the first electrode is masked, patterned and etched.

As mentioned above, in case that the wafer bonding is performed without patterning the first electrode 210 and the epi layer 200, the first electrode 210 and the epi layer 200 is masked, patterned and etched after removing the growth substrate 400, and then the bonding layer 1 10 is masked, patterned and etched after removing the growth substrate 400 in case that the bonding layer is not patterned before the wafer bonding process.

3 kinds of LED package structures in each of FIGS. 7, 8 and 9 are illustrated by the disposition of second electrode and/or how electrodes and pads are correspondingly connected.

Referring to FIGS. 7 (a) and (b), a second electrode 230 is deposited on the top surface using a vacuum deposition technique or the combination of vacuum deposition and plating technique, and then masked, patterned and etched using conventional wet etching technique. As shown in FIG. 7 (a), the second electrode 230 is patterned on the top surface of the epi layer 200 around the epi via 220, while the second electrode 230 is patterned on the edge surface of the epi layer 200 as shown in FIG. 7 (b).

The second electrode 230 may be formed in multiple layers such as Ti, Au, Cu, Al, ITO and other suitable substances. After the second electrode 230 is deposited, a passivation layer 240 is deposited using chemical vapor deposition (CVD) technique or physical vacuum deposition technique, and then masked, patterned and etched using conventional wet and/or dry etching technique. The passivation layer 240 is formed using a dielectric material such as silicon dioxide or silicon nitride. The second electrode 230 is formed to be electrically connected to the second-type Group III-V semiconductor layer 202. The second electrode 230 has ohmic contact to the second-type Group III-V semiconductor layer 202, and must be compatible with a technique to form conductors 270 and 280 described in more details below. Thus, the second electrode 230 makes electrical connection between the second-type Group III-V semiconductor layer 202 and a first pad 250 or a second pad 260, as will be discussed in more details below.

The passivation layer 240 prevents a leakage current of the first- and second-type Group III-V semiconductor layers 201 and 202 and the active layer 203, and prevents an electrical short between the first and the second electrodes 210 and 230.

Referring to FIG. 7 (c), a passivation layer 240 is first deposited before a second electrode 220 (not shown in FIG. 7 (c)) is deposited. As shown in FIG. 9 (c), the second electrode 220 is deposited before forming conductors 270 and 280, as will be decribed in more details below.

Referring to FIGS. 8 (a), (b) and (c), first and second vias 101 and 102 are formed through the carrier substrate 100 using laser drill technique or deep dry etching.

The vias 101 and 102 are routes through which the electrodes 210 and 230 are electrically connected to pads 250 and 260 described in more details below. The first and the second vias 101 and 102 may be formed before the deposition of the passivation layer 240.

Referring to FIG. 9 (a), FIG 9 (b) and FIG. 10 of bottom view, a seed layer (not shown) is deposited on the whole top and bottom surface, the inner walls of the two vias 101 and 102 and the inner wall of the epi via 220 using vacuum deposition and/or plating technique, the top and bottom surfaces are masked and patterned, and then the unmasked area is electroplated to simultaneously form first and second pads (250 and 260) and conductors (270 and 280) as contuctive traces to correspondingly connect among layers, electrodes and pads. After electro-plating the conductive traces on the unmasked area, the masking material is stripped by a chemical solution and the seed layer under the masking material is removed off by wet etching technique.

The conductive traces are referred to as all of the pads (250 and 260) and the conductors (270 and 280) herein. The seed layer is a conductive layer that serves as an adhesion promoter between different materials and makes a surface plated. As shown in FIG. 9 (a), the first electrode 210 is connected to the first pad 250 through the bonding layer 1 10 and the first conductor 270, and the second electrode 230 is connected to the second pad 260 through the second conductor 280.

As shown in FIG. 9 (b), the first electrode 210 is connected to the second pad 260 through the bonding layer 1 10 and the second conductor 280, and the second electrode 230 is connected to the first pad 250 through the first conductor 270.

Referring to FIGS. 9 (c) by which FIG. 7 (c) and FIG. 8 (c) are followed, the second electrode 230 is deposited on the whole top surface, the inner walls of the two vias 101 and 102 and the inner wall of the epi layer via 220 using vacuum deposition and/or plating techniques. In this case, the second electrode 230 may serve as a seed layer in order for electro-plating to simultaneously form the conductors (270 and 280) and the pads (250 and 260) as conductive traces like the fabrication method of FIGS. 9 (a) and (b). A seed layer (not shown) is deposited on the whole bottom surface to simultaneously form the conductors (270 and 280) and the pads (250 and 260) by electro-plating.

As shown in FIG. 9 (c), the first electrode 210 is connected to the second pad 260 through the bonding layer 110 and the second conductor 280, and the second electrode 230 is connected to the first pad 250 through the first conductor 270.

In some embodiments, the seed layer is masked, patterned and etched before forming the conductive traces. Then, the conductive traces are formed using electroless plating technique that makes the surface of the patterned seed layer plated selectively.

In general, the conductive traces and/or the seed layers may be formed in multiple layers such as Ti, Ni, Au, and Cu, but the present disclosure is not limited thereto. The first and the second conductors 270 and 280 are formed by plating conductive material to make the electrodes (210 and 230) and the pads (250 and 260) electrically connected correspondingly.

The two conductors 270 and 280 may be formed by vacuum deposition only. In this case, the first and the seconde pads 250 and 260 may not be formed simultaeneously with the two conductos 270 and 280.

A conductive material or resin may be filled into the inside of the two vias 101 and 102 and the epi via 220 by screen printing or dispensing technique.

The two pads 250 and 260 are metal-finished to be soldered to pads on a printed circuit board of LED module. Metal finish of the two pads 250 and 260 is dependent on what kind of electrical connection is applied for making a LED module. Thus, the two pads 250 and 260 may be finished by serval kinds of techniques such as electroless nickel and immersion gold plating, electroless nickel and electroless palladium and immersion gold plating, and organic solderability preservative technique, but the present disclosure is not lmited thereto. In case that plating technique is applied for the metal finish of the two pads 240 and 260, the two conductors 270 and 280 may be formed by the plating of metal finish. Thus, the two pads (240 and 260) and the two conductors (270 and 280) are simultaneously formed by the plating of metal finish.

Referring to FIG. 1 1 that illustrates one of the three LED package structures described above, a phosphor layer 300 is formed as an optional wavelength conversion layer using dispensing, spray coating, molding or any suitable methods, and then a transparent silicone or epoxy resin layer 310 is formed for mechanical and environmental protection to the LED package using dispensing, spray coating, molding or any suitable methods. The phosphor layer may include multiple layers in different colors. The phosphor layer may only be formed or the silicone or epoxy resin may only be formed.

An optical lens having a phosphor and/or adhesive layer may be attached to the LED package structures of FIGS 9 (a), (b) and (c). The optical lens may be fabricated separately in other sites.

FIG. 20 illustrates a LED package according to second exemplary embodiments. As shown in FIG. 20, the LED package includes a carrier substrate 100, a via 103, a bonding layer 110, an epi layer 200, a first electrode 210, an epi layer via 220, a second electrode 230, first and second passivation layers 241 and 242, first and second pads 250 and 260, first and second conductors 270 and 280.

Here, the same reference numerals are used to denote layers, elements, components having identical or similar effects to those of the above-described first embodiments, and repeated descriptions thereof will be omitted.

The LED package shown in FIG. 20 will be described in more details with reference to the embodiments of FIG. 12 through FIG. 20.

Referring to FIG. 12, like the embodiments of FIGS. 3, 4, 5 and 6, a first electrode 210 is deposited on an epi layer 200 grown on a growth substrate (not shown in FIG. 12), the first electrode 210 and the epi layer 200 is masked, patterned and etched to form an LED chip and an epi layer via 220, the growth substrate is wafer-bonded to a carrier substrate 100 having a bonding layer 110, and the growth substrate is removed. 2 kinds of LED package structures in each of FIGS. 13, 14, 15, 16, and 18 are illustrated by the disposition of second electrode.

Referring to FIG. 13 (a), like the embodiments of FIG. 7 (a), a second electrode 230 is deposited on the top surface, and then masked, patterned and etched. A first passivation layer 241 is deposited, maksed, patterned and etched. The first passivation layer 241 prevents current leakage of a first- and a second-type Group III-V semiconductor layers 201 and 202, and an active layer 203. Thus, the second electrode 230 is disposed on the top surface of the epi layer 200 around the epi via 220 under the second passivation layer 241.

Referring to FIG. 13 (b), a first passivation layer 241 is first deposited before a second electrode 230 (not shown in FIG. 13 (b)) is deposited. As shown in FIG. 18 (b), the second electrode 230 is deposited and patterned before forming a second conductor 280 (not shown in FIG. 13 (b)). Forming the second electrode 230 will be described in more details below.

Referring to FIG. 14, like the embodiments of FIG. 8, a via 103 is formed through the carrier substrate 100. In the second embodiments, one single via 103 serves as a path for both of the electrical connections of two electrodes and two pads, which will be describe below. Both of the electrical connections are insulated by a second passivation layer 242 deposited on a first conductor 270 and a first pad 250, which will be described below.

Referring to FIG. 15, like the embodiments of FIG. 9, a seed layer (not shown) is deposited on the whole surface, the inner wall of the via 103 and the inner wall of the epi via 220 using vacuum deposition and/or plating technique, the top and bottom surfaces are masked and patterned, and then the unmasked area is electro-plated to simultaneously form a first pad 250 and a first conductor 270 as contuctive traces to electrically connect between the first electrod 210 and the first pad 250. After electro-plating the conductive traces on the unmasked area, the masking material is stripped by a chemical solution and the seed layer under the masking material is removed off by wet etching technique.

Referring to FIGS. 16 and 17 of bottom view, a second passivation layer 242 is deposited on the top surface, the inner wall of the via 103 and the inner wall of the epi layer via 220 to insulate the first conductor 270 and the first electrode 210, and also deposited on the bottom surface to insulate the first pad 250 formed on the bottom surface of the carrier substrate 100 from a second pad 260 (not shown in FIG. 16 and 17) described below. The second passivation layer 242 is masked using a photosensitive dry film and patterned using wet etching technique. If a liquid photoresist is used for patterning the second passivation layer 242, the liquid photoresist may not be coated on the inner wall of the via 103 and the inner wall of the epi layer via 220. That is, the liquid photoresist may not mask the second passivation layer 242 on the inner walls of the via 103 and the epi layer via 220 because the liquid photoresist is typically coated on a surface using spin coating technique. The spin coating technique may not coat on a vertical surface because the spin coating technique uses centrifugal force.

Referring to FIGS. 18 (a) and 19 of bottom view, like the embodiments of FIG. 9 (a), FIG. 9 (b), FIG. 10 and FIG. 15, a seed layer (not shown) is deposited on the whole surface, the inner wall of the via 103 and the innerr wall of the epi via 220 using vacuum deposition and/or plating technique, the top and bottom surfaces are masked and patterned, and then the unmasked area is electro-plated to simultaneously form a second pad 250 and a second conductor 270 as contuctive traces to electrically connect between the second electrod 210 and the second pad 250. After electro-plating the conductive traces on the unmasked area, the masking material is stripped by a chemical solution and the seed layer under the masking material is removed off by wet etching technique. Subsequently, the first and the second pads 250 and 260 are metal-finished as described in the first embodiments.

Referring to FIGS. 18 (b) by which FIGS. 13 (b), 14 (b), 15 (b) and 16 (b) are followed, the second electrode 230 is deposited on the whole top surface, the inner wall of the via 101 and the inner wall of the epi layer via 220 using vacuum deposition and/or plating techniques. In this case, the second electrode 230 may serve as a seed layer in order for electro-plating to simultaneously form a second conductor 280 and a second pad 260 as conductive traces. A seed layer (not shown) is deposited on the whole bottom surface to simultaneously form the second conductor 280 and the second pad 260 by electro-plating.

Referring to FIG. 20 that illustrates one of the two LED package structures described above, a phosphor layer 300 is formed as an optional wavelength conversion layer using dispensing, spray coating, molding or any suitable methods, and then a transparent silicone or epoxy resin layer 310 is formed for mechanical and environmental protection to the LED package using dispensing, spray coating, molding or any suitable methods. The phosphor layer may include multiple layers in different colors. The phosphor layer is only formed or the silicone or epoxy resin is only formed.

An optical lens having a phosphor and/or adhesive layer may be attached to the LED packages. The optical lens may be fabricated separately in other sites. While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[Descriptions of the numbers in figures]

10: a Carrier Substrate in FIG. 1 and 2

1 1 : a Via in FIG. 1

20: an Epitaxial layer in FIG. 1 and 2

27: a Filled Material in FIG. 2

100: a Carrier Substrate

101 : a First Via for the first embodiments

102: a Second Via for the first embodiments

103: a Via for the second embodiments

1 10: a Bonding Layer

200: an Epitaxial Layer that includes the layers of 201, 202 and 203 201 : a First-Type Group III-V Semiconductor Layer

202: an Active Layer

203: a Second-Type Group III-V Semiconductor Layer

210: a First Electrode

220: an Epitaxial Layer Via

230: a Second Electrode

240: a Passivation Layer for the first embodiments

241 : a First Passivation Layer for the second embodiments

242: a Second Passivation Layer for the second embodiments

250: a First Pad

260: a Second Pad

270: a First Conductor

280: a Second Conductor

300: a Phosphore Layer

310: a Transparent Silicone or Epoxy Resin Layer as a Protection Layer

Claims

WHAT IS CLAIMED IS:

1. A light emitting diode (LED) package comprising:

a carrier substrate through which first and second vias are formed;

a bonding layer formed on the carrier substrate;

an epitaxial (epi) layer transferred to the carrier substrate from a growth substrate;

a first electrode formed between the bonding layer on the carrier substrate and the epi layer; a second electrode formed on the top surface of the epi layer;

an epi layer via formed through the epi layer and the first electrode layer;

a passivation layer formed for electrical insulation between the first and the second electrodes and the prevention of electrical leakage of first and second semiconductor layers and an active layer;

first and second pads in electrical connection to the first and the second electrodes correspondingly formed on the bottom surface of the carrier substrate; and

first and second conductors in electrical connection among the electrodes and the pads correspondingly formed through the two vias and the epi layer via.

2. The LED package of claim 1, wherein the carrier substrate includes aluminum nitride (A1N).

3. The LED package of claim 1, wherein a bonding layer is formed on the first electrode.

4. The LED package of claim 1, wherein a resin or conductive material is filled into the first via, the second via and the epi layer via.

5. The LED package of claim 1, wherein a seed layer is formed for electro-plating.

6. The LED package of claim 1, wherein the first and the second pads are metal-finished for soldering to pads on an LED module.

7. The LED package of claim 1, wherein a phosphor layer is formed on the top surface.

8. The LED package of claim 1, wherein a protective layer is formed on the top surface.

9. The LED package of claim 1, wherein a phosphore and a protective layer are formed on the top surface.

10. The LED package of claim 1 , wherein an optical lens is formed on tne top suriace.

11. The LED package of claim 1 , wherein an optical lens having a phosphor layer is formed on the top surface.

12. A light emitting diode (LED) package comprising:

a carrier substrate having a via formed through the carrier substrate;

a bonding layer formed on the carrier substrate;

an epi layer transferred to the carrier substrate from a growth substrate;

a first electrode formed between the bonding layer on the carrier substrate and the epi layer; an epi layer via formed through the epi layer and the first electrode;

a second electrode formed on the top surface of the epi layer;

a first passivation layer formed for the prevention of electrical leackage of first and second semiconductor layers and an active layer;

a first conductor in electrical connection between the first electrode and a first pad formed through the via;

first and second pads in electrical connection to the first and the second electrodes correspondingly formed on the bottom surface of the carrier substrate;

a second passivation layer formed to prevent an electrical short between the first and the second electrodes; and

a second conductor in electrical connection between the second electrode and the second pad formed on the second passivation and through the via and the epi layer via.

13. The LED package of claim 12, wherein the carrier substrate includes aluminum nitride (AIN).

14. The LED package of claim 12, wherein a bonding layer is formed on the first electrode.

15. The LED package of claim 12, wherein a resin or conductive material is filled into the via and the epi layer via.

16. The LED package of claim 12, wherein a seed layer is formed for electro-plating.

17. The LED package of claim 12, wherein the first and the second pads are metal-finished for soldering to pads on an LED module.

18. The LED package of claim 12, wherein a phosphor layer is lormed on tne top suriace.

19. The LED package of claim 12, wherein a protective layer is formed on the top surface.

20. The LED package of claim 12, wherein a phosphore and a protective layer are formed on the top surface.

21. The LED package of claim 12, wherein an optical lens is formed on the top surface of the epi layer.

22. The LED package of claim 12, wherein an optical lens having a phosphor layer is formed on the top surface.

23. A method of fabricating the LED package of claim 1, the method comprising:

(a) depositing a first electrode on the epi layer grown on a growth substrate, and patterning the first electrode;

(b) patterning the epi layer to form an LED chip and an epi layer via;

(c) bonding the growth substrate to a carrier substrate having a bonding layer;

(d) removing the growth substrate, leaving the epi layer and the first electrode on the carrier substrate;

(e) patterning the bonding layer;

(f) depositing a second electrode on the top surface, and patterning the second electrode;

(g) depositing a passivation layer on the top surface, and patterning the passivation layer;

(h) forming first and second vias through the carrier substrate; and

(i) forming first and second pads on the carrier substrate and first and second conductors.

24. A method of fabricating the LED package of claim 1, the method comprising:

(b) patterning the epi layer to form an LED chip and an epi layer via;

(c) bonding the growth substrate to a carrier substrate having a bonding layer;

(e) patterning the bonding layer; (f) depositing a passivation layer on the top surface, and patterning the passivation layer;

(g) forming first and second vias through the carrier substrate;

(h) depositing a second electrode on the top surface; and

25. A method of fabricating the LED package of claim 12, the method comprising:

(b) patterning the epi layer to form an LED chip and an epi layer via;

(c) bonding the growth substrate to a carrier substrate having a bonding layer;

(e) patterning the bonding layer;

(g) depositing a first passivation layer, and patterning the first passivation layer;

(h) forming a via through the carrier substrate;

(i) forming a first pad on the carrier substrate and a first conductor;

(j) depositing a second passivation layer, and patterning the passivation layer; and

(k) forming a second pad on the carrier substrate and a second conductor.

26. A method of fabricating the LED package of claim 17, the method comprising:

(b) patterning the epi layer to form an LED chip and an epi layer via;

(c) bonding the growth substrate to a carrier substrate having a bonding layer;

(e) patterning the bonding layer;

(f) depositing a first passivation layer, and patterning the first passivation layer;

(g) forming a via through the carrier substrate;

(h) forming a first pad on the carrier substrate and a first conductor;

(i) depositing a second passivation layer, and patterning the passivation layer;

(j) depositing a second electrode on the top surface; and

(k) forming a second pad on the carrier substrate and a second conductor.