KR101124434B1 - Predistortion System and Method for Memory Effects Compensation of Power Amplifier - Google Patents

Abstract

The present invention relates to a predistortion system and method capable of compensating the memory effect of a power amplifier by connecting a transmission line having a different signal delay from a transistor to a nonlinear path of a predistorter. According to an aspect of the present invention, a first power divider divides a signal input to a power amplifier into a first signal and a second signal, and receives a second signal and divides the signal into a plurality of signals and uses a plurality of distortion generators composed of transistors. A second path unit for generating a plurality of distortion signals having different delays and combining the plurality of distortion signals, a first path unit receiving a first signal and delaying the first signal by a second path unit, and A predistortion system is provided to compensate for the memory effect of a power amplifier comprising a first power combiner coupling the output of the first path portion and the second path portion.

Description

Predistortion System and Method for Memory Effects Compensation of Power Amplifier

The present invention relates to a linearization method of a power amplifier, and more particularly, a predistortion capable of compensating a memory effect of a power amplifier by connecting a transmission line having a different signal delay from a transistor to a nonlinear path of a predistorter. System and method.

Currently, wireless communication has strict linearity specifications for the accurate delivery of data. The power amplifier has a great influence on the linearity of the entire communication system. In order to improve the linearity of the power amplifier, forward feedback, backward feedback, digital predistortion, and analog predistortion have been studied.

Among them, the analog predistorter has the advantages of simple circuit and easy implementation, and by using the distorted signal generated by the analog predistorter as the input of the power amplifier, the distorted signal and the distortion signal produced by the power amplifier cancel each other. Improve the linearity of the power amplifier.

In recent years, memory phenomena have become a major factor in improving linearization of power amplifiers due to the widespread use of wideband signals such as wideband code division multiple access (WCDMA). The memory phenomenon is that the output of the past affects the magnitude and phase of the current output. The distortion of the high and low frequency components of the output spectrum is asymmetric. The memory effect is exacerbated as the bandwidth of the signal increases, thus affecting the limitations of linearity improvement in power amplifiers using broadband signals.

1 is a circuit diagram illustrating a general analog predistorter according to an exemplary embodiment, and includes a first signal generator 100a, a second signal generator 100b, a combiner 100c, a power divider 101, and a delay line ( 102, third-order distortion signal generator 103, variable attenuator 104, variable phase shifter 105, power combiner 106. Referring to FIG. 1, an analog predistorter according to an exemplary embodiment will be described.

Referring to FIG. 1, a signal generated by the signal generator 100 is divided into a first path part and a second path part through power distribution and output. The input signals f1 and f2, which are input signals from the first signal generator 100a and the second signal generator 100b, are combined and output through the combiner 100c, and the output signal is input to the power divider 101. Here, f1 and f2 mean source frequency signals of a transmission band, respectively.

The signal input to the second path part is reduced by the third-order distortion signal generator 103 made of a diode, and the third frequency intermodulation distortion component of the 2f1-f2 and 2f2-f1 frequency components is generated. . The third intermodulation distortion signal is adjusted through the variable attenuator 104 and the variable phaser 105 to adjust the magnitude and phase of the distortion component.

In order to compensate for the signal delay caused by the second path portion, a delay line 102 is inserted in the first path portion, and the third intermodulation distortion signal passing through the variable phase shifter 105 of the second path portion and the source of the first path portion are provided. The frequency signal is combined by the power combiner 106 and used as the input of the power amplifier 107.

The general power amplifier 107 generates a third order intermodulation distortion signal when a source frequency signal is input, and this component is a major cause of deterioration of the linearity of the power amplifier 107. However, the analog predistorter generates a signal for compensating for the third order intermodulation distortion signal generated by the power amplifier 107 through the second path portion and uses it as an input of the power amplifier 107, thereby providing linearity in the power amplifier 107. Can be increased.

However, since the variable attenuator 104 and the variable phaser 105 adjust the magnitude and phase of the 3rd order intermodulation distortion signal of 2f1-f2 and the 3rd order modulation modulation signal of 2f2-f1 simultaneously, There is a limit to compensate for the asymmetric distortion caused by the memory effect. Therefore, a method of compensating the memory effect of the power amplifier by adjusting the third order intermodulation distortion signals of 2f1-f2 and 2f2-f1, respectively, has been proposed to improve linearity.

2 is a circuit diagram illustrating an analog predistorter for independently adjusting a third-order intermodulation distortion signal according to the related art, and includes a first signal generator 200a, a second signal generator 200b, a combiner 200c, and a gain amplifier. 201, delay line 202, low pass filter 203, distortion signal generator 204, first frequency mixer 204a, second frequency mixer 204b, variable attenuator 204c, variable phaser 204d, a first power combiner 204e, a second power combiner 205, and a power amplifier 206. Referring to FIG. 2, an analog predistorter according to an exemplary embodiment will be described.

Referring to FIG. 2, the input signals f1 and f2 from the first signal generator 200a and the second signal generator 200b are combined and output through the combiner 200c. Here, f1 and f2 mean source frequency signals of a transmission band, respectively. The signal generated by the signal generator 200 is used as an input of the gain amplifier 201 and the distortion signal generator 204. The two source frequency signals summed through the combiner 200c are used as inputs of the gain amplifier 201. The output of the gain amplifier 201 not only amplifies the source frequency component but also generates a signal having a certain magnitude at the frequency of the difference between the two source frequencies. The output of the gain amplifier 201 is used as the input of the delay line 202 to compensate for the signal delay of the distortion signal generator 204, and only the frequency components of the two source frequency differences are passed through the low pass filter 203. The distortion signal generator 204 is used to generate the distortion signal.

The signals input to the distortion signal generator 204 are used as inputs of the first frequency mixer 204a and the second frequency mixer 204b, and the low pass filter 203 and the signal of the first signal generator 200a. The output signals at < RTI ID = 0.0 >) < / RTI > The signal of the second signal generator 200b and the output signal of the low pass filter 203 are mixed to generate a third order intermodulation distortion component of the 2f1-f2 frequency component.

The generated third-order intermodulation distortion components are adjusted through the variable attenuator 204c and the variable phaser 204d, and the magnitude and phase of the distortion components are adjusted and summed through the first power combiner 204e. The output of the first power combiner 204e is the same as the distortion component of a typical analog predistorter, but unlike the conventional analog predistorter, the output of the first (2f2-f1) and lower (2f1-f2) cubic intermodulation distortion components There is a characteristic that can adjust the phase individually.

The distortion signal output through the first power combiner 204e and the output of the delay line 202 are summed through the second power combiner 205 and used to improve linearity of the power amplifier 206. This analog predistorter that independently adjusts the third-order intermodulation components can compensate for the memory effect of the power amplifier because it can adjust the upper and lower third-order intermodulation distortion components independently, but the circuit is complex and the broadband modulation signal Due to noise generation during down-conversion or up-conversion, it is difficult to expect a large linearity improvement.

The conventional analog predistorter improves linearity of a power amplifier by using a third-order intermodulation distortion signal generated by a third-order distortion signal generator, and removes a third-order intermodulation distortion component generated by the power amplifier itself. The signal generated by the third-order distortion generator made of the diode is controlled by using a variable attenuator and a variable phaser. Since the upper and lower third-order intermodulation components are controlled at the same time, the third-order intermodulation distortion component is asymmetric memory. There was a problem that it is difficult to linearize effectively. In addition, the analog predistorter that independently adjusts the conventional third-order intermodulation distortion signal has a problem in that a structure is complicated and many parameters to be adjusted are added as various circuits are added to compensate for a memory effect.

Accordingly, an object of the present invention is to provide an analog predistortion system and method for effectively compensating the memory effect of a power amplifier while using a low supply voltage and having a simple structure. There is this.

In order to achieve the above object, a first aspect of the present invention provides a first power divider for distributing a signal input to a power amplifier into a first signal and a second signal, and receiving and distributing a second signal into a plurality of signals to a transistor. A second path unit for generating a plurality of distortion signals having different delays and combining the plurality of distortion signals using the configured plurality of distortion generators, and receiving the first signal as much as the delay in the second path unit; A predistortion system for compensating for the memory effect of a power amplifier comprising a first path portion for delaying a signal and a first power combiner for coupling the outputs of the first path portion and the second path portion.

In addition, the plurality of distortion generators composed of the transistor provides a predistortion system for controlling the magnitude of the plurality of distortion signals by adjusting the collector bias voltage.

The second path unit may further include a variable attenuator configured to adjust a magnitude of the combined distortion signal; And a variable phaser for adjusting the phase of the combined distortion signal.

In addition, the plurality of distortion signals provide a predistortion system including a reference delay distortion signal, a distortion signal having a delay shorter than the reference delay distortion signal, and a distortion signal having a delay longer than the reference delay distortion signal.

The first path unit also provides a predistortion system including a delay line for compensating for signal delay in the second path unit.

The second path unit may include a second power divider that receives a second signal and distributes the plurality of signals into a plurality of signals, a plurality of distortion generators connected in parallel to receive and distort each of the plurality of signals, and a plurality of distortion generators, respectively. A plurality of delayers for time delaying the output of each of the plurality of distortion generators; And a second power combiner for coupling the outputs of the plurality of delayers.

The plurality of retarders also provide a predistortion system having different time delays from each other.

The plurality of distortion generators also provides a predistortion system consisting of transistors having a low supply voltage.

In order to achieve the above object, a second aspect of the present invention provides a method for distributing a signal input to a power amplifier into a first signal and a second signal, distributing a second signal into a plurality of signals, and a plurality of signals. Generating a plurality of distortion signals by a plurality of distortion generators each configured to receive inputs, delaying each of the plurality of distortion signals to have a different delay, and generating a third signal by combining the plurality of delayed signals And delaying the first signal by the third signal, and combining the delayed first signal and the third signal. .

The generating of the plurality of distortion signals may further include adjusting the size of the plurality of distortion signals by adjusting collector bias voltages of the plurality of distortion generators including transistors.

The generating of the third signal may further include generating a third signal by adjusting magnitudes and phases of the plurality of combined signals.

The delaying may include delaying the plurality of delayed signals to include a reference delay distortion signal, a distortion signal having a delay shorter than the reference delay distortion signal, and a distortion signal having a delay longer than the reference delay distortion signal. Provided is a predistortion generating method comprising.

According to the present invention, a distortion signal based on a transistor is connected in parallel to create a distortion signal, and a delay line having a different signal delay from a reference delay line is connected to an amplifier output to add a different delay to the distortion signal, or By subtracting the memory signal to the distortion signal, a low supply voltage is used, and a simple structure can effectively compensate for the memory effect of the power amplifier.

In addition, there is an effect that the size of the distortion signal can be easily adjusted by adjusting the collector bias voltage of the transistor constituting the distortion generator.

In addition, since only one variable attenuator and a variable phaser are used in the predistortion system, it is possible to obtain excellent performance while reducing power consumption.

1 is a circuit diagram illustrating a general analog predistorter according to a conventional embodiment.
2 is a circuit diagram illustrating an analog predistorter for independently adjusting a third order intermodulation distortion signal according to the related art.
3 is a circuit diagram illustrating an analog predistortion system for compensating memory effects of a transistor-based power amplifier according to an embodiment of the present invention.
4 is a circuit diagram illustrating an analog predistortion system for compensating for a memory effect of a transistor-based power amplifier according to an embodiment of the present invention.
5 is a flowchart illustrating a predistortion generating process for compensating for a memory effect of a power amplifier according to an exemplary embodiment of the present invention.
6 is an output power according to a collector bias voltage of a transistor-based distortion generator when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal; It is a graph showing the characteristics of the third order intermodulation distortion component IM3, the fifth order intermodulation distortion component IM5, and the current I _CC flowing through the collector.
7 is a collector of a first distortion generator, a second distortion generator, and a third distortion generator when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal. A graph showing the output spectrum of the second power combiner according to the bias voltages V _CC1 , V _CC2 , and V _CC3 .
Fig. 8 shows a typical analog predistorter (CAPD) and an analog predistortion system (MCAPD) for compensating memory effects when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal. Graph showing the output spectrum.
9 illustrates a general analog predistorter (CAPD) and a memory effect according to an embodiment of the present invention when a two-tone signal having a center frequency of 2.14 GHz and a two-tone signal having a tone spacing of 2 MHz is used as an input signal. A graph showing the output spectrum before and after linearization of a power amplifier using an analog predistorter (MCAPD) to compensate for this problem.
10 shows an output spectrum of a general analog predistorter (CAPD) and an analog predistortion system (MCAPD) for compensating memory effects when a WCDMA signal having a center frequency of 2.14 GHz and a 5 MHz bandwidth is used as an input signal. Is a graph.
FIG. 11 shows a general analog predistorter (CAPD) before and after linearization at an output power of 34 dBm and an analog predistor to compensate for a memory effect when a WCDMA signal having a center frequency of 2.14 GHz and a 5 MHz bandwidth is used as an input signal. A graph showing the output spectrum of the distortion system (MCAPD).
12 is a graph showing ACLR at an offset of ± 5 MHz before and after linearization according to an output power of a power amplifier when a center frequency is 2.14 GHz and a WCDMA signal having a 5 MHz bandwidth is used as an input signal.
FIG. 13 is a graph showing output spectra before and after linearization at an output power of 34 dBm when a 4-carrier WCDMA signal having a center frequency of 2.14 GHz and a 20 MHz bandwidth is used as an input signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

3 is a circuit diagram illustrating an analog predistortion system for compensating a memory effect of a transistor-based power amplifier according to an embodiment of the present invention. And a signal generator 302 and a first power combiner 303.

The distortion signal generator 302 includes a second power divider 302a, a first distortion generator 302b, a second distortion generator 302c, a third distortion generator 302d, a second delay line 302e, and a third A delay line 302f, a fourth delay line 302g, a second power combiner 302h, a variable attenuator 302i and a variable phaser 303j. The first distortion generator 302b, the second distortion generator 302c, and the third distortion generator 302d are manufactured using the same transistor. Each distortion generator based on a transistor has a different magnitude of distortion components depending on the collector bias voltage.

The first power divider 300 divides the input signal into two paths, and the second power divider 302a uses the signal to use the output of the first power divider 300 as an input of each distortion signal generator 302. Give out. Each of the distortion signals generated by the distortion generators 302 (b), 302 (c), and 302 (d) has different delays between the distortion signals while passing through delay lines having different delays.

The delay lines of the distortion signal generator 302 are second delay lines 302e having a delay shorter by Δτ and a fourth delay lines having a delay longer by Δτ with respect to the third delay line 302f as a reference. 302g. Distortion signals having different delays are summed through the second power combiner 302h, so that the distortion signal output from the second power combiner 302h has a memory component.

The distortion signal having the memory component passes through the variable attenuator 302i and the variable phaser 302j, and the magnitude and phase of the distortion component are adjusted, and the reference delay? Of the distortion signal generator is passed through the first power combiner 303. _{It adds} up with the input signal passing through the delay line 301 having _N ).

Unlike the conventional technology using a variable attenuator and a variable phaser for each distortion generator, the present invention has an effect of simple and excellent performance by using a single variable attenuator and a variable phase shifter.

4 is a circuit diagram illustrating an analog predistortion system for compensating memory effects of a transistor-based power amplifier according to an embodiment of the present invention. The signal generator 400, the first power divider 401, and the first path are illustrated in FIG. The unit 402 includes a second path unit 403, a first power combiner 404, and a power amplifier 405.

The first path unit 402 includes a first delay line 402a, and the second path unit 403 includes a second power divider 403a, a first distortion generator 404b, a second distortion generator 403c, Third distortion generator 403d, second delay line 403e, third delay line 403f, fourth delay line 403g, second power combiner 403h, variable attenuator 403i and variable phaser ( 403j).

The source signal output from the signal generator 400 is divided into a first path part 402 and a second path part 403 through the first power divider 401. The second power divider 403a of the second path unit 403 distributes the signal coming from the first power divider 401 to the input of each distortion generator in phase. The first distortion generator 403b, the second distortion generator 403c, and the third distortion generator 403d are manufactured using the same transistor.

Each of the distortion generators not only amplifies the input signal but also generates a distortion signal, and the distortion signal output from the second distortion generator 403c passes through the third delay line 403f having a constant length. Since the first distortion generator 403b uses the same element as the second distortion generator 403c, it not only amplifies the source signal but also generates distortion components, and the second delay line 403e uses the third delay line 403f. By using a transmission line shorter than), the signal delay is shorter than the signal delay of the output of the second distortion generator 403c.

In such a circuit, the first distortion generator 403b, the third distortion generator 403d, the second delay line 403e and the fourth delay line 403g are symmetrically positioned and perform the same function. However, the fourth delay line 403g uses a transmission line longer than the third delay line 403f so that the signal delay is longer than the signal delay of the output of the second distortion generator 403c.

The distortion components passing through the different delay lines are combined through the second power combiner 403h, and the magnitude and phase of the distortion components are adjusted through the variable attenuator 403i and the variable phaser 403j.

Each distortion generator based on a transistor has a different magnitude of distortion components depending on the collector bias voltage. Each of the distortion components generated by the distortion generators generates a signal having a different phase difference through different phases, and a distortion signal having a memory effect is generated through the second power combiner 403h. The distortion components with these memory components are used to compensate for the memory effect of the power amplifier 405.

The distortion components with memory components are then summed through the first power combiner 404 with the source signal passing through the first delay line 402a and used as an input of the power amplifier 405.

5 is a flowchart illustrating a predistortion generating process for compensating for a memory effect of a power amplifier according to an exemplary embodiment of the present invention. In operation 510, a signal input to the power amplifier is separated into a first signal and a second signal. In operation 520, the first signal divides the second signal into a plurality of signals. In operation 530, each of the separated signals is input to generate a plurality of distortion signals by a plurality of distortion generators composed of transistors. The plurality of distortion generators composed of transistors adjust the collector bias voltage of the transistor to adjust the magnitude of the plurality of distortion signals. In operation 540, each of the plurality of distortion signals is delayed to have a different delay from each other. The delayed plurality of signals may be delayed to include a reference delay distortion signal, a distortion signal having a delay shorter than the reference delay distortion signal, and a distortion signal having a delay longer than the reference delay distortion signal. In operation 550, a third signal is generated by combining the delayed signals. The plurality of signals may be combined and then adjusted in magnitude and phase to generate a third signal. In step 560, the first signal is delayed by the third signal. That is, the first signal may be delayed based on the reference delayed distortion signal. In step 570, the delayed first and third signals are combined. The combined signal can be input to a power amplifier to compensate for the memory effect.

6 is an output power according to a collector bias voltage of a transistor-based distortion generator when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal; It is a graph showing the characteristics of the third order intermodulation distortion component IM3, the fifth order intermodulation distortion component IM5, and the current I _CC flowing through the collector. In the graph of FIG. 6, the third and fifth order intermodulation distortion components are generated according to the collector bias voltage. In particular, the third and fifth order intermodulation distortion components are generated when the collector bias voltage is in the range of 4V to 4.8V. It can be seen that a lot occurs. This shows that a transistor-based distortion generator can be used as a distortion signal generator.

7 is a collector of a first distortion generator, a second distortion generator, and a third distortion generator when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal. A graph showing the output spectrum of the second power combiner according to the bias voltages V _CC1 , V _CC2 , and V _CC3 . As the collector voltage of each distortion generator is adjusted, the third-order and fifth-order intermodulation distortion components appear asymmetrically due to the memory effect of the distortion components.

Fig. 8 shows a typical analog predistorter (CAPD) and an analog predistortion system (MCAPD) for compensating memory effects when a two-tone signal having a center frequency of 2.14 GHz and a tone spacing of 2 MHz is used as an input signal. Graph showing the output spectrum. While the output of a typical analog predistorter has the same magnitude in the upper and lower third-order intermodulation components, the output spectrum of the analog predistortion system to compensate for the memory effect is determined by the upper and lower 3 The differential intermodulation distortion component exhibits asymmetrical features.

9 illustrates a general analog predistorter (CAPD) and a memory effect according to an embodiment of the present invention when a two-tone signal having a center frequency of 2.14 GHz and a two-tone signal having a tone spacing of 2 MHz is used as an input signal. A graph showing the output spectrum before and after linearization of a power amplifier using an analog predistorter (MCAPD) to compensate for this problem. The power amplifier's output spectrum before being linearized at 34dBm of output power has a 3dB difference in the upper and lower third-order intermodulation distortion components due to memory effects. When a typical analog predistorter (CAPD) is used, the upper and lower third-order intermodulation distortion components improve linearity up to about -58.5 dBc. On the other hand, when the analog predistortion system (MCAPD) is used to compensate for the memory effect, both the upper and lower third-order intermodulation distortion components show good linearity of -72 dBc or more.

10 shows an output spectrum of a general analog predistorter (CAPD) and an analog predistortion system (MCAPD) for compensating memory effects when a WCDMA signal having a center frequency of 2.14 GHz and a 5 MHz bandwidth is used as an input signal. Is a graph. While the output of a typical analog predistorter shows a symmetrical spectrum from the center frequency, the output spectrum of an analog predistortion system to compensate for the memory effect is asymmetrical from the center frequency because it has a memory component. Characteristic

FIG. 11 shows a general analog predistorter (CAPD) and an analog predistor for compensating memory effects before and after linearization at an output power of 34 dBm when a WCDMA signal having a center frequency of 2.14 GHz and a 5 MHz bandwidth is used as an input signal. A graph showing the output spectrum of the distortion system (MCAPD). The power amplifier's output spectrum before being linearized at 34dBm output power shows asymmetrical spectra with memory effects. When the power amplifier is linearized using a typical predistorter, it shows an ACLR (adjacent channel leakage) of about -52 dBc at an offset of ± 5 MHz, but the linearization result using an analog predistortion system to compensate for the memory effect is ± 5 MHz. Excellent linearization results of about -60dBc or more at offset.

12 is a graph showing ACLR at an offset of ± 5 MHz before and after linearization according to an output power of a power amplifier when a center frequency is 2.14 GHz and a WCDMA signal having a 5 MHz bandwidth is used as an input signal. It can be seen that the linearization result using the analog predistorter for compensating the memory effect over the entire output range is superior to the linearization result of the conventional analog predistorter. It can achieve 30.1% efficiency at an output power of 38.2dBm.

FIG. 13 is a graph showing output spectra before and after linearization at an output power of 34 dBm when a 4-carrier WCDMA signal having a center frequency of 2.14 GHz and a 20 MHz bandwidth is used as an input signal. The linearization of the power amplifier using a typical predistorter shows an ACLR of about -44 dBc at an offset of ± 5 MHz. However, the linearization results using an analog predistortion system to compensate for memory effects show that ACLR is weak at an offset of ± 5 MHz. 55dBc or better shows good linearization results.

Modules, functional blocks or means of the present embodiment may be implemented in a variety of known elements, such as electronic circuits, integrated circuits, ASICs (Application Specific Integrated Circuit), each may be implemented separately, or two or more may be integrated into one Can be.

As described above, the embodiments have been described for the understanding of the present invention, but as will be appreciated by those skilled in the art, the present invention is not limited to the specific embodiments described herein, but variously without departing from the scope of the present invention. May be modified, changed and replaced. Therefore, it is intended that the present invention cover all modifications and variations that fall within the true spirit and scope of the present invention.

300: first power divider 301: first delay line
302: distortion signal generator 303: first power combiner
302a: second power divider 302b: first distortion generator
302c: second distortion generator 302d: third distortion generator
302e: second delay line 302f: third delay line
302g: fourth delay line 302h: second power combiner
302i: variable attenuator 303j: variable phase shifter

Claims (12)

A predistortion system for compensating for the memory effect of a power amplifier,
A first power divider for distributing the signal input to the power amplifier into a first signal and a second signal;
A second path unit receiving the second signal and distributing the signal into a plurality of signals to generate a plurality of distortion signals having different delays from each other by using a plurality of distortion generators composed of transistors, and combining the plurality of distortion signals;
A first path unit receiving the first signal and delaying the first signal by a delay in the second path unit; And
A first power combiner for coupling the output of the first path portion and the second path portion,
The plurality of distortion generators composed of the transistors adjust the collector bias voltages of the transistors to adjust the magnitudes of the plurality of distortion signals.
Predistortion system.
delete The method of claim 1,
The second path portion,
A variable attenuator for adjusting the magnitude of the combined distortion signal; And
A variable phaser for adjusting the phase of the combined distortion signal
Predistortion system.
The method of claim 1,
The plurality of distortion signals include a reference delay distortion signal, a distortion signal having a delay shorter than the reference delay distortion signal, and a distortion signal having a delay longer than the reference delay distortion signal.
Predistortion system.
The method of claim 1,
The first path portion,
A delay line for compensating for signal delay in the second path portion;
Predistortion system.
The method of claim 1,
The second path portion,
A second power divider receiving the second signal and distributing the signal into the plurality of signals;
A plurality of distortion generators connected in parallel to receive and distort each of the plurality of signals;
A plurality of delayers corresponding to each of the plurality of distortion generators and for delaying an output of each of the plurality of distortion generators; And
A second power combiner for coupling the outputs of the plurality of delayers
Predistortion system.
The method according to claim 6,
The plurality of delay units have different time delays from each other.
Predistortion system.
The method according to claim 6,
The plurality of distortion generators are composed of a transistor having a low supply voltage
Predistortion system.
A method of generating predistortion for compensating a memory effect of a power amplifier,
Dividing a signal input to the power amplifier into a first signal and a second signal;
Dividing the second signal into a plurality of signals;
Receiving each of the plurality of signals and generating a plurality of distortion signals by a plurality of distortion generators composed of transistors;
Delaying each of the plurality of distortion signals to have a different delay;
Combining the plurality of delayed signals to generate a third signal;
Delaying the first signal by the third signal;
Combining the delayed first signal and the third signal,
The generating of the plurality of distortion signals may include:
Adjusting the collector bias voltages of the plurality of distortion generators including the transistors to adjust the magnitudes of the plurality of distortion signals.
How predistortion occurs.
delete The method of claim 9,
Generating the third signal,
Generating the third signal by adjusting magnitudes and phases of the plurality of combined signals;
How predistortion occurs.
The method of claim 9,
The delaying step,
Delaying the plurality of delayed signals to include a reference delay distortion signal, a distortion signal having a delay shorter than the reference delay distortion signal, and a distortion signal having a delay longer than the reference delay distortion signal.
How predistortion occurs.

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