CN113572432A - Analog predistorter with adjustable memory compensation - Google Patents
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Abstract
The invention discloses an adjustable memory compensation analog predistorter, which comprises n paths of delay lines, n vector modulators, 1 power divider and 1 combiner, wherein the lengths from the 1 st path of delay line to the n th path of delay line are gradually increased, the length difference between two adjacent paths of delay lines is equal, and the n paths of delay lines are used as delay modules to delay signals output by n proper regulators and compensate the memory effect of a power amplifier; the method has the advantages that the nonlinear characteristic of the power amplifier can be calibrated, and simultaneously the memory effect of the power amplifier can be compensated.
Description
Technical Field
The present invention relates to an analog predistorter, and more particularly, to an analog predistorter with adjustable memory compensation.
Background
With the rapid development of communication technology, the fifth generation mobile communication technology (5G) has begun to be put into commercial use in communication systems, and the 5G communication technology has the characteristics of high data rate, low delay, large system capacity, large-scale equipment connection and the like. A radio frequency power amplifier (power amplifier for short) is used as one of core modules of a communication system, and nonlinear distortion of the radio frequency power amplifier is always a key problem for restricting the development of communication technology. The memory effect of the power amplifier can make the distortion component generated by the nonlinear characteristic of the power amplifier not constant, and the slight memory effect does not have a serious influence on the linearity of the power amplifier. That is, in the dual tone test, if the phase rotation angle of the third-order intermodulation component of the power amplifier is small and the amplitude fluctuation is not large with the increase of the tone interval, the memory effect of the power amplifier does not obviously affect the power ratio of the adjacent channels and can not be considered. However, when the ACPR (an adjacent channel Power ratio) of the upper and lower sidebands of the Power amplifier has a large asymmetry, even if the phase and amplitude distortion of the third-order and fifth-order intermodulation components is small, the influence of the memory effect on the Power amplifier cannot be ignored. Especially in a broadband communication system, under the input of broadband signals, the influence of the memory effect on the power amplifier is quite serious, and the quality of the communication system is directly influenced.
The memory effect of the power amplifier is analyzed from the angle of the time domain, and can be shown that the current output is not only a function of the input at the current moment, but also is related to the functions of the input and the output at the previous moments; from the analysis of the frequency domain, the memory effect of the power amplifier can be expressed as the asymmetry of the intermodulation products of the power amplifier, namely the amplitude and the phase of the intermodulation products of the upper sideband and the lower sideband are different. In the current 5G communication era, the bandwidth of signals is very wide, and the wide bandwidth is one of the main factors causing the memory effect of power amplifiers. Therefore, the memory effect of the compensation power amplifier has important significance in the communication field.
The existing power amplifier linearization techniques are mainly classified into Digital Predistortion (DPD) techniques and Analog Predistortion (APD) techniques. The research of the DPD technique is mature, has high precision, can dynamically calibrate the non-linear characteristic of the power amplifier in real time, and is widely used in current communication systems. However, if the DPD is used to compensate the memory effect of the power amplifier under the broadband signal, the speed of analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) devices has a very high requirement, the cost is greatly increased, and meanwhile, the large amount of data greatly increases the calculation amount of digital predistortion, consumes more calculation resources, significantly increases the power consumption, increases the system complexity, and sharply decreases the overall efficiency. The analog predistortion technology is an early linearization technology, has the advantages of simple structure, low power consumption, large bandwidth, small volume and low cost, and is widely applied to military affairs and satellite communication. The analog predistorter is a hot technique for solving the problem of the linearization of the current communication system by virtue of the advantages of simple structure, low power consumption, low cost, large bandwidth and the like. However, the traditional analog predistorter realizes linearization by setting a nonlinear compensation module, and has no delay module, so that the memory effect of the power amplifier cannot be compensated.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an analog predistorter with adjustable memory compensation, which can compensate the memory effect of a power amplifier while calibrating the nonlinear characteristic of the power amplifier.
The technical scheme adopted by the invention for solving the technical problems is as follows: an adjustable memory compensation analog predistorter comprises n delay lines, n vector modulators, 1 power divider and 1 combiner, wherein the lengths of the 1 st delay line to the nth delay line are gradually increased, the length difference between two adjacent delay lines is equal, and the length of the jth delay line is recorded as LjLet the delay time of the jth delay line be τjJ is 1, 2,3 … n, wherein the delay time τ of the 1 st delay line1＝L1V, representing the propagation velocity of the signal on the PCB circuit board,
c is the speed of light,. epsilon.r is the dielectric constant of the PCB circuit board material, and the delay time of the kth delay line is tauk＝(k-1)*Δτ+τ1Where k is 2,3 … n, Δ τ is the delay time added by the difference in length of the kth delay line relative to the 1 st delay line,
"+" is the sign of the multiplication operation; the power divider is provided with an input end and n output ends, each vector modulator is respectively provided with an input end, an output end and an adjusting end, the combiner is provided with n input ends and an output end, n output ports of the power divider are correspondingly connected with the input ends of the n vector modulators one by one, the output ends of the n vector modulators are correspondingly connected with one ends of n delay lines one by one, and the other end of the n delay lines is connected with one of the n input ends of the combinerThe input end of the power divider is used as the input end of the analog predistorter, and is used for connecting with the output end of a power amplifier and accessing a radio frequency input signal, the output end of the combiner is used as the output end of the analog predistorter and is used for connecting with the input end of the power amplifier and outputting a radio frequency output signal, when the power amplifier is subjected to predistortion, the input end of the analog predistorter is connected with the output end of the power amplifier, the output end of the analog predistorter is connected with the input end of the power amplifier, when the radio frequency input signal enters from the input end of the analog predistorter, the power divider divides the radio frequency input signal into n paths of signals to be output at n output ends in a one-to-one correspondence manner, the n paths of signals enter n vector modulators from the input ends of the n vector modulators one-to-one correspondence manner, vector modulation signals are obtained and then output, n paths of vector modulation signals output by the n vector modulators are correspondingly delayed through n paths of delay lines one by one, then are correspondingly input into n input ends of the combiner one by one, and are combined into one path through the combiner and then are output at the output end of the combiner.
The vector modulator is realized by adopting a circuit structure with a variable capacitance diode, the capacitance of the variable capacitance diode is changed by adjusting the bias voltage loaded externally, so that the phase shift amount of the vector modulator is changed, the phase of a signal accessed to the input end of the vector modulator is electrically adjusted to the delay effect, in the signal transmission process, the capacitance of the variable capacitance diode is changed by adjusting the external bias voltage of n vector modulators, and the electric adjustment is performed to the effect of compensating the memory effect of the power amplifier of n paths of delay lines. The vector modulator loads the bias voltage through the external power supply, and the capacitance of the variable capacitance diode is adjusted within the rated capacitance range of the variable capacitance diode based on the simulation predistortion effect, so that the compensation effect is adjustable, the simulation predistortion effect can be finely adjusted, and the predistortion effect is further improved.
Each vector modulator comprises a first rectangular microstrip line, a second rectangular microstrip line, a third rectangular microstrip line, a fourth rectangular microstrip line, a fifth rectangular microstrip line, a sixth rectangular microstrip line, a seventh rectangular microstrip line, an eighth rectangular microstrip line, a first T-shaped microstrip line, a second T-shaped microstrip line, a third T-shaped microstrip line, a first cross microstrip line, a first resistor, a first inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor and a varactor with the model of SMV2205-040LF, wherein the first T-shaped microstrip line, the second T-shaped microstrip line and the third T-shaped microstrip line respectively have a port 1, a port 2 and a port 3, the port 1 and the port 3 are symmetrical, the first cross microstrip line has a port 1, a port 2, a port 3 and a port 4, and the port 1 and the port 4 are symmetrical, the 2 port and the 3 port are symmetrical, one end of the first rectangular microstrip line is used for accessing an external bias voltage, the other end of the first rectangular microstrip line is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the second rectangular microstrip line, the other end of the second rectangular microstrip line is connected with the 1 port of the first T-shaped microstrip line, the 2 port of the first T-shaped microstrip line is connected with one end of the first capacitor, the other end of the first capacitor is grounded, the 3 port of the first T-shaped microstrip line is connected with the 1 port of the second T-shaped microstrip line, the 2 port of the second T-shaped microstrip line is connected with one end of the second capacitor, the other end of the second capacitor is grounded, and the 3 port of the second T-shaped microstrip line is connected with the 1 port of the third T-shaped microstrip line, a 2 port of the third T-shaped microstrip line is connected with one end of the third capacitor, the other end of the third capacitor is grounded, a 3 port of the third T-shaped microstrip line is connected with one end of the first inductor, the other end of the first inductor is connected with one end of the third rectangular microstrip line, the other end of the third rectangular microstrip line is connected with a 1 port of the first cross microstrip line, a 2 port of the first cross microstrip line is connected with one end of the fifth rectangular microstrip line, the other end of the fifth rectangular microstrip line is connected with one end of the fourth capacitor, the other end of the fourth capacitor is connected with one end of the fourth rectangular microstrip line, the other end of the fourth rectangular microstrip line is an input end of the vector modulator, and a 4 port of the first cross microstrip line is connected with one end of the sixth rectangular microstrip line, the other end of the sixth rectangular microstrip line is connected with one end of the fifth capacitor, the other end of the fifth capacitor is connected with one end of the seventh rectangular microstrip line, the other end of the seventh rectangular microstrip line is the output end of the vector modulator, the 3-port of the first cross microstrip line is connected with one end of the eighth rectangular microstrip line, the other end of the eighth rectangular microstrip line is connected with one end of the variable capacitance diode, and the other end of the variable capacitance diode is grounded. When the vector modulator is used in an analog predistorter, an input signal enters from an input port of a power divider, is divided into n branches and is output from n output ends of the power divider, a signal of each branch passes through the vector modulator and a delay line which are arranged behind the branch, when the vector modulator is connected with a signal of a corresponding path, the signal enters from one end of a fourth rectangular microstrip line, is output from the other end of the fourth rectangular microstrip line, passes through a fourth capacitor, enters from one end of a fifth rectangular microstrip line, is output from the other end of the fifth microstrip line, enters from a port 2 of a first cross microstrip line, is output from a port 3 of the first cross microstrip line, enters from one end of an eighth rectangular microstrip line, is output from the other end of the eighth rectangular microstrip line, passes through a varactor diode, changes a bias voltage V of the varactor diode, and changes the capacitance value of the varactor diode, the signal is enabled to obtain a phase characteristic, the signal with the phase characteristic is reflected back to the 3 ports of the first cross microstrip line, is output from the 4 ports of the first cross microstrip line, enters from one end of the sixth rectangular microstrip line, is output from the other end of the sixth rectangular microstrip line, passes through the fifth capacitor, enters from one end of the seventh rectangular microstrip line, is output from the other end of the seventh rectangular microstrip line, then passes through the delay line of the corresponding branch, finally the signal of each branch enters into the input end of the corresponding combiner, and is output from the output end after being combined by the combiner, the circuit structure of the vector modulator is formed by using two lumped elements of capacitors and inductors and microstrip lines, clutter can be effectively filtered, the stability of the whole circuit is improved, the direct current signal can be effectively prevented from influencing the impedance characteristic of the alternating current circuit part, and the vector modulator can be more practical and more practical than the circuit structure using a pure microstrip line under the condition of low frequency, Stable and saves materials.
The length of the first rectangular microstrip line is 1.11mm, the width of the first rectangular microstrip line is 3mm, the length of the second rectangular microstrip line is 1.11mm, the width of the second rectangular microstrip line is 3mm, the length of the third rectangular microstrip line is 1.11mm, the width of the third rectangular microstrip line is 3mm, the length of the fourth rectangular microstrip line is 1.11mm, the width of the fourth rectangular microstrip line is 3mm, the length of the fifth rectangular microstrip line is 1.11mm, the width of the fifth rectangular microstrip line is 3mm, the length of the sixth rectangular microstrip line is 1.11mm, the width of the sixth rectangular microstrip line is 3mm, the length of the seventh rectangular microstrip line is 1.11mm, the width of the seventh rectangular microstrip line is 3mm, the length of the eighth rectangular microstrip line is 1.11mm, the width of the eighth rectangular microstrip line is 3mm, the widths of the first T-shaped microstrip line are all 1.11mm, the widths of the first T-shaped microstrip line are all 1, 2 and 3, the widths of the second T-shaped microstrip line are all 1, 11, and the third T-shaped microstrip line is 1, and the cross-shaped microstrip line is 1.11mm, and the first cross-shaped microstrip line is formed by the second rectangular microstrip line, and the third T-shaped microstrip line is formed by 1, and the cross-shaped microstrip line is formed by 1, and 3, and the cross-shaped microstrip line is formed by 1, and the cross-shaped microstrip line is formed by the cross-shaped microstrip line, and the cross-shaped microstrip line is formed by the cross-shaped microstrip line, the microstrip, The width of 2 ports, 3 ports and 4 ports is 1.11mm, the resistance of first resistance be 550 ohm, the value of first inductance be 4700nH, first electric capacity hold the value and be 47pF, second electric capacity hold the value and be 47pF, third electric capacity hold the value and be 47pF, fourth electric capacity hold the value and be 47pF, fifth electric capacity hold the value and be 47 pF.
Compared with the prior art, the method has the advantages that the analog predistorter is formed by n delay lines, n vector modulators, 1 power divider and 1 combiner, the lengths from the 1 st delay line to the n th delay line are gradually increased, the length difference between two adjacent delay lines is equal, and the length of the jth delay line is recorded as LjLet the delay time of the jth delay line be τjWherein, the delay time tau of the 1 st delay line1＝L1V, representing the propagation velocity of the signal on the PCB circuit board,
c is the speed of light,. epsilon.r is the dielectric constant of the PCB circuit board material, and the delay time of the kth delay line isτk＝(k-1)*Δτ+τ1Where k is 2,3 … n, Δ τ is the delay time added by the difference in length of the kth delay line relative to the 1 st delay line,
the power divider is provided with an input end and n output ends, each vector modulator is respectively provided with an input end, an output end and an adjusting end, the combiner is provided with n input ends and an output end, n output ports of the power divider are correspondingly connected with the input ends of the n vector modulators one by one, the output ends of the n vector modulators are correspondingly connected with one ends of n delay lines one by one, the other ends of the n delay lines are correspondingly connected with the n input ends of the combiner one by one, the input end of the power divider is used as the input end of the analog predistorter and is used for being connected with the output end of the power amplifier to access a radio frequency input signal, the output end of the combiner is used as the output end of the analog predistorter and is used for being connected with the input end of the power amplifier to output a radio frequency output signal, when the power amplifier is predistorted, the input end of the analog predistorter is connected with the output end of the power amplifier, the output end of the analog predistorter is connected with the input end of the power amplifier, when a radio frequency input signal enters from the input end of the analog predistorter, the power divider divides the radio frequency input signal into n paths of signals to be output at n output ends in a one-to-one correspondence manner, the n paths of signals enter n vector modulators from the input ends of the n vector modulators one to one correspondence manner, at the moment, the n paths of vector modulation signals output by the n vector modulators are delayed one to one by n paths of delay lines and input into n input ends of the combiner one to one correspondence manner, the signals are output at the output ends of the combiner after being combined into one path by the combiner, during the signal transmission process, the n paths of delay lines are used as delay modules to delay the signals output by n proper amount of regulators, because the memory effect of the power amplifier shows that the power amplifier output at the current moment in the time domain not only depends on the power amplifier input at the current moment, but also depends on the input and the output of the power amplifiers at the previous moments, therefore, n delay lines are set as a plurality of delay lines with unequal lengths, a plurality of previous moments of the power amplifier are simulated, and the delay time of the delay lines is the same value due to the uniform length difference between two adjacent delay lines, so that the aim of delaying the power amplifier is achievedThe memory effect compensation is performed at the previous moment, the previous two moments and the previous n moments, so that the memory effect compensation method can compensate the memory effect of the power amplifier while calibrating the nonlinear characteristic of the power amplifier.
Drawings
FIG. 1 is a block diagram of an adjustable memory compensated analog predistorter of the present invention;
FIG. 2 is a circuit diagram of a vector modulator of the adjustable memory compensated analog predistorter of the present invention;
FIG. 3 is a simulation diagram of the delay effect of the 4-way delay line of the tunable memory compensated analog predistorter of the present invention;
fig. 4 is a diagram illustrating the measured effect of the adjustable memory compensated analog predistorter of the present invention on a wideband signal.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example (b): as shown in fig. 1, an analog predistorter with adjustable memory compensation includes n delay lines, n vector modulators, 1 power divider and 1 combiner, where the lengths of the 1 st delay line to the nth delay line gradually increase, the length difference between two adjacent delay lines is equal, and the length of the jth delay line is denoted as LjLet the delay time of the jth delay line be τjJ is 1, 2,3 … n, wherein the delay time τ of the 1 st delay line1＝L1V, representing the propagation velocity of the signal on the PCB circuit board,
c is the speed of light,. epsilon.r is the dielectric constant of the PCB circuit board material, and the delay time of the kth delay line is tauk＝(k-1)*Δτ+τ1Where k is 2,3 … n, Δ τ is the delay time added by the difference in length of the kth delay line relative to the 1 st delay line,
"+" is the sign of the multiplication operation; the power divider has an input terminal and n output terminals, and each vector modulator has an output terminalThe combiner is provided with n input ends and an output end, n output ports of the power divider are connected with the input ends of n vector modulators in a one-to-one corresponding manner, the output ends of the n vector modulators are connected with one ends of n delay lines in a one-to-one corresponding manner, the other ends of the n delay lines are connected with n input ends of the combiner in a one-to-one corresponding manner, the input end of the power divider is used as the input end of an analog predistorter and is connected with the output end of a power amplifier to access a radio frequency input signal, the output end of the combiner is used as the output end of the analog predistorter and is connected with the input end of the power amplifier to output a radio frequency output signal, the vector modulator is realized by adopting a circuit structure with a variable capacitance diode C6, the capacitance of the variable capacitance diode C6 is changed by adjusting an externally loaded bias voltage, so that the phase shift quantity of the vector modulator is changed, and the phase of the signal accessed to the input end of the vector modulator, electrically adjusting the delay effect; when the power amplifier is pre-distorted, the input end of the analog pre-distorter is connected with the output end of the power amplifier, the output end of the analog pre-distorter is connected with the input end of the power amplifier, when the radio frequency input signal enters from the input end of the analog pre-distorter, the power divider divides the radio frequency input signal into n paths of signals which are output at n output ends in a one-to-one correspondence manner, the n paths of signals enter n vector modulators one by one from the input ends of the n vector modulators, at the moment, the external bias voltage of the capacitance diode C6 in each vector modulator is changed to change the phase of 1 path of signal input into the vector modulator, the vector modulation signal is output after being obtained, the n paths of vector modulation signals output by the n vector modulators are delayed one by one through n paths of delay lines, the vector modulation signals are input into n input ends of the combiner one by one path and output at the output end of the combiner after being combined into one path, in the signal transmission process, the capacitance of the variable capacitance diode C6 is changed by adjusting the external bias voltage of the n vector modulators, the effect of the n-path delay line on compensating the memory effect of the power amplifier is electrically adjusted, and the n-path delay line is used as a main delay module to delay signals output by n proper regulators and compensate the memory effect of the power amplifier.
As shown in fig. 2, in the present embodiment, each vector modulator includes a first rectangular microstrip line L1, a second rectangular microstrip line L2, a third rectangular microstrip line L3, a fourth rectangular microstrip line L4, a fifth rectangular microstrip line L5, a sixth rectangular microstrip line L6, a seventh rectangular microstrip line L7, an eighth rectangular microstrip line L8, a first T-shaped microstrip line L9, a second T-shaped microstrip line L10, a third T-shaped microstrip line L11, a first cross microstrip line L12, a first resistor L13, a first inductor L14, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a cross varactor diode C9 with a model of SMV2205-040LF, the first T-shaped microstrip line L9, the second T-shaped microstrip line L10, and the third T-shaped microstrip line L11 have ports 1, 2, and 3, respectively, and a symmetrical first T-shaped microstrip port 12 has ports 1, and a symmetrical port 1 port with a cross-symmetrical port 12, The circuit comprises a 2 port, a 3 port and a 4 port, wherein the 1 port and the 4 port are symmetrical, the 2 port and the 3 port are symmetrical, one end of a first rectangular microstrip line L1 is used for accessing an external bias voltage, the other end of the first rectangular microstrip line L1 is connected with one end of a first resistor L13, the other end of the first resistor L13 is connected with one end of a second rectangular microstrip line L2, the other end of a second rectangular microstrip line L2 is connected with the 1 port of a first T-shaped microstrip line L9, the 2 port of the first T-shaped microstrip line L9 is connected with one end of a first capacitor C1, the other end of a first capacitor C1 is grounded, the 3 port of the first T-shaped microstrip line L9 is connected with the 1 port of a second T-shaped microstrip line L10, the 2 port of the second T-shaped microstrip line L10 is connected with one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, the 3 port of the second T-shaped microstrip L10 is connected with the 1 port of a third T-shaped microstrip line L11, a 2 port of a third T-shaped microstrip line L11 is connected with one end of a third capacitor C3, the other end of the third capacitor C3 is grounded, a 3 port of the third T-shaped microstrip line L11 is connected with one end of a first inductor L14, the other end of the first inductor L14 is connected with one end of a third rectangular microstrip line L3, the other end of a third rectangular microstrip line L3 is connected with a 1 port of a first cross microstrip line L12, a 2 port of a first cross microstrip line L12 is connected with one end of a fifth rectangular microstrip line L5, the other end of a fifth rectangular microstrip line L5 is connected with one end of a fourth capacitor C4, the other end of a fourth capacitor C4 is connected with one end of a fourth rectangular microstrip line L4, the other end of a fourth rectangular microstrip line 4 is an input end of a vector modulator, a 4 port of a first cross microstrip line L12 is connected with one end of a sixth rectangular microstrip line L6, and the other end of a sixth rectangular microstrip line L6 is connected with one end of a fifth capacitor C5, the other end of the fifth capacitor C5 is connected with one end of a seventh rectangular microstrip line L7, the other end of the seventh rectangular microstrip line L7 is the output end of the vector modulator, the 3-port of the first cross microstrip line L12 is connected with one end of an eighth rectangular microstrip line L8, the other end of the eighth rectangular microstrip line L8 is connected with one end of a varactor C6, and the other end of the varactor C6 is grounded.
In this embodiment, the length of the first rectangular microstrip line L1 is 1.11mm, the width thereof is 3mm, the length of the second rectangular microstrip line L2 is 1.11mm, the width thereof is 3mm, the length of the third rectangular microstrip line L3 is 1.11mm, the width thereof is 3mm, the length of the fourth rectangular microstrip line L4 is 1.11mm, the width thereof is 3mm, the length of the fifth rectangular microstrip line L5 is 1.11mm, the width thereof is 3mm, the length of the sixth rectangular microstrip line L6 is 1.11mm, the width thereof is 3mm, the length of the seventh rectangular microstrip line L7 is 1.11mm, the width thereof is 3mm, the length of the eighth rectangular microstrip line L8 is 1.11mm, the width thereof is 3mm, the widths of the 1 port, the 2 port and the 3 port of the first T-shaped microstrip line L9 are all 1.11mm, the 1 port, the 2 port and the 3 port of the second T-shaped microstrip line L10 are all 1.11mm, the width of the third rectangular microstrip line L11 is all 1, the width of the first cross-shaped microstrip line L4834, the first cross-shaped microstrip line is 1.11mm, the width of the cross-shaped microstrip line L2 port, the cross-shaped microstrip line L4834 is the cross-shaped microstrip line port, the cross-shaped microstrip line is 1, the cross-shaped microstrip line, the cross-shaped microstrip line is 1, the cross-shaped microstrip line is the cross-shaped microstrip line, the cross-shaped microstrip line is the cross-shaped, the resistance of first resistance L13 is 550 ohm, and the value of first inductance L14 is 4700nH, and first electric capacity C1 holds the value and is 47pF, and second electric capacity C2 holds the value and is 47pF, and third electric capacity C3 holds the value and is 47pF, and fourth electric capacity C4 holds the value and is 47pF, and fifth electric capacity C5 holds the value and is 47 pF.
The adjustable memory compensation analog predistorter provided by the invention is simulated by using the transient simulation function of ADS (automatic dependent surveillance broadcasting) under the condition that the working frequency is 3.5GHz, and during simulation, the adjustable memory compensation analog predistorter comprises 4 delay lines, wherein a simulation graph of the delay effect of a 2 nd delay line, a 3 rd delay line and a 4 th delay line relative to a 1 st delay line is shown in fig. 3, and in fig. 3, the delay effects of the 2 nd delay line, the 3 rd delay line and the 4 th delay line relative to the 1 st delay line are respectively delayed by 0.04ns, 0.1ns and 0.17ns, so that two adjacent delay lines in the adjustable memory compensation analog predistorter are uniform in delay and can accurately compensate the memory effect of a power amplifier.
Under the condition of 3.5GHz, the actual measurement broadband signal of the analog predistorter adopting the adjustable memory compensation is a 256QAM signal of 200MHz, the actual measurement effect graph is shown in figure 4, and the analog predistorter adopting the adjustable memory compensation comprises 4 paths of delay lines during actual measurement. In fig. 4, a first curve is an output curve of the power amplifier itself, a second curve and a third curve are output curves of the power amplifier after predistortion, and the difference between the second curve and the third curve is that external bias voltages of the vector modulators are different, where the external bias voltages of the second curve are 1.12V (1 st vector modulator), 2.03V (2 nd vector modulator), 1.67V (3 rd vector modulator), and 3.05V (4 th vector modulator), respectively; the third curve external bias voltage is 2.45V (1 st vector modulator), 4.31V (2 nd vector modulator), 5.13V (3 rd vector modulator), 1.86V (4 th vector modulator), respectively. Analysis of FIG. 4 reveals that: by changing the external bias voltage, the invention can indeed compensate the memory effect of the power amplifier and improve the nonlinear performance of the power amplifier.
Claims (4)
1. An adjustable memory compensation analog predistorter is characterized by comprising n delay lines, n vector modulators, 1 power divider and 1 combiner, wherein the lengths of the 1 st delay line to the nth delay line are gradually increased, the length difference between two adjacent delay lines is equal, and the length of the jth delay line is recorded as LjLet the delay time of the jth delay line be τjJ is 1, 2,3 … n, wherein the delay time τ of the 1 st delay line1＝L1V, v represents the propagation velocity of the signal on the PCB circuit board,
c is the speed of light,. epsilon.r is the dielectric constant of the PCB circuit board material, and the delay time of the kth delay line is tauk＝(k-1)*Δτ+τ1Where k is 2,3 … n, Δ τ is the delay time added by the difference in length of the kth delay line relative to the 1 st delay line,
"+" is the sign of the multiplication operation;
the power divider is provided with an input end and n output ends, each vector modulator is respectively provided with an input end, an output end and an adjusting end, the combiner is provided with n input ends and an output end, n output ports of the power divider are correspondingly connected with the input ends of the n vector modulators one by one, the output ends of the n vector modulators are correspondingly connected with one ends of n delay lines one by one, the other ends of the n delay lines are correspondingly connected with the n input ends of the combiner one by one, the input end of the power divider is used as the input end of the analog predistorter and is connected with the output end of the power amplifier to access a radio frequency input signal, and the output end of the combiner is used as the output end of the analog predistorter and is connected with the input end of the power amplifier to output a radio frequency output signal; when the power amplifier is pre-distorted, the input end of the analog pre-distorter is connected with the output end of the power amplifier, the output end of the analog pre-distorter is connected with the input end of the power amplifier, when a radio frequency input signal enters from the input end of the analog pre-distorter, the power divider divides the radio frequency input signal into n paths of signals which are output at n output ends in a one-to-one correspondence manner, the n paths of signals enter n vector modulators from the input ends of the n vector modulators one by one to obtain vector modulation signals and then are output, the n paths of vector modulation signals output by the n vector modulators are delayed one by n paths of delay lines and then are input into n input ends of the combiner one by one to be combined into one path by the combiner and then are output at the output ends of the combiner, and in the signal transmission process, the n paths of delay lines are used as delay modules to delay the signals output by n proper amount of regulators, and compensating the memory effect of the power amplifier.
2. The adjustable memory compensation analog predistorter of claim 1, characterized in that the vector modulator is implemented by using a circuit structure with varactor diodes, and the capacitance of the varactor diodes is changed by adjusting an externally loaded bias voltage, so as to change the phase shift amount of the vector modulator, so that the phase of a signal accessed at the input end of the vector modulator is electrically adjusted to the delay effect, and in the signal transmission process, the capacitance of the varactor diodes is changed by adjusting the external bias voltages of n vector modulators, so as to electrically adjust the effect of the n delay lines to compensate the memory effect of the power amplifier.
3. The analog predistorter of claim 2, wherein each of the vector modulators includes a first rectangular microstrip line, a second rectangular microstrip line, a third rectangular microstrip line, a fourth rectangular microstrip line, a fifth rectangular microstrip line, a sixth rectangular microstrip line, a seventh rectangular microstrip line, an eighth rectangular microstrip line, a first T-shaped microstrip line, a second T-shaped microstrip line, a third T-shaped microstrip line, a first cross microstrip line, a first resistor, a first inductor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a varactor of SMV2205-040LF type, wherein the first T-shaped microstrip line, the second T-shaped microstrip line, and the third T-shaped microstrip line have 1 port, 2 port, and 3 port, respectively, and the 1 port and 3 port are symmetric, and the first cross microstrip line has 1 port, 2 port, 3 port, 1 port, and 3 port symmetric, The device comprises a first rectangular microstrip line, a second rectangular microstrip line, a first resistor, a first capacitor, a second capacitor, a first T-shaped microstrip line, a second capacitor, a second rectangular microstrip line, a second T-shaped microstrip line, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein the 2 port, the 3 port and the 4 port of the first rectangular microstrip line are symmetrical, the 2 port and the 3 port are symmetrical, one end of the first resistor is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the second rectangular microstrip line, the other end of the second rectangular microstrip line is connected with an external bias voltage, the other end of the second rectangular microstrip line is connected with the 1 port of the first T-shaped microstrip line, the 2 port of the first T-shaped microstrip line is connected with one end of the first capacitor, the other end of the first capacitor is grounded, the 3 port of the second T-shaped microstrip line is connected with the 1 port of the third T-shaped microstrip line, the 2 port of the third T-shaped microstrip line is connected with one end of the third capacitor, the other end of the third capacitor is grounded, the 3 port of the third T-shaped microstrip line is connected with one end of the first inductor, the other end of the first inductor is connected with one end of the third rectangular microstrip line, the other end of the third rectangular microstrip line is connected with the 1 port of the first cross microstrip line, the 2 port of the first cross microstrip line is connected with one end of the fifth rectangular microstrip line, the other end of the fifth rectangular microstrip line is connected with one end of the fourth capacitor, the other end of the fourth capacitor is connected with one end of the fourth rectangular microstrip line, and the other end of the fourth rectangular microstrip line is the input end of the vector modulator, the 4 ports of the first cross microstrip line are connected with one end of the sixth rectangular microstrip line, the other end of the sixth rectangular microstrip line is connected with one end of the fifth capacitor, the other end of the fifth capacitor is connected with one end of the seventh rectangular microstrip line, the other end of the seventh rectangular microstrip line is the output end of the vector modulator, the 3 ports of the first cross microstrip line are connected with one end of the eighth rectangular microstrip line, the other end of the eighth rectangular microstrip line is connected with one end of the variable capacitance diode, and the other end of the variable capacitance diode is grounded.
4. The analog predistorter for adjustable memory compensation according to claim 3, wherein the first rectangular microstrip line has a length of 1.11mm and a width of 3mm, the second rectangular microstrip line has a length of 1.11mm and a width of 3mm, the third rectangular microstrip line has a length of 1.11mm and a width of 3mm, the fourth rectangular microstrip line has a length of 1.11mm and a width of 3mm, the fifth rectangular microstrip line has a length of 1.11mm and a width of 3mm, the sixth rectangular microstrip line has a length of 1.11mm and a width of 3mm, the seventh rectangular microstrip line has a length of 1.11mm and a width of 3mm, the eighth rectangular microstrip line has a length of 1.11mm and a width of 3mm, the first T-shaped microstrip line has a width of 1 port, a width of 2 port and a width of 3 port of 1.11mm, and the second T-shaped microstrip line has a width of 1.11mm and a width of 3 port of 1.11mm, the width of 1 port, 2 ports and 3 ports of third T shape microstrip line be 1.11mm, the width of 1 port, 2 ports, 3 ports and 4 ports of first cross microstrip line be 1.11mm, the resistance of first resistance be 550 ohm, the value of first inductance be 4700nH, first electric capacity hold the value and be 47pF, second electric capacity hold the value and be 47pF, third electric capacity hold the value and be 47pF, fourth electric capacity hold the value and be 47pF, fifth electric capacity hold the value and be 47 pF.
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