KR101114292B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device having a buried gate, comprising: forming an insulating film on a substrate having a cell region and a ferry region; Forming a photoresist pattern on the insulating layer using a per-open mask; A first etching step of etching the insulating layer using the photoresist pattern as an etch barrier; Etching the photoresist pattern so as to have an inclined sidewall profile; A third etching step of recessing the substrate using the etched photosensitive film pattern and the insulating film as an etch barrier; And forming a bit line in the cell region and simultaneously forming a ferrite in the ferry region. According to the present invention, the cell region and the recess are formed through primary, secondary and tertiary etching. As the boundary surface of the ferry region in contact with the inclined profile has an inclined profile, residues can be prevented from occurring in the interface between the cell region and the recessed ferry region in the process of simultaneously forming the bit line and the ferry gate. .

Cell area, ferry area, residues, recesses, bit lines, ferry gates

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

TECHNICAL FIELD This invention relates to the manufacturing technique of a semiconductor device. Specifically, It is related with the manufacturing method of the semiconductor device provided with the buried gate (BG).

As micronization progresses in the semiconductor process, various device characteristics and process implementations are becoming difficult. In particular, the formation of the gate structure, the bit line structure, and the contact structure is showing a limit as it goes down to 40 nm or less. For example, even if the structure is formed, it is possible to secure a resistance characteristic, a refresh (refresh) or a low fail that can satisfy the device characteristics. And breakdown voltage (BV) characteristics are present. Recently, the buried gate (BG) process, in which the gate is buried in the active region, is introduced to reduce parasitic capacitance, increase process margin, and minimize the formation of a smallest cell transistor. .

1 is a cross-sectional view of a semiconductor device having a buried gate according to the prior art.

Referring to FIG. 1, a method of manufacturing a semiconductor device having a buried gate according to the related art is described. After forming a buried gate 12 in a cell region of a substrate 11 having a cell region and a ferry region, the substrate of the ferry region is formed. After the ferrite gate 13 is formed on the (11), a series of processes of forming the bit line 14 in the cell region are sequentially performed. In this case, an insulating film 15 is interposed between the buried gate 12, the ferrite gate 13, and the bit line 14.

As such, there is a problem in that the process steps are increased by forming the structures disposed in the cell region and the ferry region according to the prior art through separate processes, thereby increasing the production cost of the semiconductor device and producing the yield. ) Causes a problem of deterioration.

In order to solve this problem, a technique of simultaneously forming the bit line 14 of the cell region and the ferrite 13 of the ferry region has been proposed after recessing the substrate 11 of the ferry region.

FIG. 2 is a cross-sectional view illustrating a semiconductor device having a buried gate according to the improved prior art, and FIG. 3 is an image illustrating a problem according to the improved prior art.

Referring to FIG. 2, a method of manufacturing a semiconductor device having a buried gate according to the improved technology according to the related art is described. After the buried gate 12 is formed in a cell region, the substrate 11 of the ferry region is recessed to a predetermined depth. )do. Subsequently, after the conductive film is formed over the entire surface of the substrate 11, the conductive film is selectively etched to form the bit line 14 in the cell region and the ferrite 13 is formed in the ferry region.

However, the semiconductor device according to the related art is improved between the cell region and the recessed ferry region by recessing the substrate 11 of the ferry region to simultaneously form the bit line 14 and the ferrigate 13. As the step occurs and the interface between them has a vertical profile, a large amount of residue remains at the interface between the cell region and the recessed ferry region in the process of forming the bit line 14 and the ferry gate 13. There is a problem that water (Residue, R) occurs (see reference numeral 'R' in FIGS. 2 and 3).

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and in the semiconductor device having a buried gate, a semiconductor device can be prevented from generating residues at an interface between a cell region and a recessed ferry region. The purpose is to provide a method.

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: forming an insulating film on a substrate having a cell region and a ferry region; Forming a photoresist pattern on the insulating layer using a per-open mask; A first etching step of etching the insulating layer using the photoresist pattern as an etch barrier; Etching the photoresist pattern so as to have an inclined sidewall profile; A third etching step of recessing the substrate using the etched photosensitive film pattern and the insulating film as an etch barrier; And forming a ferrite in the ferry region while forming a bit line in the cell region. The method may further include forming a plurality of buried gates in the substrate of the cell region before forming the insulating layer.

The primary, secondary and tertiary etching may be performed in situ in the same chamber, and the primary, secondary and tertiary etching may be performed by dry etching using plasma.

The primary and tertiary etching may proceed to have an anisotropic etching characteristic, and the secondary etching may proceed to have an isotropic etching characteristic.

The insulating layer may include an oxide layer, and the first etching may be performed using a mixed gas in which chlorine gas and methane fluoride gas are mixed.

The secondary etching may be performed using a mixed gas of chlorine gas and inert gas.

The substrate may include a silicon substrate, and the third etching may be performed using a mixed gas of hydrogen bromide gas and sulfur hexafluoride gas.

Based on the above-described problem solving means, the present invention simultaneously forms a bit line and a ferrigate as the interface between the cell region and the recessed ferry region has an inclined profile through primary, secondary and tertiary etching. In the process, the residue can be prevented from occurring in the interface between the cell region and the recessed ferry region.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

In the embodiment of the present invention to be described later, in the semiconductor device having a buried gate (BG) in order to simplify the process, the cell region and the recess in the process of simultaneously forming the bit line of the cell region and the ferrigate of the ferry region Provided is a method of manufacturing a semiconductor device capable of preventing residue from occurring at an interface where the ferry region is in contact. To this end, an embodiment of the present invention is characterized in that the interface between the cell region and the recessed ferry region is formed to have an inclined profile.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

As shown in FIG. 4A, after a hard mask pattern (not shown) is formed on a substrate 21 having a cell region and a ferry region, for example, a silicon substrate, the cell region is etched as a etch barrier. The substrate 21 is etched to form a plurality of trenches 22.

Next, after forming the cell gate insulating film 23 on the trench 22 surface, a cell gate electrode 24 for partially filling the trench 22 is formed on the cell gate insulating film 23. In this case, the cell gate insulating film 23 may be formed of an oxide film, for example, silicon oxide (SiO ₂ ), and the cell gate electrode 24 may be formed of a metallic film such as tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN). ) And the like.

Through the above-described process, a plurality of trenches 22 formed in the substrate 21, a cell gate insulating film 23 formed on the surface of the trench 22, and a cell gate partially filling the trench 22 on the cell gate insulating film 23 are formed. A buried gate 25 made of an electrode 24 may be formed.

Next, an insulating film 26 is formed over the entire surface of the substrate 21. The insulating layer 26 serves to protect the substrate 21 and the buried gate 25 of the cell region during the subsequent process and serves as a mask in the process of recessing the substrate 21 of the ferry region.

The insulating film 26 may be formed of various insulating materials. For example, it may be formed of any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film or a laminated film in which these are laminated.

Next, the photosensitive film pattern 27 is formed on the insulating film 26 by using a peri open mask.

As shown in FIG. 4B, a first etching process is performed to expose the substrate 21 of the ferry region by etching the insulating layer 26 using the photoresist pattern 27 as an etch barrier. Hereinafter, the reference numeral of the etched insulating film 26 is changed to '26A' and described.

The first etching process may be performed using a dry etching method, and the dry etching method may be a dry etching method using plasma. In this case, the first etching process may be performed to have an anisotropic etching characteristic so that the sidewalls of the photoresist pattern 27 and the insulating layer 26A have a vertical profile. For example, when a bias is applied to the top electrode positioned above the substrate 21 in the chamber and the bottom electrode positioned below the substrate 21, anisotropic etching characteristics may be induced. For reference, a bias applied to the top electrode is commonly referred to as source power, and a bias applied to the bottom electrode is referred to as bias power. The source power plays a role of generating plasma, and the bias power plays a role of accelerating particles in the plasma to enter the substrate 21. The etching gas may be adjusted (or selected) depending on the material of the insulating layer 26A.

For example, when the insulating film 26A is formed of an oxide film, the primary etching process may be performed using a mixed gas in which chlorine gas (Cl 2) and methane fluoride gas are mixed. In this case, CHF ₃ gas may be used as the methane fluoride gas. As such, the mixed gas in which the chlorine gas and the methane fluoride gas are mixed may be suppressed to the maximum loss of the inter-process photosensitive film pattern 27 as a gas combination capable of generating a large amount of polymer. If the photoresist pattern 27 is lost during the first etching process, the etching margin for the subsequent process may be reduced. This is because the photoresist pattern 27 acts as an etching barrier in the process of recessing the substrate 21 of the subsequent ferry region.

As shown in FIG. 4C, the secondary etching process is performed such that the sidewall of the photoresist pattern 27 has an inclined profile. This is because the boundary surface of the cell region and the recessed ferry region has an inclined profile in the process of recessing the substrate 21 of the subsequent ferry region. Hereinafter, the reference numeral of the photosensitive film pattern 27 having the profile of which the sidewall is inclined is changed to '27A' and described.

The secondary etching process may be performed using the same method as the primary etching process, that is, dry etching, and dry etching using plasma may be used as the dry etching method. In addition, the secondary etching process may be performed in situ in the same chamber as the primary etching process to simplify the process. In this case, it is preferable that the secondary etching process is performed to have an isotropic etching characteristic so that the sidewall of the photoresist pattern 27A has an inclined profile. For example, when the secondary etching process is performed by applying only source power to the chamber, the isotropic etching characteristic may be induced.

 The secondary etching process may be performed using a mixed gas of chlorine gas and inert gas, and argon gas (Ar) may be used as the inert gas.

As shown in FIG. 4D, a third etching process is performed to recess the substrate 21 in the ferry region with the photoresist pattern 27A and the insulating layer 26A as an etch barrier.

The third etching process may be performed using the same method as the first and second etching processes, that is, the dry etching method, and the dry etching method using plasma may be used as the dry etching method. In addition, the third etching process may be performed in situ in the same chamber as the first and second etching processes to simplify the process. In this case, in order to transfer the inclined sidewall profile of the photosensitive film pattern 27A to the substrate 21, the third etching process may be performed to have an anisotropic etching characteristic.

When the silicon substrate is used as the substrate 21, the third etching process may be performed using a mixed gas in which hydrogen bromide gas (HBr) and sulfur hexafluoride gas (SF ₆ ) are mixed.

Next, the photoresist pattern 27A remaining after the tertiary etching process is completed is removed. The photoresist pattern 27A may be removed through an ashing process.

Through the above-described process processes, that is, primary, secondary and tertiary etching processes, the interface between the cell region and the recessed ferry region may be formed to have an inclined profile (see FIG. 5). In this way, residues can be prevented from occurring at the interface between the subsequent processes.

As shown in FIG. 4E, the ferrite gate insulating film 34 is formed on the surface of the ferrite region substrate 21, and the bit line contact hole 28 is formed by partially etching the insulating layer 26A of the cell region.

Next, the first conductive layer 29 is formed on the entire surface of the substrate 21 to fill the bit line contact hole 28. In this case, the first conductive layer 29 may be formed of a silicon layer.

Next, the second conductive film 30 and the hard mask film 31 are sequentially formed on the first conductive film 29. In this case, the second conductive film 30 may be formed of a metallic film such as titanium or tungsten silicide, and the hard mask film 31 may be an insulating film, for example, a single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. Or they can be formed by the laminated film by which they were laminated.

As shown in FIG. 4F, the hard mask layer 31, the second conductive layer 30, the first conductive layer 29, and the ferry gate insulating layer 34 are selectively etched. Hereinafter, the reference numerals of the etched hard mask layer 31, the second conductive layer 30, the first conductive layer 29, and the ferry gate insulating layer 34 are denoted by '31A', '30A', '29A', and Change to '34A' and write down.

Through the above-described process, a bit line 32 having a structure in which the first conductive film 29A, the drafting film 30A, and the hard mask film 31A are sequentially stacked in the cell area is formed, and at the same time, the ferry is placed in the ferry area. A ferrogate 33 having a structure in which the gate insulating film 34A, the first conductive film 29A, the drafting film 30A, and the hard mask film 31A are sequentially stacked may be formed. At this time, as the boundary surface between the cell region and the recessed ferry region has an inclined profile, in the process of simultaneously forming the bit line 32 and the ferry gate 33, the boundary region between the cell region and the recessed ferry region is in contact with each other. Residues can be prevented from occurring.

5 is an image showing a comparison of the profile of the interface between the cell region and the recessed ferry region in the prior art and the embodiment of the present invention.

As shown in FIG. 5, in the prior art, the interface between the cell region and the recessed ferry region has a vertical profile, whereas in one embodiment of the present invention, the ferry may be formed through primary, secondary and tertiary etching processes. By recessing the substrate of the region, it can be confirmed that the interface profile that they contact is inclined.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a semiconductor device having a buried gate according to the prior art.

2 is a cross-sectional view of a semiconductor device having an embedded gate in accordance with an improved prior art.

Figure 3 is an image showing the problem according to the improved prior art.

4A to 4F are cross-sectional views illustrating a method of manufacturing a semiconductor device having a buried gate according to an embodiment of the present invention.

5 is an image showing a comparison of the profile of the interface between the cell region and the recessed ferry region in the prior art and the embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 substrate 22 trench

23: cell gate insulating film 24: cell gate electrode

25: buried gate 26, 26A: insulating film

27, 27A: Photoresist pattern 28: Bit line contact hole

29, 29A: first conductive film 30, 30A: second conductive film

31, 31A: Hard mask layer 32: Bit line

33: Ferrigate 34, 34A: Ferrigate insulating film

Claims (11)

Forming an insulating film on a substrate having a cell region and a ferry region; Forming a photoresist pattern on the insulating layer using a per-open mask; A first etching step of opening the substrate of the ferry region by etching the insulating layer using the photoresist pattern as an etch barrier; A second etching step of etching the photoresist pattern so that sidewalls of the photoresist pattern have an inclined profile; A third etching step of recessing the substrate using the etched photosensitive film pattern and the insulating film as an etch barrier; And Forming a bit line in the cell region and forming a ferrite in the ferry region Semiconductor device manufacturing method comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming a plurality of buried gates in the substrate of the cell region before forming the insulating film; And Forming a bit line contact hole by selectively etching the insulating layer of the cell region before forming the bit line in the cell region A semiconductor device manufacturing method further comprising. Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The first, second and third etching is performed by a dry etching method using a plasma. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the first and third etchings are performed to have anisotropic etching characteristics. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And the second etching proceeds to have isotropic etching characteristics. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, And the insulating film comprises an oxide film. Claim 8 was abandoned when the registration fee was paid. The method of claim 7, wherein The first etching is performed using a mixed gas of chlorine gas and methane fluoride gas mixture. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, The second etching is performed using a mixed gas of chlorine gas and inert gas mixed. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1, The substrate comprises a silicon substrate manufacturing method. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 10, The tertiary etching is performed using a mixed gas of hydrogen bromide gas and sulfur hexafluoride gas.

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